Urja Rannikko has uploaded a new change for review. ( https://review.coreboot.org/19615 )
Change subject: Add probe_dummy for chips that are not practical to probe
......................................................................
Add probe_dummy for chips that are not practical to probe
This is in preparation for read-only definition of a 27C256.
Change-Id: I327400e337d6ce600c4f0f165f328715f5b341e2
Signed-off-by: Urja Rannikko <urjaman(a)gmail.com>
---
M chipdrivers.h
M flashrom.c
2 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/15/19615/1
diff --git a/chipdrivers.h b/chipdrivers.h
index c85eac9..eeb9d27 100644
--- a/chipdrivers.h
+++ b/chipdrivers.h
@@ -27,6 +27,9 @@
#include "flash.h" /* for chipaddr and flashctx */
+/* flashrom.c */
+int probe_dummy(struct flashctx *flash);
+
/* spi.c */
int spi_aai_write(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
int spi_chip_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
diff --git a/flashrom.c b/flashrom.c
index 25e53f2..c8d477d 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -405,6 +405,18 @@
{0}, /* This entry corresponds to PROGRAMMER_INVALID. */
};
+/* This is a dummy probe for flash chips that cannot be probed for. */
+int probe_dummy(struct flashctx *flash)
+{
+ if (!chip_to_probe || strcmp(chip_to_probe, flash->chip->name)) {
+ msg_cdbg("Cant probe for this chip. Use 'flashrom -c %s' if you have one.\n", flash->chip->name);
+ return 0;
+ }
+ msg_cdbg("selected by user (Note: probing not possible or not implemented).\n");
+ return 1;
+}
+
+
#define SHUTDOWN_MAXFN 32
static int shutdown_fn_count = 0;
struct shutdown_func_data {
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I327400e337d6ce600c4f0f165f328715f5b341e2
Gerrit-PatchSet: 1
Gerrit-Project: flashrom
Gerrit-Branch: staging
Gerrit-Owner: Urja Rannikko <urjaman(a)gmail.com>
Urja Rannikko has uploaded a new change for review. ( https://review.coreboot.org/19614 )
Change subject: cli_common: Dont request reports from known-bad chip operations
......................................................................
cli_common: Dont request reports from known-bad chip operations
Change-Id: Ic4dc0d85534f2fcfe4dcb9733d4994c8853b48a7
Signed-off-by: Urja Rannikko <urjaman(a)gmail.com>
---
M cli_common.c
1 file changed, 15 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/14/19614/1
diff --git a/cli_common.c b/cli_common.c
index 71cc2dd..6bdc086 100644
--- a/cli_common.c
+++ b/cli_common.c
@@ -70,10 +70,12 @@
msg_cdbg("This chip's main memory can not be erased/written by design.\n");
}
+
if ((chip->tested.probe == BAD) || (chip->tested.probe == NT) ||
(chip->tested.read == BAD) || (chip->tested.read == NT) ||
(chip->tested.erase == BAD) || (chip->tested.erase == NT) ||
(chip->tested.write == BAD) || (chip->tested.write == NT)){
+ int untested = 0;
msg_cinfo("===\n");
if ((chip->tested.probe == BAD) ||
(chip->tested.read == BAD) ||
@@ -104,14 +106,20 @@
if (chip->tested.write == NT)
msg_cinfo(" WRITE");
msg_cinfo("\n");
+ untested = 1;
}
- msg_cinfo("The test status of this chip may have been updated in the latest development\n"
- "version of flashrom. If you are running the latest development version,\n"
- "please email a report to flashrom(a)flashrom.org if any of the above operations\n"
- "work correctly for you with this flash chip. Please include the flashrom log\n"
- "file for all operations you tested (see the man page for details), and mention\n"
- "which mainboard or programmer you tested in the subject line.\n"
- "Thanks for your help!\n");
+ if (untested) {
+ msg_cinfo("The test status of this chip may have been updated in the latest development\n"
+ "version of flashrom. If you are running the latest development version,\n"
+ "please email a report to flashrom(a)flashrom.org if any of the above operations\n"
+ "work correctly for you with this flash chip. Please include the flashrom log\n"
+ "file for all operations you tested (see the man page for details), and mention\n"
+ "which mainboard or programmer you tested in the subject line.\n"
+ "Thanks for your help!\n");
+ } else {
+ msg_cinfo("The test status of this chip may have been updated in the latest development\n"
+ "version of flashrom.\n");
+ }
}
}
--
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/19342 )
Change subject: layout: Add -i <region>[:<file>] support.
......................................................................
Patch Set 5:
> Looks like the patching in of -i files for write support got lost during
> rebase? Or maybe I just don't see where it happens...
Found it in the next commit ;)
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/19342 )
Change subject: layout: Add -i <region>[:<file>] support.
......................................................................
Patch Set 5:
Looks like the patching in of -i files for write support got lost during
rebase? Or maybe I just don't see where it happens...
--
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/17953 )
Change subject: Add option to read ROM layout from IFD
......................................................................
Patch Set 13: Code-Review+1
Ok sry for this, fixed my ifd and it works fine.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/17953 )
Change subject: Add option to read ROM layout from IFD
......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/#/c/17953/13/ich_descriptors.c
File ich_descriptors.c:
PS13, Line 934: "Flash_Descriptor",
: "BIOS",
: "Intel_ME",
: "GbE",
: "Platform_Data"
We should probably use the same names that `ifdtool -f` spits out.
For any reason their version got merged faster :-P
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/17953 )
Change subject: Add option to read ROM layout from IFD
......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/#/c/17953/13/ich_descriptors.c
File ich_descriptors.c:
PS13, Line 948: min(desc.content.NR + 1, ARRAY_SIZE(regions))
> In other words your GbE is at FLREGs[3]? like it usually is? but you
ok makes sense
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/17953 )
Change subject: Add option to read ROM layout from IFD
......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/#/c/17953/13/ich_descriptors.c
File ich_descriptors.c:
PS13, Line 948: min(desc.content.NR + 1, ARRAY_SIZE(regions))
> What I have is a Flash_Descriptor, a BIOS, and a GbE and no ME. content.NR
In other words your GbE is at FLREGs[3]? like it usually is? but you
exclude it by setting a short NR? Then fix your flash descriptor...
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