Change in flashrom[master]: flashcips: Add Spansion S25FL512S

[Bernhard Urban-Forster (Code Review)]

Bernhard Urban-Forster has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38596 )

Change subject: flashcips: Add Spansion S25FL512S
......................................................................

flashcips: Add Spansion S25FL512S

As found on the Tesla AP2.5 board.

Based on https://mail.coreboot.org/pipermail/flashrom/2013-June/011066.html

Tested with
```console
$ flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=16384 -r content.bin
```

Signed-off-by: Bernhard Urban-Forster 
Change-Id: Ifa9b7615951125b6bbc1f051370ef54896bf506c
---
M flashchips.c
1 file changed, 36 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/38596/1

diff --git a/flashchips.c b/flashchips.c
index 65dda0e..f4f6ad7 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -15968,6 +15968,42 @@
    },

{
+		.vendor		= "Spansion",
+		.name		= "S25FL512S",
+		.bustype	= BUS_SPI,
+		.manufacture_id	= SPANSION_ID,
+		.model_id	= SPANSION_S25FL512,
+		.total_size	= 65536, /* 512 Mb (=> 64 MB)) */
+		.page_size	= 256,
+		/* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_EAR7,
+		.tested		= TEST_OK_PREW,
+		.probe		= probe_spi_rdid,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { { 256 * 1024, 256} },
+				.block_erase = spi_block_erase_dc,
+			}, {
+				.eraseblocks = { { 256 * 1024, 256} },
+				.block_erase = spi_block_erase_d8,
+			}, {
+				.eraseblocks = { { 65536 * 1024, 1} },
+				.block_erase = spi_block_erase_60,
+			}, {
+				.eraseblocks = { { 65536 * 1024, 1} },
+				.block_erase = spi_block_erase_c7,
+			}
+		},
+		.printlock	= spi_prettyprint_status_register_bp2_ep_srwd, /* TODO: SR2 and many others */
+		.unlock		= spi_disable_blockprotect_bp2_srwd, /* TODO: various other locks */
+		.write		= spi_chip_write_256, /* Multi I/O supported, IGNORE for now */
+		.read		= spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
+		.voltage	= {2700, 3600},
+	},
+
+	{
    	.vendor		= "SyncMOS/MoselVitelic",
    	.name		= "{F,S,V}29C51001B",
    	.bustype	= BUS_PARALLEL,

[Bernhard Urban-Forster (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/38596

to look at the new patch set (#2).

Change subject: flashcips: Add Spansion S25FL512S
......................................................................

flashcips: Add Spansion S25FL512S

As found on the Tesla AP2.5 board.

Based on https://mail.coreboot.org/pipermail/flashrom/2013-June/011066.html

Tested with
```console
$ flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=16384 -r content.bin
```

Github issue: https://github.com/flashrom/flashrom/issues/121

Signed-off-by: Bernhard Urban-Forster 
Change-Id: Ifa9b7615951125b6bbc1f051370ef54896bf506c
---
M flashchips.c
1 file changed, 36 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/38596/2

[Bernhard Urban-Forster (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/38596

to look at the new patch set (#3).

Change subject: flashcips: Add Spansion S25FL512S
......................................................................

flashcips: Add Spansion S25FL512S

As found on the Tesla AP2.5 board.

Based on https://mail.coreboot.org/pipermail/flashrom/2013-June/011066.html

Tested with
```console
$ flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=16384 -r content.bin
```

Fixes https://github.com/flashrom/flashrom/issues/121

Signed-off-by: Bernhard Urban-Forster 
Change-Id: Ifa9b7615951125b6bbc1f051370ef54896bf506c
---
M flashchips.c
1 file changed, 36 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/38596/3

[David Hendricks (Code Review)]

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/38596 )

Change subject: flashcips: Add Spansion S25FL512S
......................................................................

Patch Set 3: Code-Review-1

(1 comment)

Thanks! I also happen to have one of these chips handy, and was able to get reads, erase, and writes working using native 4BA instructions (erase opcode DC).

I have a bit more testing to do and some more comments, so marking as -1 for now.

https://review.coreboot.org/c/flashrom/+/38596/3/flashchips.c 
File flashchips.c:

https://review.coreboot.org/c/flashrom/+/38596/3/flashchips.c@15979 
PS3, Line 15979: FEATURE_4BA_EAR7
I was able to get erase/writes working when using FEATURE_4BA_NATIVE

[Bernhard Urban-Forster (Code Review)]

Hello David Hendricks, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/38596

to look at the new patch set (#4).

Change subject: flashcips: Add Spansion S25FL512S
......................................................................

flashcips: Add Spansion S25FL512S

As found on the Tesla AP2.5 board.

Based on https://mail.coreboot.org/pipermail/flashrom/2013-June/011066.html

Tested with
```console
$ flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 -r content.bin
```

Signed-off-by: Bernhard Urban-Forster 
Change-Id: Ifa9b7615951125b6bbc1f051370ef54896bf506c
---
M flashchips.c
1 file changed, 27 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/38596/4

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/38596 )

Change subject: flashcips: Add Spansion S25FL512S
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/flashrom/+/38596/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/flashrom/+/38596/4//COMMIT_MSG@14 
PS4, Line 14: ```console
            : $ flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 -r content.bin
            : ```
Just one line and indent with four spaces or tab?

[Bernhard Urban-Forster (Code Review)]

Hello David Hendricks, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/38596

to look at the new patch set (#5).

Change subject: flashcips: Add Spansion S25FL512S
......................................................................

flashcips: Add Spansion S25FL512S

As found on the Tesla AP2.5 board.

Based on https://mail.coreboot.org/pipermail/flashrom/2013-June/011066.html

Tested with:
    flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 -r content.bin

Signed-off-by: Bernhard Urban-Forster 
Change-Id: Ifa9b7615951125b6bbc1f051370ef54896bf506c
---
M flashchips.c
1 file changed, 27 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/38596/5

[David Hendricks (Code Review)]

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/38596 )

Change subject: flashcips: Add Spansion S25FL512S
......................................................................

Patch Set 5: Code-Review-1

(1 comment)

https://review.coreboot.org/c/flashrom/+/38596/5/flashchips.c 
File flashchips.c:

https://review.coreboot.org/c/flashrom/+/38596/5/flashchips.c@15989 
PS5, Line 15989: 		},
oops, sorry if my comment on github was confusing. Please re-add the bulk erase opcodes (60 and c7). I only meant that I was able to successfully use dc as a block erase command with FEATURE_4BA_NATIVE.

[Bernhard Urban-Forster (Code Review)]

Hello David Hendricks, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/38596

to look at the new patch set (#6).

Change subject: flashcips: Add Spansion S25FL512S
......................................................................

flashcips: Add Spansion S25FL512S

As found on the Tesla AP2.5 board.

Based on https://mail.coreboot.org/pipermail/flashrom/2013-June/011066.html

Tested with:
    flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 -r content.bin

Signed-off-by: Bernhard Urban-Forster 
Change-Id: Ifa9b7615951125b6bbc1f051370ef54896bf506c
---
M flashchips.c
1 file changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/38596/6

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/38596 )

Change subject: flashcips: Add Spansion S25FL512S
......................................................................

Patch Set 6: Code-Review+1

(2 comments)

https://review.coreboot.org/c/flashrom/+/38596/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/flashrom/+/38596/6//COMMIT_MSG@7 
PS6, Line 7: flashcips
missing the 2nd `h`: flashcHips

https://review.coreboot.org/c/flashrom/+/38596/6/flashchips.c 
File flashchips.c:

https://review.coreboot.org/c/flashrom/+/38596/6/flashchips.c@15980 
PS6, Line 15980: TEST_OK_PREW
Did you test erase and write as well?

[David Hendricks (Code Review)]

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/38596 )

Change subject: flashcips: Add Spansion S25FL512S
......................................................................

Patch Set 6:

(2 comments)

Let's fix that tiny issue in the commit message and get this merged!

https://review.coreboot.org/c/flashrom/+/38596/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/flashrom/+/38596/6//COMMIT_MSG@7 
PS6, Line 7: flashcips
> missing the 2nd `h`: flashcHips

nice catch

https://review.coreboot.org/c/flashrom/+/38596/6/flashchips.c 
File flashchips.c:

https://review.coreboot.org/c/flashrom/+/38596/6/flashchips.c@15980 
PS6, Line 15980: TEST_OK_PREW
> Did you test erase and write as well?

Yep, and I verified them independently as well.

Change in flashrom[master]: flashchips: Add Spansion S25FL512S

[Bernhard Urban-Forster (Code Review)]

Hello Angel Pons, David Hendricks, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/38596

to look at the new patch set (#7).

Change subject: flashchips: Add Spansion S25FL512S
......................................................................

flashchips: Add Spansion S25FL512S

As found on the Tesla AP2.5 board.

Based on https://mail.coreboot.org/pipermail/flashrom/2013-June/011066.html

Tested with:
    flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 -r content.bin

Signed-off-by: Bernhard Urban-Forster 
Change-Id: Ifa9b7615951125b6bbc1f051370ef54896bf506c
---
M flashchips.c
1 file changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/38596/7

Change in flashrom[master]: flashchips: Add Spansion S25FL512S

[Bernhard Urban-Forster (Code Review)]

Bernhard Urban-Forster has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/38596 )

Change subject: flashchips: Add Spansion S25FL512S
......................................................................

Patch Set 7:

(5 comments)

What is missing to get this merged?

https://review.coreboot.org/c/flashrom/+/38596/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/flashrom/+/38596/4//COMMIT_MSG@14 
PS4, Line 14: ```console
            : $ flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 -r content.bin
            : ```
> Just one line and indent with four spaces or tab?

Ack

https://review.coreboot.org/c/flashrom/+/38596/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/flashrom/+/38596/6//COMMIT_MSG@7 
PS6, Line 7: flashcips
> nice catch

ha, thank you! :-)

https://review.coreboot.org/c/flashrom/+/38596/3/flashchips.c 
File flashchips.c:

https://review.coreboot.org/c/flashrom/+/38596/3/flashchips.c@15979 
PS3, Line 15979: FEATURE_4BA_EAR7
> I was able to get erase/writes working when using FEATURE_4BA_NATIVE

Ack

https://review.coreboot.org/c/flashrom/+/38596/5/flashchips.c 
File flashchips.c:

https://review.coreboot.org/c/flashrom/+/38596/5/flashchips.c@15989 
PS5, Line 15989: 		},
> oops, sorry if my comment on github was confusing. Please re-add the bulk erase opcodes (60 and c7). […]

Ah I see. I've added it back, and successfully re-ran my tests. Thank you!

https://review.coreboot.org/c/flashrom/+/38596/6/flashchips.c 
File flashchips.c:

https://review.coreboot.org/c/flashrom/+/38596/6/flashchips.c@15980 
PS6, Line 15980: TEST_OK_PREW
> Yep, and I verified them independently as well.

Yes, I've tested read, erase and write.

Change in flashrom[master]: flashchips: Add Spansion S25FL512S

[David Hendricks (Code Review)]

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/38596 )

Change subject: flashchips: Add Spansion S25FL512S
......................................................................

Patch Set 8: Code-Review+2

Change in flashrom[master]: flashchips: Add Spansion S25FL512S

[David Hendricks (Code Review)]

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/38596 )

Change subject: flashchips: Add Spansion S25FL512S
......................................................................

Patch Set 8:
> Patch Set 7:
>
> (5 comments)
>
> What is missing to get this merged?

Time. Thanks for your patience, and your patch!

Change in flashrom[master]: flashchips: Add Spansion S25FL512S

[David Hendricks (Code Review)]

David Hendricks has submitted this change. ( https://review.coreboot.org/c/flashrom/+/38596 )

Change subject: flashchips: Add Spansion S25FL512S
......................................................................

flashchips: Add Spansion S25FL512S

As found on the Tesla AP2.5 board.

Based on https://mail.coreboot.org/pipermail/flashrom/2013-June/011066.html

Tested with:
    flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 -r content.bin

Signed-off-by: Bernhard Urban-Forster 
Change-Id: Ifa9b7615951125b6bbc1f051370ef54896bf506c
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38596
Tested-by: build bot (Jenkins) 
Reviewed-by: David Hendricks 
---
M flashchips.c
1 file changed, 33 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  David Hendricks: Looks good to me, approved

diff --git a/flashchips.c b/flashchips.c
index 65dda0e..58dd4f3 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -15968,6 +15968,39 @@
    },

{
+		.vendor		= "Spansion",
+		.name		= "S25FL512S",
+		.bustype	= BUS_SPI,
+		.manufacture_id	= SPANSION_ID,
+		.model_id	= SPANSION_S25FL512,
+		.total_size	= 65536, /* 512 Mb (=> 64 MB)) */
+		.page_size	= 256,
+		/* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_NATIVE,
+		.tested		= TEST_OK_PREW,
+		.probe		= probe_spi_rdid,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { { 256 * 1024, 256} },
+				.block_erase = spi_block_erase_dc,
+			}, {
+				.eraseblocks = { { 65536 * 1024, 1} },
+				.block_erase = spi_block_erase_60,
+			}, {
+				.eraseblocks = { { 65536 * 1024, 1} },
+				.block_erase = spi_block_erase_c7,
+			}
+		},
+		.printlock	= spi_prettyprint_status_register_bp2_ep_srwd, /* TODO: SR2 and many others */
+		.unlock		= spi_disable_blockprotect_bp2_srwd, /* TODO: various other locks */
+		.write		= spi_chip_write_256, /* Multi I/O supported, IGNORE for now */
+		.read		= spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
+		.voltage	= {2700, 3600},
+	},
+
+	{
    	.vendor		= "SyncMOS/MoselVitelic",
    	.name		= "{F,S,V}29C51001B",
    	.bustype	= BUS_PARALLEL,