Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47218 )
Change subject: chipset_enable.c: change "Broadwell U Base" NT->OK ......................................................................
chipset_enable.c: change "Broadwell U Base" NT->OK
Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318 Signed-off-by: Nikolai Artemiev nartemiev@google.com --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/47218/1
diff --git a/chipset_enable.c b/chipset_enable.c index 4273478..77d07a1 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1997,7 +1997,7 @@ {0x8086, 0x9cc1, B_FS, NT, "Intel", "Haswell U Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc2, B_FS, NT, "Intel", "Broadwell U Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc3, B_FS, DEP, "Intel", "Broadwell U Premium", enable_flash_pch9_lp}, - {0x8086, 0x9cc5, B_FS, NT, "Intel", "Broadwell U Base", enable_flash_pch9_lp}, + {0x8086, 0x9cc5, B_FS, OK, "Intel", "Broadwell U Base", enable_flash_pch9_lp}, {0x8086, 0x9cc6, B_FS, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc7, B_FS, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp}, {0x8086, 0x9cc9, B_FS, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp},
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47218 )
Change subject: chipset_enable.c: change "Broadwell U Base" NT->OK ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/flashrom/+/47218/1/chipset_enable.c File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/47218/1/chipset_enable.c@2000 PS1, Line 2000: OK We use `DEP` (DEPends) for chipsets where the flash may not be freely accessible due to e.g. flash descriptor settings.
Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/47218
to look at the new patch set (#2).
Change subject: chipset_enable.c: change "Broadwell U Base" test state from NT to OK ......................................................................
chipset_enable.c: change "Broadwell U Base" test state from NT to OK
Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318 Signed-off-by: Nikolai Artemiev nartemiev@google.com --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/47218/2
Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/47218
to look at the new patch set (#3).
Change subject: chipset_enable.c: change "Broadwell U Base" NT->OK ......................................................................
chipset_enable.c: change "Broadwell U Base" NT->OK
Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318 Signed-off-by: Nikolai Artemiev nartemiev@google.com --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/47218/3
Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/47218
to look at the new patch set (#4).
Change subject: chipset_enable.c: change "Broadwell U Base" test state from NT to OK ......................................................................
chipset_enable.c: change "Broadwell U Base" test state from NT to OK
Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318 Signed-off-by: Nikolai Artemiev nartemiev@google.com --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/47218/4
Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/47218
to look at the new patch set (#5).
Change subject: chipset_enable.c: change "Broadwell U Base" test state from NT to DEP ......................................................................
chipset_enable.c: change "Broadwell U Base" test state from NT to DEP
Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318 Signed-off-by: Nikolai Artemiev nartemiev@google.com --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/47218/5
Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47218 )
Change subject: chipset_enable.c: change "Broadwell U Base" test state from NT to DEP ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/flashrom/+/47218/1/chipset_enable.c File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/47218/1/chipset_enable.c@2000 PS1, Line 2000: OK
We use `DEP` (DEPends) for chipsets where the flash may not be freely accessible due to e.g. […]
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47218 )
Change subject: chipset_enable.c: change "Broadwell U Base" test state from NT to DEP ......................................................................
Patch Set 5: Code-Review+2
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47218 )
Change subject: chipset_enable.c: change "Broadwell U Base" test state from NT to DEP ......................................................................
Patch Set 5: Code-Review+2
(1 comment)
https://review.coreboot.org/c/flashrom/+/47218/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/flashrom/+/47218/5//COMMIT_MSG@8 PS5, Line 8: Please include a commit msg body with something like:
``` Set device id=0x9cc5 to 'DEP' (DEPends) for chipsets where the flash may not be freely accessible due to e.g. flash descriptor settings. This avoids a warning where the chipset isn't tested when in fact it works well.
BUG=b:xxx BRANCH=none TEST=the line you used to confirm the warning went away ```
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47218 )
Change subject: chipset_enable.c: change "Broadwell U Base" test state from NT to DEP ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/flashrom/+/47218/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/flashrom/+/47218/5//COMMIT_MSG@8 PS5, Line 8:
Please include a commit msg body with something like: […]
I have several changes like this one, I usually reuse the last part of the commit message (changing only the board I've tested it on): https://review.coreboot.org/q/owner:th3fanbus%2540gmail.com+project:flashrom...
Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/47218
to look at the new patch set (#6).
Change subject: chipset_enable.c: mark "Broadwell U Base" as DEP ......................................................................
chipset_enable.c: mark "Broadwell U Base" as DEP
Tested probe/read/erase/write operations succeed with cros flashrom on rikku chromebook. Marking as DEP to follow convention for ME-enabled chipsets.
BUG=b:170906609 BRANCH=none TEST=Applied patch to cros flashrom and verified that `flashrom -VV` no longer prints a chipset warning on rikku
Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318 Signed-off-by: Nikolai Artemiev nartemiev@google.com --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/47218/6
Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/47218
to look at the new patch set (#7).
Change subject: chipset_enable.c: mark "Broadwell U Base" as DEP ......................................................................
chipset_enable.c: mark "Broadwell U Base" as DEP
Tested probe/read/erase/write operations succeed with cros flashrom on rikku. Marking as DEP to follow convention for ME-enabled chipsets.
BUG=b:170906609 BRANCH=none TEST=Applied patch to cros flashrom and verified that `flashrom -VV` no longer prints a chipset warning on rikku
Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318 Signed-off-by: Nikolai Artemiev nartemiev@google.com --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/47218/7
Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/47218
to look at the new patch set (#8).
Change subject: chipset_enable.c: mark "Broadwell U Base" as DEP ......................................................................
chipset_enable.c: mark "Broadwell U Base" as DEP
Tested probe/read/erase/write operations succeed with cros flashrom on rikku chromebox. Marking as DEP to follow convention for ME-enabled chipsets.
BUG=b:170906609 BRANCH=none TEST=Applied patch to cros flashrom and verified that `flashrom -VV` no longer prints a chipset warning on rikku
Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318 Signed-off-by: Nikolai Artemiev nartemiev@google.com --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/47218/8
Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47218 )
Change subject: chipset_enable.c: mark "Broadwell U Base" as DEP ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/flashrom/+/47218/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/flashrom/+/47218/5//COMMIT_MSG@8 PS5, Line 8:
I have several changes like this one, I usually reuse the last part of the commit message (changing […]
Done
Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/47218
to look at the new patch set (#10).
Change subject: chipset_enable.c: change "Broadwell U Base" NT->OK ......................................................................
chipset_enable.c: change "Broadwell U Base" NT->OK
Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318 Signed-off-by: Nikolai Artemiev nartemiev@google.com --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/47218/10
Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/47218
to look at the new patch set (#11).
Change subject: chipset_enable.c: mark "Broadwell U Base" as DEP ......................................................................
chipset_enable.c: mark "Broadwell U Base" as DEP
Tested probe/read/erase/write operations succeed with cros flashrom on rikku chromebox. Marking as DEP to follow convention for ME-enabled chipsets.
BUG=b:170906609 BRANCH=none TEST=Applied patch to cros flashrom and verified that `flashrom -VV` no longer prints a chipset warning on rikku
Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318 Signed-off-by: Nikolai Artemiev nartemiev@google.com --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/47218/11
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47218 )
Change subject: chipset_enable.c: mark "Broadwell U Base" as DEP ......................................................................
Patch Set 11: Code-Review+2
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47218 )
Change subject: chipset_enable.c: mark "Broadwell U Base" as DEP ......................................................................
Patch Set 11: -Code-Review
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47218 )
Change subject: chipset_enable.c: mark "Broadwell U Base" as DEP ......................................................................
Patch Set 11: Code-Review-2
(1 comment)
https://review.coreboot.org/c/flashrom/+/47218/11/chipset_enable.c File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/47218/11/chipset_enable.c@2005 PS11, Line 2005: OK, this switched back to "OK" again?
Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/47218
to look at the new patch set (#12).
Change subject: chipset_enable.c: mark "Broadwell U Base" as DEP ......................................................................
chipset_enable.c: mark "Broadwell U Base" as DEP
Tested probe/read/erase/write operations succeed with cros flashrom on rikku chromebox. Marking as DEP to follow convention for ME-enabled chipsets.
BUG=b:170906609 BRANCH=none TEST=Applied patch to cros flashrom and verified that `flashrom -VV` no longer prints a chipset warning on rikku
Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318 Signed-off-by: Nikolai Artemiev nartemiev@google.com --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/47218/12
Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47218 )
Change subject: chipset_enable.c: mark "Broadwell U Base" as DEP ......................................................................
Patch Set 12: Code-Review+1
(1 comment)
https://review.coreboot.org/c/flashrom/+/47218/11/chipset_enable.c File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/47218/11/chipset_enable.c@2005 PS11, Line 2005: OK,
this switched back to "OK" again?
Fixed - I must have messed it up in one of the rebases
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47218 )
Change subject: chipset_enable.c: mark "Broadwell U Base" as DEP ......................................................................
Patch Set 12: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47218 )
Change subject: chipset_enable.c: mark "Broadwell U Base" as DEP ......................................................................
Patch Set 12: Code-Review+2
Nikolai Artemiev has removed a vote from this change. ( https://review.coreboot.org/c/flashrom/+/47218 )
Change subject: chipset_enable.c: mark "Broadwell U Base" as DEP ......................................................................
Removed Code-Review+1 by Nikolai Artemiev nartemiev@google.com
Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/47218 )
Change subject: chipset_enable.c: mark "Broadwell U Base" as DEP ......................................................................
chipset_enable.c: mark "Broadwell U Base" as DEP
Tested probe/read/erase/write operations succeed with cros flashrom on rikku chromebox. Marking as DEP to follow convention for ME-enabled chipsets.
BUG=b:170906609 BRANCH=none TEST=Applied patch to cros flashrom and verified that `flashrom -VV` no longer prints a chipset warning on rikku
Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318 Signed-off-by: Nikolai Artemiev nartemiev@google.com Reviewed-on: https://review.coreboot.org/c/flashrom/+/47218 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Edward O'Callaghan quasisec@chromium.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved
diff --git a/chipset_enable.c b/chipset_enable.c index 7c98798..9205d0e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2002,7 +2002,7 @@ {0x8086, 0x9cc1, B_FS, NT, "Intel", "Haswell U Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc2, B_FS, NT, "Intel", "Broadwell U Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc3, B_FS, DEP, "Intel", "Broadwell U Premium", enable_flash_pch9_lp}, - {0x8086, 0x9cc5, B_FS, NT, "Intel", "Broadwell U Base", enable_flash_pch9_lp}, + {0x8086, 0x9cc5, B_FS, DEP, "Intel", "Broadwell U Base", enable_flash_pch9_lp}, {0x8086, 0x9cc6, B_FS, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9_lp}, {0x8086, 0x9cc7, B_FS, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp}, {0x8086, 0x9cc9, B_FS, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp},