Edward O'Callaghan submitted this change.
chipset_enable.c: mark "Broadwell U Base" as DEP
Tested probe/read/erase/write operations succeed with cros
flashrom on rikku chromebox. Marking as DEP to follow
convention for ME-enabled chipsets.
BUG=b:170906609
BRANCH=none
TEST=Applied patch to cros flashrom and verified that
`flashrom -VV` no longer prints a chipset warning on rikku
Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
M chipset_enable.c
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/chipset_enable.c b/chipset_enable.c
index 7c98798..9205d0e 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -2002,7 +2002,7 @@
{0x8086, 0x9cc1, B_FS, NT, "Intel", "Haswell U Sample", enable_flash_pch9_lp},
{0x8086, 0x9cc2, B_FS, NT, "Intel", "Broadwell U Sample", enable_flash_pch9_lp},
{0x8086, 0x9cc3, B_FS, DEP, "Intel", "Broadwell U Premium", enable_flash_pch9_lp},
- {0x8086, 0x9cc5, B_FS, NT, "Intel", "Broadwell U Base", enable_flash_pch9_lp},
+ {0x8086, 0x9cc5, B_FS, DEP, "Intel", "Broadwell U Base", enable_flash_pch9_lp},
{0x8086, 0x9cc6, B_FS, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9_lp},
{0x8086, 0x9cc7, B_FS, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp},
{0x8086, 0x9cc9, B_FS, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp},
To view, visit change 47218. To unsubscribe, or for help writing mail filters, visit settings.