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[S] Change in flashrom[main]: Provide an option to use PCI_ACCESS_ECAM to access pci register
by Kane Chen (Code Review) 15 Aug '24

15 Aug '24

Kane Chen has posted comments on this change by Kane Chen. ( https://review.coreboot.org/c/flashrom/+/83896?usp=email ) Change subject: Provide an option to use PCI_ACCESS_ECAM to access pci register ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/flashrom/+/83896?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I4549f87c8b01da0a1d3d8ce0b3b75c1f5fa2cbab Gerrit-Change-Number: 83896 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Thu, 15 Aug 2024 05:51:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in flashrom[main]: flashrom.c: Rename {erase|write}_by_layout_new as the only one
by Anastasia Klimchuk (Code Review) 15 Aug '24

15 Aug '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83852?usp=email ) Change subject: flashrom.c: Rename {erase|write}_by_layout_new as the only one ...................................................................... flashrom.c: Rename {erase|write}_by_layout_new as the only one We used to have two code paths for erase and write, so we had {erase|write}_by_layout in two variants: *_new and *_legacy. Now that legacy is removed, *_new can be renamed without *_new suffix. Change-Id: Ib21bf29e1993c4fc0516e76fde2ad283eedb50d2 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83852 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aarya <aarya.chaumal(a)gmail.com> Reviewed-by: Peter Marheine <pmarheine(a)chromium.org> --- M flashrom.c 1 file changed, 2 insertions(+), 14 deletions(-) Approvals: Aarya: Looks good to me, approved build bot (Jenkins): Verified Peter Marheine: Looks good to me, approved diff --git a/flashrom.c b/flashrom.c index 453a2bf..01a41c4 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1327,7 +1327,7 @@ return ret; } -static int erase_by_layout_new(struct flashctx *const flashctx) +static int erase_by_layout(struct flashctx *const flashctx) { bool all_skipped = true; const uint32_t flash_size = flashctx->chip->total_size * 1024; @@ -1370,12 +1370,7 @@ return ret; } -static int erase_by_layout(struct flashctx *const flashctx) -{ - return erase_by_layout_new(flashctx); -} - -static int write_by_layout_new(struct flashctx *const flashctx, +static int write_by_layout(struct flashctx *const flashctx, void *const curcontents, const void *const newcontents, bool *all_skipped) { @@ -1410,13 +1405,6 @@ return ret; } -static int write_by_layout(struct flashctx *const flashctx, - uint8_t *const curcontents, const uint8_t *const newcontents, - bool *all_skipped) -{ - return write_by_layout_new(flashctx, curcontents, newcontents, all_skipped); -} - /** * @brief Compares the included layout regions with content from a buffer. * -- To view, visit https://review.coreboot.org/c/flashrom/+/83852?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ib21bf29e1993c4fc0516e76fde2ad283eedb50d2 Gerrit-Change-Number: 83852 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in flashrom[main]: flashrom.c: Delete legacy erase and write logic
by Anastasia Klimchuk (Code Review) 15 Aug '24

15 Aug '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83846?usp=email ) Change subject: flashrom.c: Delete legacy erase and write logic ...................................................................... flashrom.c: Delete legacy erase and write logic Current code path for erase and write has been enabled in the tree since May 2023, which is more than 1 year ago (15 months ago), and legacy path has been disabled since the same time. Current logic has been officially released in v1.4.0 in July 2024. Change-Id: I08fd686fecf6a5313eea2d66b368661c664f4800 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83846 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aarya <aarya.chaumal(a)gmail.com> Reviewed-by: Peter Marheine <pmarheine(a)chromium.org> --- M erasure_layout.c M flashrom.c 2 files changed, 1 insertion(+), 369 deletions(-) Approvals: Aarya: Looks good to me, approved build bot (Jenkins): Verified Peter Marheine: Looks good to me, approved diff --git a/erasure_layout.c b/erasure_layout.c index ab54c12..a7eaa2d 100644 --- a/erasure_layout.c +++ b/erasure_layout.c @@ -151,7 +151,7 @@ * @param region_start pointer to start address of the region to align * @param region_end pointer to end address of the region to align * - * This function aligns start and end address of the region (in struct walk_info) + * This function aligns start and end address of the region * to some erase sector boundaries and modify the region start and end addresses * to match nearest erase sector boundaries. This function will be used in the * new algorithm for erase function selection. diff --git a/flashrom.c b/flashrom.c index dbf06cf..453a2bf 100644 --- a/flashrom.c +++ b/flashrom.c @@ -36,8 +36,6 @@ #include "chipdrivers.h" #include "erasure_layout.h" -static bool use_legacy_erase_path = false; - const char flashrom_version[] = FLASHROM_VERSION; static const struct programmer_entry *programmer = NULL; @@ -1329,250 +1327,6 @@ return ret; } -typedef int (*erasefn_t)(struct flashctx *, unsigned int addr, unsigned int len); -/** - * @private - * - * For read-erase-write, `curcontents` and `newcontents` shall point - * to buffers of the chip's size. Both are supposed to be prefilled - * with at least the included layout regions of the current flash - * contents (`curcontents`) and the data to be written to the flash - * (`newcontents`). - * - * For erase, `curcontents` and `newcontents` shall be NULL-pointers. - * - * The `chipoff_t` values are used internally by `walk_by_layout()`. - */ -struct walk_info { - uint8_t *curcontents; - const uint8_t *newcontents; - chipoff_t region_start; - chipoff_t region_end; - chipoff_t erase_start; - chipoff_t erase_end; -}; -/* returns 0 on success, 1 to retry with another erase function, 2 for immediate abort */ -typedef int (*per_blockfn_t)(struct flashctx *, const struct walk_info *, erasefn_t, bool *); - -static int walk_eraseblocks(struct flashctx *const flashctx, - struct walk_info *const info, - const size_t erasefunction, const per_blockfn_t per_blockfn, - bool *all_skipped) -{ - int ret; - size_t i, j; - bool first = true; - struct block_eraser *const eraser = &flashctx->chip->block_erasers[erasefunction]; - - info->erase_start = 0; - for (i = 0; i < NUM_ERASEREGIONS; ++i) { - /* count==0 for all automatically initialized array - members so the loop below won't be executed for them. */ - for (j = 0; j < eraser->eraseblocks[i].count; ++j, info->erase_start = info->erase_end + 1) { - info->erase_end = info->erase_start + eraser->eraseblocks[i].size - 1; - - /* Skip any eraseblock that is completely outside the current region. */ - if (info->erase_end < info->region_start) - continue; - if (info->region_end < info->erase_start) - break; - - /* Print this for every block except the first one. */ - if (first) - first = false; - else - msg_cdbg(", "); - msg_cdbg("0x%06"PRIx32"-0x%06"PRIx32":", info->erase_start, info->erase_end); - - erasefunc_t *erase_func = lookup_erase_func_ptr(eraser); - ret = per_blockfn(flashctx, info, erase_func, all_skipped); - if (ret) - return ret; - } - if (info->region_end < info->erase_start) - break; - } - msg_cdbg("\n"); - return 0; -} - -static int walk_by_layout(struct flashctx *const flashctx, struct walk_info *const info, - const per_blockfn_t per_blockfn, bool *all_skipped) -{ - const struct flashrom_layout *const layout = get_layout(flashctx); - const struct romentry *entry = NULL; - - *all_skipped = true; - msg_cinfo("Erasing and writing flash chip... "); - - while ((entry = layout_next_included(layout, entry))) { - const struct flash_region *region = &entry->region; - info->region_start = region->start; - info->region_end = region->end; - - size_t j; - int error = 1; /* retry as long as it's 1 */ - for (j = 0; j < NUM_ERASEFUNCTIONS; ++j) { - if (j != 0) - msg_cinfo("Looking for another erase function.\n"); - msg_cdbg("Trying erase function %zi... ", j); - if (check_block_eraser(flashctx, j, 1)) - continue; - - error = walk_eraseblocks(flashctx, info, j, per_blockfn, all_skipped); - if (error != 1) - break; - - if (info->curcontents) { - msg_cinfo("Reading current flash chip contents... "); - if (read_by_layout(flashctx, info->curcontents)) { - /* Now we are truly screwed. Read failed as well. */ - msg_cerr("Can't read anymore! Aborting.\n"); - /* We have no idea about the flash chip contents, so - retrying with another erase function is pointless. */ - error = 2; - break; - } - msg_cinfo("done. "); - } - } - if (error == 1) - msg_cinfo("No usable erase functions left.\n"); - if (error) { - msg_cerr("FAILED!\n"); - return 1; - } - } - if (*all_skipped) - msg_cinfo("\nWarning: Chip content is identical to the requested image.\n"); - msg_cinfo("Erase/write done.\n"); - return 0; -} - -static int erase_block(struct flashctx *const flashctx, - const struct walk_info *const info, const erasefn_t erasefn, - bool *all_skipped) -{ - const unsigned int erase_len = info->erase_end + 1 - info->erase_start; - const bool region_unaligned = info->region_start > info->erase_start || - info->erase_end > info->region_end; - uint8_t *backup_contents = NULL, *erased_contents = NULL; - int ret = 2; - - /* - * If the region is not erase-block aligned, merge current flash con- - * tents into a new buffer `backup_contents`. - */ - if (region_unaligned) { - backup_contents = malloc(erase_len); - erased_contents = malloc(erase_len); - if (!backup_contents || !erased_contents) { - msg_cerr("Out of memory!\n"); - ret = 1; - goto _free_ret; - } - memset(backup_contents, ERASED_VALUE(flashctx), erase_len); - memset(erased_contents, ERASED_VALUE(flashctx), erase_len); - - msg_cdbg("R"); - /* Merge data preceding the current region. */ - if (info->region_start > info->erase_start) { - const chipoff_t start = info->erase_start; - const chipsize_t len = info->region_start - info->erase_start; - if (read_flash(flashctx, backup_contents, start, len)) { - msg_cerr("Can't read! Aborting.\n"); - goto _free_ret; - } - } - /* Merge data following the current region. */ - if (info->erase_end > info->region_end) { - const chipoff_t start = info->region_end + 1; - const chipoff_t rel_start = start - info->erase_start; /* within this erase block */ - const chipsize_t len = info->erase_end - info->region_end; - if (read_flash(flashctx, backup_contents + rel_start, start, len)) { - msg_cerr("Can't read! Aborting.\n"); - goto _free_ret; - } - } - } - - ret = 1; - *all_skipped = false; - - msg_cdbg("E"); - - if (!flashctx->flags.skip_unwritable_regions) { - if (check_for_unwritable_regions(flashctx, info->erase_start, erase_len)) - goto _free_ret; - } - - unsigned int len; - for (unsigned int addr = info->erase_start; addr < info->erase_start + erase_len; addr += len) { - struct flash_region region; - get_flash_region(flashctx, addr, &region); - - len = min(info->erase_start + erase_len, region.end + 1) - addr; - - if (region.write_prot) { - msg_gdbg("%s: cannot erase inside %s region (%#08"PRIx32"..%#08"PRIx32"), skipping range (%#08x..%#08x).\n", - __func__, region.name, region.start, region.end, addr, addr + len - 1); - free(region.name); - continue; - } - - msg_gdbg("%s: %s region (%#08"PRIx32"..%#08"PRIx32") is writable, erasing range (%#08x..%#08x).\n", - __func__, region.name, region.start, region.end, addr, addr + len - 1); - free(region.name); - - if (erasefn(flashctx, addr, len)) - goto _free_ret; - if (check_erased_range(flashctx, addr, len)) { - msg_cerr("ERASE FAILED!\n"); - goto _free_ret; - } - } - - - if (region_unaligned) { - unsigned int starthere = 0, lenhere = 0, writecount = 0; - /* get_next_write() sets starthere to a new value after the call. */ - while ((lenhere = get_next_write(erased_contents + starthere, backup_contents + starthere, - erase_len - starthere, &starthere, flashctx->chip->gran))) { - if (!writecount++) - msg_cdbg("W"); - /* Needs the partial write function signature. */ - if (write_flash(flashctx, backup_contents + starthere, - info->erase_start + starthere, lenhere)) - goto _free_ret; - starthere += lenhere; - } - } - - ret = 0; - -_free_ret: - free(erased_contents); - free(backup_contents); - return ret; -} - -/** - * @brief Erases the included layout regions. - * - * If there is no layout set in the given flash context, the whole chip will - * be erased. - * - * @param flashctx Flash context to be used. - * @return 0 on success, - * 1 if all available erase functions failed. - */ -static int erase_by_layout_legacy(struct flashctx *const flashctx) -{ - struct walk_info info = { 0 }; - bool all_skipped = true; - return walk_by_layout(flashctx, &info, &erase_block, &all_skipped); -} - static int erase_by_layout_new(struct flashctx *const flashctx) { bool all_skipped = true; @@ -1618,129 +1372,9 @@ static int erase_by_layout(struct flashctx *const flashctx) { - if (use_legacy_erase_path) - return erase_by_layout_legacy(flashctx); return erase_by_layout_new(flashctx); } -static int read_erase_write_block(struct flashctx *const flashctx, - const struct walk_info *const info, const erasefn_t erasefn, - bool *all_skipped) -{ - const chipsize_t erase_len = info->erase_end + 1 - info->erase_start; - const bool region_unaligned = info->region_start > info->erase_start || - info->erase_end > info->region_end; - const uint8_t *newcontents = NULL; - int ret = 2; - - /* - * If the region is not erase-block aligned, merge current flash con- - * tents into `info->curcontents` and a new buffer `newc`. The former - * is necessary since we have no guarantee that the full erase block - * was already read into `info->curcontents`. For the latter a new - * buffer is used since `info->newcontents` might contain data for - * other unaligned regions that touch this erase block too. - */ - if (region_unaligned) { - msg_cdbg("R"); - uint8_t *const newc = malloc(erase_len); - if (!newc) { - msg_cerr("Out of memory!\n"); - return 1; - } - memcpy(newc, info->newcontents + info->erase_start, erase_len); - - /* Merge data preceding the current region. */ - if (info->region_start > info->erase_start) { - const chipoff_t start = info->erase_start; - const chipsize_t len = info->region_start - info->erase_start; - if (read_flash(flashctx, newc, start, len)) { - msg_cerr("Can't read! Aborting.\n"); - goto _free_ret; - } - memcpy(info->curcontents + start, newc, len); - } - /* Merge data following the current region. */ - if (info->erase_end > info->region_end) { - const chipoff_t start = info->region_end + 1; - const chipoff_t rel_start = start - info->erase_start; /* within this erase block */ - const chipsize_t len = info->erase_end - info->region_end; - if (read_flash(flashctx, newc + rel_start, start, len)) { - msg_cerr("Can't read! Aborting.\n"); - goto _free_ret; - } - memcpy(info->curcontents + start, newc + rel_start, len); - } - - newcontents = newc; - } else { - newcontents = info->newcontents + info->erase_start; - } - - ret = 1; - bool skipped = true; - uint8_t *const curcontents = info->curcontents + info->erase_start; - const uint8_t erased_value = ERASED_VALUE(flashctx); - if (!(flashctx->chip->feature_bits & FEATURE_NO_ERASE) && - need_erase(curcontents, newcontents, erase_len, flashctx->chip->gran, erased_value)) { - if (erase_block(flashctx, info, erasefn, all_skipped)) - goto _free_ret; - /* Erase was successful. Adjust curcontents. */ - memset(curcontents, erased_value, erase_len); - skipped = false; - } - - unsigned int starthere = 0, lenhere = 0, writecount = 0; - /* get_next_write() sets starthere to a new value after the call. */ - while ((lenhere = get_next_write(curcontents + starthere, newcontents + starthere, - erase_len - starthere, &starthere, flashctx->chip->gran))) { - if (!writecount++) - msg_cdbg("W"); - /* Needs the partial write function signature. */ - if (write_flash(flashctx, newcontents + starthere, - info->erase_start + starthere, lenhere)) - goto _free_ret; - starthere += lenhere; - skipped = false; - } - if (skipped) - msg_cdbg("S"); - else - *all_skipped = false; - - /* Update curcontents, other regions with overlapping erase blocks - might rely on this. */ - memcpy(curcontents, newcontents, erase_len); - ret = 0; - -_free_ret: - if (region_unaligned) - free((void *)newcontents); - return ret; -} - -/** - * @brief Writes the included layout regions from a given image. - * - * If there is no layout set in the given flash context, the whole image - * will be written. - * - * @param flashctx Flash context to be used. - * @param curcontents A buffer of full chip size with current chip contents of included regions. - * @param newcontents The new image to be written. - * @return 0 on success, - * 1 if anything has gone wrong. - */ -static int write_by_layout_legacy(struct flashctx *const flashctx, - void *const curcontents, const void *const newcontents, - bool *all_skipped) -{ - struct walk_info info; - info.curcontents = curcontents; - info.newcontents = newcontents; - return walk_by_layout(flashctx, &info, read_erase_write_block, all_skipped); -} - static int write_by_layout_new(struct flashctx *const flashctx, void *const curcontents, const void *const newcontents, bool *all_skipped) @@ -1780,8 +1414,6 @@ uint8_t *const curcontents, const uint8_t *const newcontents, bool *all_skipped) { - if (use_legacy_erase_path) - return write_by_layout_legacy(flashctx, curcontents, newcontents, all_skipped); return write_by_layout_new(flashctx, curcontents, newcontents, all_skipped); } -- To view, visit https://review.coreboot.org/c/flashrom/+/83846?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I08fd686fecf6a5313eea2d66b368661c664f4800 Gerrit-Change-Number: 83846 Gerrit-PatchSet: 4 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in flashrom[main]: flashchips: add GD25LF512MF model
by Victor Lim (Code Review) 14 Aug '24

14 Aug '24

Victor Lim has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83912?usp=email ) Change subject: flashchips: add GD25LF512MF model ...................................................................... flashchips: add GD25LF512MF model GD25LF512MF: 1.8V 512Mbit high performance, quad IO enabled. I will have to send you the datasheet through email. Tested on ch347 with erase, write, read, and protection Change-Id: I3d202f5afcc9c33a4040f8186dc6fef1878ba79a Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- M flashchips.c M include/flashchips.h 2 files changed, 57 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/12/83912/1 diff --git a/flashchips.c b/flashchips.c index 2617162..5b8069c 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6644,6 +6644,62 @@ { .vendor = "GigaDevice", + .name = "GD25LF512MF", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25LF512MF, + .total_size = 65536, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2 | FEATURE_4BA, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = SPI_BLOCK_ERASE_21, + }, { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_5C, + }, { + .eraseblocks = { {32 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_DC, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {64 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {64 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1695, 1950}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */ + .srl = {STATUS2, 0, RW}, + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "GigaDevice", .name = "GD25LQ128E/GD25LB128E/GD25LR128E/GD25LQ128D/GD25LQ128C", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, diff --git a/include/flashchips.h b/include/flashchips.h index 250ade4..20f799e 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -407,6 +407,7 @@ #define GIGADEVICE_GD25LB512MF 0x601A /* Same as GD25LR512MF */ #define GIGADEVICE_GD25LF128E 0x6318 #define GIGADEVICE_GD25LF256F 0x6319 +#define GIGADEVICE_GD25LF512MF 0x631A #define GIGADEVICE_GD25LR256E 0x6719 #define GIGADEVICE_GD25LR512ME 0x671A /* Same as GD25LB512ME */ #define GIGADEVICE_GD25WQ80E 0x6514 -- To view, visit https://review.coreboot.org/c/flashrom/+/83912?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I3d202f5afcc9c33a4040f8186dc6fef1878ba79a Gerrit-Change-Number: 83912 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com>

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[S] Change in flashrom[main]: flashchips: add support for MX77U51250F chip
by Anastasia Klimchuk (Code Review) 14 Aug '24

14 Aug '24

Attention is currently required from: Bora Guvendik, Nikolai Artemiev, Stefan Reinauer, Subrata Banik. Anastasia Klimchuk has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/flashrom/+/82626?usp=email ) Change subject: flashchips: add support for MX77U51250F chip ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/82626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I2c2e94f01dc63f60cf636bc6afe1f033e2a6f83c Gerrit-Change-Number: 82626 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: DZ <danielzhang(a)mxic.com.cn> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 14 Aug 2024 05:56:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in flashrom[main]: flashchips: adding GD25LB512MF/GD25LR512MF
by Anastasia Klimchuk (Code Review) 14 Aug '24

14 Aug '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/83899?usp=email ) Change subject: flashchips: adding GD25LB512MF/GD25LR512MF ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/83899?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I6a0061a43af5966c93c95645b51a640c00f3d829 Gerrit-Change-Number: 83899 Gerrit-PatchSet: 2 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 14 Aug 2024 05:54:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in flashrom[main]: flashchips: adding GD25LB512MF/GD25LR512MF
by Victor Lim (Code Review) 14 Aug '24

14 Aug '24

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer. Victor Lim has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/83899?usp=email ) Change subject: flashchips: adding GD25LB512MF/GD25LR512MF ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/83899/comment/2f128ef6_05d063cb?us… : PS1, Line 14: The datasheet is under controll. : You can either refer to GD25LB512MF datasheet. : Or I send you a copy. > If you say the both datasheets is identical, that's fine, no need to send me the second one. […] Done https://review.coreboot.org/c/flashrom/+/83899/comment/6820e7f3_e6ffcf7b?us… : PS1, Line 18: Tested > Have you tested both models? Maybe you can add here "tested both models". Done File flashchips.c: https://review.coreboot.org/c/flashrom/+/83899/comment/0d7c42a0_c2905e47?us… : PS1, Line 7109: BP3 > SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD here? (instead of BP3) Done https://review.coreboot.org/c/flashrom/+/83899/comment/77acec98_6468ec90?us… : PS1, Line 7118: tb = {STATUS1, 6, RW}, > I think you need to add a usual comment here […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/83899?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I6a0061a43af5966c93c95645b51a640c00f3d829 Gerrit-Change-Number: 83899 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 14 Aug 2024 05:03:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[M] Change in flashrom[main]: flashchips: adding GD25LB512MF/GD25LR512MF
by Victor Lim (Code Review) 14 Aug '24

14 Aug '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/83899?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: flashchips: adding GD25LB512MF/GD25LR512MF ...................................................................... flashchips: adding GD25LB512MF/GD25LR512MF GD25LB512MF: 1.8V 512Mbit shipped with Quad enabled. https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20231213/DS-0… GD25LR512MF: all GD25LB512MF features + RPMC feature The datasheet is identical with GD25LB512MF for the NOR flash side. Tested both models on ch347 with erase, read, write, and protection. Change-Id: I6a0061a43af5966c93c95645b51a640c00f3d829 Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- M flashchips.c M include/flashchips.h 2 files changed, 57 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/99/83899/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/83899?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I6a0061a43af5966c93c95645b51a640c00f3d829 Gerrit-Change-Number: 83899 Gerrit-PatchSet: 2 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com>

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[M] Change in flashrom[main]: flashchips: adding GD25LB512MF/GD25LR512MF
by Anastasia Klimchuk (Code Review) 14 Aug '24

14 Aug '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/83899?usp=email ) Change subject: flashchips: adding GD25LB512MF/GD25LR512MF ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/83899/comment/e73d9e58_7de21e43?us… : PS1, Line 14: The datasheet is under controll. : You can either refer to GD25LB512MF datasheet. : Or I send you a copy. If you say the both datasheets is identical, that's fine, no need to send me the second one. You can remove these 3 lines from commit message. But please have a look at my other comment about testing. Thank you! https://review.coreboot.org/c/flashrom/+/83899/comment/ca1d460c_e41f423a?us… : PS1, Line 18: Tested Have you tested both models? Maybe you can add here "tested both models". File flashchips.c: https://review.coreboot.org/c/flashrom/+/83899/comment/ffd19cd3_5b19ea70?us… : PS1, Line 7109: BP3 SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD here? (instead of BP3) https://review.coreboot.org/c/flashrom/+/83899/comment/19409ba3_d39cf2bb?us… : PS1, Line 7118: tb = {STATUS1, 6, RW}, I think you need to add a usual comment here > Called BP4 in datasheet, acts like TB -- To view, visit https://review.coreboot.org/c/flashrom/+/83899?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I6a0061a43af5966c93c95645b51a640c00f3d829 Gerrit-Change-Number: 83899 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 14 Aug 2024 03:36:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in flashrom[main]: flashchips: add support for MX77U51250F chip
by DZ (Code Review) 14 Aug '24

14 Aug '24

Attention is currently required from: Anastasia Klimchuk, Bora Guvendik, Nikolai Artemiev, Stefan Reinauer, Subrata Banik. DZ has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/flashrom/+/82626?usp=email ) Change subject: flashchips: add support for MX77U51250F chip ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > Daniel, maybe you could a final look at the patch? All the comments are resolved now. […] OK, I think the modification is all good. -- To view, visit https://review.coreboot.org/c/flashrom/+/82626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I2c2e94f01dc63f60cf636bc6afe1f033e2a6f83c Gerrit-Change-Number: 82626 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: DZ <danielzhang(a)mxic.com.cn> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 14 Aug 2024 03:29:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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