Nico Huber has uploaded this change for review. ( https://review.coreboot.org/20246
Change subject: ich_descriptors: Add function to guess chipset version
......................................................................
ich_descriptors: Add function to guess chipset version
Add guess_ich_chipset() that takes fields from a descriptor dump and
returns the lowest possible chipset version.
Intel did several incompatible changes to the descriptor through the
years. However, they forgot to add a version number. So we have to
apply some heuristics to detect the chipset version in case of exter-
nal flashing.
Change-Id: Ie1736663dc33801b19d3e695c072c61a6c6345a2
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M ich_descriptors.c
M ich_descriptors.h
2 files changed, 64 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/46/20246/1
diff --git a/ich_descriptors.c b/ich_descriptors.c
index aab686a..9241389 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -702,6 +702,66 @@
msg_pdbg2("\n");
}
+/*
+ * Guesses a minimum chipset version based on the maximum number of
+ * soft straps per generation.
+ */
+static enum ich_chipset guess_ich_chipset_from_content(const struct ich_desc_content *const content)
+{
+ if (content->ICCRIBA == 0x00) {
+ if (content->MSL == 0 && content->ISL <= 2)
+ return CHIPSET_ICH8;
+ else if (content->ISL <= 2)
+ return CHIPSET_ICH9;
+ else if (content->ISL <= 10)
+ return CHIPSET_ICH10;
+ else
+ return CHIPSET_5_SERIES_IBEX_PEAK;
+ } else if (content->ICCRIBA < 0x31 && content->FMSBA < 0x30) {
+ if (content->MSL == 0 && content->ISL <= 17)
+ return CHIPSET_BAYTRAIL;
+ else if (content->MSL <= 1 && content->ISL <= 18)
+ return CHIPSET_6_SERIES_COUGAR_POINT;
+ else if (content->MSL <= 1 && content->ISL <= 21)
+ return CHIPSET_8_SERIES_LYNX_POINT;
+ else
+ return CHIPSET_100_SERIES_SUNRISE_POINT;
+ } else {
+ return CHIPSET_100_SERIES_SUNRISE_POINT;
+ }
+}
+
+/*
+ * As an additional measure, we check the read frequency like `ifdtool`.
+ * The frequency value 6 (17MHz) was reserved before Skylake and is the
+ * only valid value since. Skylake is currently the most important dis-
+ * tinction because of the dropped number of regions field (NR).
+ */
+enum ich_chipset guess_ich_chipset(const struct ich_desc_content *const content,
+ const struct ich_desc_component *const component)
+{
+ const enum ich_chipset guess = guess_ich_chipset_from_content(content);
+
+ if (component->modes.freq_read == 6) {
+ if (guess <= CHIPSET_5_SERIES_IBEX_PEAK)
+ msg_pwarn("\nThe firmware descriptor has the read frequency set to 17MHz. However,\n"
+ "it doesn't look like a Skylake/Sunrise Point compatible descriptor.\n"
+ "Please report this message, the output of `ich_descriptors_tool` for\n"
+ "your descriptor and the output of `lspci -nn` to flashrom(a)flashrom.org\n\n");
+ return CHIPSET_100_SERIES_SUNRISE_POINT;
+ } else {
+ if (guess == CHIPSET_100_SERIES_SUNRISE_POINT) {
+ msg_pwarn("\nThe firmware descriptor looks like a Skylake/Sunrise Point descriptor.\n"
+ "However, the read frequency isn't set to 17MHz (the only valid value).\n"
+ "Please report this message, the output of `ich_descriptors_tool` for\n"
+ "your descriptor and the output of `lspci -nn` to flashrom(a)flashrom.org\n\n");
+ return CHIPSET_9_SERIES_WILDCAT_POINT;
+ }
+ }
+
+ return guess;
+}
+
/* len is the length of dump in bytes */
int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, struct ich_descriptors *desc)
{
diff --git a/ich_descriptors.h b/ich_descriptors.h
index ec85e0c..920e098 100644
--- a/ich_descriptors.h
+++ b/ich_descriptors.h
@@ -93,9 +93,10 @@
union { /* 0x0c */
uint32_t FLMAP2;
struct {
- uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */
- MSL :8, /* MCH Strap Length */
- :16;
+ uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */
+ MSL :8, /* MCH Strap Length */
+ ICCRIBA :8, /* ICC Reg. Init Base Addr. (new since Sandy Bridge) */
+ RIL :8; /* Register Init Length (new since Hawell) */
};
};
};
--
To view, visit https://review.coreboot.org/20246
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Gerrit-Project: flashrom
Gerrit-Branch: staging
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie1736663dc33801b19d3e695c072c61a6c6345a2
Gerrit-Change-Number: 20246
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Hello Stefan Tauner, David Hendricks, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19044
to look at the new patch set (#4).
Change subject: ich_descriptors: Fix more odd +1s
......................................................................
ich_descriptors: Fix more odd +1s
+1 on everything doesn't make software greater per se.
v2: o Fix another +1.
o Amend style of similar (not +1 suffering) code, too.
Change-Id: Ifa5455c999e90ff9121aed29f542d71ac9ca2b1c
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M ich_descriptors.c
1 file changed, 7 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/44/19044/4
--
To view, visit https://review.coreboot.org/19044
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: staging
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ifa5455c999e90ff9121aed29f542d71ac9ca2b1c
Gerrit-Change-Number: 19044
Gerrit-PatchSet: 4
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello Stefan Tauner, Paul Menzel, David Hendricks, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18973
to look at the new patch set (#9).
Change subject: ich_descriptors: Update for Intel Skylake
......................................................................
ich_descriptors: Update for Intel Skylake
Interpretation of component clocks changed. Also more regions and more
masters are supported now. The number of regions (NR) is now static per
chipset (10 in the 100 Series case) and not coded into the descriptor
any more.
v2: o Use guess_ich_chipset() for read_ich_descriptors_from_dump().
o Update region extraction in `ich_descriptors_tool`.
TEST=Run `ich_descriptors_tool` over a 100 Series dump and checked
that output looks sane. Run `ich_descriptors_tool` over dumps
of five different older systems (1 x Sandy Bridge, 3 x Ivy Bridge,
1 x Haswell). Beside whitespace changes, regions not accounted
by `NR` are not printed any more.
Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M ich_descriptors.c
M ich_descriptors.h
M util/ich_descriptors_tool/ich_descriptors_tool.c
3 files changed, 265 insertions(+), 163 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/18973/9
--
To view, visit https://review.coreboot.org/18973
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: flashrom
Gerrit-Branch: staging
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8
Gerrit-Change-Number: 18973
Gerrit-PatchSet: 9
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>