Attention is currently required from: Anastasia Klimchuk, Peter Marheine, Thomas Heijligen.
Brian Norris has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/81545?usp=email )
Change subject: udelay: only use OS time for delays, except on DOS
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Patch Set 9: Code-Review+1
(3 comments)
Patchset:
PS9:
LGTM % test question
File meson.build:
https://review.coreboot.org/c/flashrom/+/81545/comment/615b625a_b50dc7b2 :
PS4, Line 121: DHAVE_NANOSLEEP=1
> On reflection, this isn't even required. […]
👍
I was kinda wondering if we really cared to support non-POSIX.1-2008 here (outside of Windows and DOS, which build non-nanosleep code already).
File tests/udelay.c:
https://review.coreboot.org/c/flashrom/+/81545/comment/9e7989ec_59a9e340 :
PS9, Line 41: This test could fail spuriously on a heavily-loaded system
I see you acknowledge this already, but I just want to mention that this is definitely relevant for ChromeOS. We run tests from quite a few different projects in our CI environment, and sometimes this may yield a lot of system load at the same time. We've seen sleep-related latencies that are 5x their expected.
Specifically, we expected 100ms, so we tested for 500ms -- and even then, we saw frequent enough flakes that we expanded the margin to 1000ms.
That's to say, I expect this test will become flaky on ChromeOS CI. I don't know how that fits into the flashrom project expectations.
Anyway, personally, I'd recommend only testing the lower bound and not the upper bound.
---
For the record, public references:
https://chromium-review.googlesource.com/c/chromiumos/platform2/+/2207141https://bugs.chromium.org/p/chromium/issues/detail?id=1083515
Non-public reference: b/333412847
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Maximilian Brune has uploaded a new patch set (#2). ( https://review.coreboot.org/c/flashrom/+/81855?usp=email )
Change subject: util/list_yet_unsupported_chips.h: Fix path
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util/list_yet_unsupported_chips.h: Fix path
Change-Id: Iecb6cf3d1f214102a243a3ffa8d0c9301263af0a
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
---
M util/list_yet_unsupported_chips.sh
1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/55/81855/2
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Change subject: sb600spi.c: Drop "Promontory" support
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Change subject: [WIP] ft2232_spi.c: Reduce scope of programmer param variables
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46523 )
Change subject: dummyflasher.c: Use programmer logger functions
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dummyflasher.c: Use programmer logger functions
All but three log messages use the programmer logger. Change the three
outliers that were using the chip logger accordingly.
Change-Id: Ia8668e05df2da739e6bb4c7d0fddad86e8d054a3
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M dummyflasher.c
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/23/46523/1
diff --git a/dummyflasher.c b/dummyflasher.c
index 6426ad2..d233db4 100644
--- a/dummyflasher.c
+++ b/dummyflasher.c
@@ -610,7 +610,7 @@
}
for (i = 0; i < data->spi_ignorelist_size; i++) {
if (writearr[0] == data->spi_ignorelist[i]) {
- msg_cdbg("Ignoring ignorelisted SPI command 0x%02x\n",
+ msg_pdbg("Ignoring ignorelisted SPI command 0x%02x\n",
data->spi_ignorelist[i]);
/* Return success because the command does not fail,
* it is simply ignored.
@@ -1050,7 +1050,7 @@
* Search "total_size * 1024" in code.
*/
flash->chip->total_size = emu_data->emu_chip_size / 1024;
- msg_cdbg("%s: set flash->total_size to %dK bytes.\n", __func__,
+ msg_pdbg("%s: set flash->total_size to %dK bytes.\n", __func__,
flash->chip->total_size);
/* Update the first count of each of the block_erasers. */
@@ -1061,7 +1061,7 @@
eraser->eraseblocks[0].count = 1;
eraser->eraseblocks[0].size = emu_data->emu_chip_size;
- msg_cdbg("%s: eraser.size=%d, .count=%d\n",
+ msg_pdbg("%s: eraser.size=%d, .count=%d\n",
__func__, eraser->eraseblocks[0].size,
eraser->eraseblocks[0].count);
}
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Change subject: treewide: Use calloc() where applicable
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Change subject: [UNTESTED] bitbang_spi.c: Support changing clock polarity and phase
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Change subject: bitbang_spi.c: Do not set MOSI during initialization
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Change subject: bitbang_spi: Refactor `set_sck_set_mosi`
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