- flashrom-gerrit - mail.coreboot.org

[S] Change in flashrom[main]: flashchips: Add support for MXIC MX25R2035F
by DZ (Code Review) 12 Apr '24

12 Apr '24

DZ has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/81839?usp=email ) Change subject: flashchips: Add support for MXIC MX25R2035F ...................................................................... flashchips: Add support for MXIC MX25R2035F The MX25R2035F has been tested by ch341a programmer : read, write, erase and wp. We have tested --wp-enable, --wp-disable, --wp-list and --wp-range commands for write-protect feature. MX25R2035F datasheet is available at the following URL: https://www.macronix.com/Lists/Datasheet/Attachments/8696/MX25R2035F,%20Wid… Change-Id: I00e76ef942976e3e102cf71fe695c6287b392b64 Signed-off-by: DanielZhang <danielzhang(a)mxic.com.cn> --- M flashchips.c M include/flashchips.h 2 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/39/81839/1 diff --git a/flashchips.c b/flashchips.c index 7a40f07..4c3c9f3 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10213,6 +10213,53 @@ { .vendor = "Macronix", + .name = "MX25R2035F", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25R2035F, + .total_size = 256, + .page_size = 256, + /* OTP: 1024B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_CFGR, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 8} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {1 * 256 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {1 * 256 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit 6 is quad enable */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1650, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {CONFIG, 3, OTP} + }, + + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "Macronix", .name = "MX25V4035F", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, diff --git a/include/flashchips.h b/include/flashchips.h index 103e6ea..b5194fd 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -540,6 +540,7 @@ #define MACRONIX_MX25R1635F 0x2815 #define MACRONIX_MX25R3235F 0x2816 #define MACRONIX_MX25R6435F 0x2817 +#define MXCRONIX_MX25R2035F 0x2812 #define MACRONIX_MX29F001B 0x19 #define MACRONIX_MX29F001T 0x18 -- To view, visit https://review.coreboot.org/c/flashrom/+/81839?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I00e76ef942976e3e102cf71fe695c6287b392b64 Gerrit-Change-Number: 81839 Gerrit-PatchSet: 1 Gerrit-Owner: DZ <danielzhang(a)mxic.com.cn> Gerrit-MessageType: newchange

1 0

[S] Change in flashrom[main]: flashchips: Add support for MXIC MX25R4035F
by DZ (Code Review) 12 Apr '24

12 Apr '24

DZ has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/81838?usp=email ) Change subject: flashchips: Add support for MXIC MX25R4035F ...................................................................... flashchips: Add support for MXIC MX25R4035F The MX25R4035F has been tested by ch341a programmer : read, write, erase and wp. We have tested --wp-enable, --wp-disable, --wp-list and --wp-range commands for write-protect feature. MX25R4035F datasheet is available at the following URL: https://www.macronix.com/Lists/Datasheet/Attachments/8671/MX25R4035F,%20Wid… Change-Id: I91dbc4735bf232e0b1dce72c7f06be967d35ebfb Signed-off-by: DanielZhang <danielzhang(a)mxic.com.cn> --- M flashchips.c M include/flashchips.h 2 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/38/81838/1 diff --git a/flashchips.c b/flashchips.c index 7a40f07..f74c705 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10213,6 +10213,53 @@ { .vendor = "Macronix", + .name = "MX25R4035F", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25R4035F, + .total_size = 512, + .page_size = 256, + /* OTP: 1024B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_CFGR, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 16} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {1 * 512 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {1 * 512 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit 6 is quad enable */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1650, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {CONFIG, 3, OTP} + }, + + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "Macronix", .name = "MX25V4035F", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, diff --git a/include/flashchips.h b/include/flashchips.h index 103e6ea..3aea170 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -540,6 +540,7 @@ #define MACRONIX_MX25R1635F 0x2815 #define MACRONIX_MX25R3235F 0x2816 #define MACRONIX_MX25R6435F 0x2817 +#define MACRONIX_MX25R4035F 0x2813 #define MACRONIX_MX29F001B 0x19 #define MACRONIX_MX29F001T 0x18 -- To view, visit https://review.coreboot.org/c/flashrom/+/81838?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I91dbc4735bf232e0b1dce72c7f06be967d35ebfb Gerrit-Change-Number: 81838 Gerrit-PatchSet: 1 Gerrit-Owner: DZ <danielzhang(a)mxic.com.cn> Gerrit-MessageType: newchange

1 0

[S] Change in flashrom[main]: flashchips: Add support for MXIC MX25R8035F
by DZ (Code Review) 12 Apr '24

12 Apr '24

DZ has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/81837?usp=email ) Change subject: flashchips: Add support for MXIC MX25R8035F ...................................................................... flashchips: Add support for MXIC MX25R8035F The MX25R8035F has been tested by ch341a programmer : read, write, erase and wp. We have tested --wp-enable, --wp-disable, --wp-list and --wp-range commands for write-protect feature. MX25R8035F datasheet is available at the following URL: https://www.macronix.com/Lists/Datasheet/Attachments/8749/MX25R8035F,%20Wid… Change-Id: Iec244ffc29278c1f8c3ae47d17af2c4fe5fbe498 Signed-off-by: DanielZhang <danielzhang(a)mxic.com.cn> --- M flashchips.c M include/flashchips.h 2 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/37/81837/1 diff --git a/flashchips.c b/flashchips.c index 7a40f07..e1e774c 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10213,6 +10213,53 @@ { .vendor = "Macronix", + .name = "MX25R8035F", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25R8035F, + .total_size = 1024, + .page_size = 256, + /* OTP: 1024B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_CFGR, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {1 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {1 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit 6 is quad enable */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1650, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {CONFIG, 3, OTP} + }, + + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "Macronix", .name = "MX25V4035F", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, diff --git a/include/flashchips.h b/include/flashchips.h index 103e6ea..c9303d5 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -540,6 +540,7 @@ #define MACRONIX_MX25R1635F 0x2815 #define MACRONIX_MX25R3235F 0x2816 #define MACRONIX_MX25R6435F 0x2817 +#define MACRONIX_MX25R8035F 0x2814 #define MACRONIX_MX29F001B 0x19 #define MACRONIX_MX29F001T 0x18 -- To view, visit https://review.coreboot.org/c/flashrom/+/81837?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Iec244ffc29278c1f8c3ae47d17af2c4fe5fbe498 Gerrit-Change-Number: 81837 Gerrit-PatchSet: 1 Gerrit-Owner: DZ <danielzhang(a)mxic.com.cn> Gerrit-MessageType: newchange

1 0

[L] Change in flashrom[main]: udelay: only use OS time for delays, except on DOS
by Peter Marheine (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Anastasia Klimchuk, Brian Norris, Thomas Heijligen. Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/81545?usp=email ) Change subject: udelay: only use OS time for delays, except on DOS ...................................................................... Patch Set 9: (2 comments) Patchset: PS9: > Peter, this looks cool ! What do you think about sharing the link to the patch on the mailing list, […] Yup, good idea. Added a note to the existing thread. File tests/udelay.c: https://review.coreboot.org/c/flashrom/+/81545/comment/2ab2c0fc_d1278800 : PS9, Line 41: This test could fail spuriously on a heavily-loaded system > From my side, I would want to keep the test, with both lower and upper bound. […] Carrying a patch to the test on ChromeOS seems okay to me, but I'm not particularly attached to testing the upper bound anyway since it doesn't feel very right to me to have a test that can fail when run on a machine that's busy doing other things. The invariant that the implementation needs to enforce is that it waits for no less time than requested; the upper bound is only important in that waiting for a longer time might result in a poor user experience. The question is whether we consider a poor user experience a true error, and if so what threshold we care about. -- To view, visit https://review.coreboot.org/c/flashrom/+/81545?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I7ac5450d194a475143698d65d64d8bcd2fd25e3f Gerrit-Change-Number: 81545 Gerrit-PatchSet: 9 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Brian Norris <briannorris(a)chromium.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Fri, 12 Apr 2024 06:28:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Brian Norris <briannorris(a)chromium.org> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: comment

1 0

[L] Change in flashrom[main]: udelay: only use OS time for delays, except on DOS
by Anastasia Klimchuk (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Brian Norris, Peter Marheine, Thomas Heijligen. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/81545?usp=email ) Change subject: udelay: only use OS time for delays, except on DOS ...................................................................... Patch Set 9: (2 comments) Patchset: PS9: Peter, this looks cool ! What do you think about sharing the link to the patch on the mailing list, perhaps some people would be interested to help testing. Even building on environment which is not-like-Jenkins would be really helpful. File tests/udelay.c: https://review.coreboot.org/c/flashrom/+/81545/comment/2a494375_efde4c23 : PS9, Line 41: This test could fail spuriously on a heavily-loaded system > Since this test is mostly meant to exercise the sleep-free case (as I explained in response to Anast […] From my side, I would want to keep the test, with both lower and upper bound. I like more tests, not less! :) I really appreciate Peter adding a test in a patch! Jenkins seems to be happy with the test, as we see. We can get incoming patches from anyone in the world, and unit tests are easy to run, and they give more confidence in the patch (for both sides). In any case I agree to keep an eye on how the test is doing after it's merged, if it causes many flakes for upstream development we can remove upper bound. But I don't think there will be troubles. ChromeOS fork could perhaps make a small one line diff, change the assert line, or disable the test (but first option is better, much less intrusive for downstreaming). It's not the only diff in unit tests. Peter you are closer to that, do you think it's fine? -- To view, visit https://review.coreboot.org/c/flashrom/+/81545?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I7ac5450d194a475143698d65d64d8bcd2fd25e3f Gerrit-Change-Number: 81545 Gerrit-PatchSet: 9 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Brian Norris <briannorris(a)chromium.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Fri, 12 Apr 2024 05:51:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Brian Norris <briannorris(a)chromium.org> Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: comment

1 0

[XS] Change in flashrom[main]: Makefile: Fix cleanup for Sphinx versions prior to 4.x
by Anastasia Klimchuk (Code Review) 12 Apr '24

12 Apr '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/81802?usp=email ) Change subject: Makefile: Fix cleanup for Sphinx versions prior to 4.x ...................................................................... Makefile: Fix cleanup for Sphinx versions prior to 4.x Fixup for change I9cd280551a1ba4d17edb2e857d56f80431b61e1b. Change-Id: I123aec7cf2f016ba905c220cfc84a217523f9932 Signed-off-by: Anton Samsonov <devel(a)zxlab.ru> Reviewed-on: https://review.coreboot.org/c/flashrom/+/81802 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M Makefile 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/Makefile b/Makefile index 9ce5906..1c0904b 100644 --- a/Makefile +++ b/Makefile @@ -1075,7 +1075,7 @@ # We don't use EXEC_SUFFIX here because we want to clean everything. clean: rm -rf $(PROGRAM) $(PROGRAM).exe libflashrom.a $(filter-out Makefile.d, $(wildcard *.d *.o platform/*.d platform/*.o)) \ - man8 .doctrees $(PROGRAM).bash $(BUILD_DETAILS_FILE) + man8 8 .doctrees $(PROGRAM).bash $(BUILD_DETAILS_FILE) @+$(MAKE) -C util/ich_descriptors_tool/ clean install: $(PROGRAM)$(EXEC_SUFFIX) $(call has_dependency, $(HAS_SPHINXBUILD), man8/$(PROGRAM).8) $(PROGRAM).bash -- To view, visit https://review.coreboot.org/c/flashrom/+/81802?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I123aec7cf2f016ba905c220cfc84a217523f9932 Gerrit-Change-Number: 81802 Gerrit-PatchSet: 2 Gerrit-Owner: Anton Samsonov <devel(a)zxlab.ru> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in flashrom[main]: util/list_yet_unsupported_chips.h: Fix path
by Anastasia Klimchuk (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Maximilian Brune. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/81855?usp=email ) Change subject: util/list_yet_unsupported_chips.h: Fix path ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: Ooh this has been broken for a while, include dir was introduced a while ago... thank you for fixing Maximillian! You have probably run the script, does it produce a useful info? Is it detecting the chips that are in .h file but have no definition in .c file? -- To view, visit https://review.coreboot.org/c/flashrom/+/81855?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Iecb6cf3d1f214102a243a3ffa8d0c9301263af0a Gerrit-Change-Number: 81855 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Fri, 12 Apr 2024 05:25:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in flashrom[main]: flashchips: Add support for MXIC MX25L1633E
by DZ (Code Review) 12 Apr '24

12 Apr '24

DZ has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/81836?usp=email ) Change subject: flashchips: Add support for MXIC MX25L1633E ...................................................................... flashchips: Add support for MXIC MX25L1633E The MX25L1633E has been tested by ch341a programmer : read, write, erase and wp. We have tested --wp-enable, --wp-disable, --wp-list and --wp-range commands for write-protect feature. MX25L1633E datasheet is available at the following URL: https://www.macronix.com/Lists/Datasheet/Attachments/8617/MX25L1633E,%203V,… Change-Id: I63ee0182ad6e62b7408136285aa0e927d53f7bc8 Signed-off-by: DanielZhang <danielzhang(a)mxic.com.cn> --- M flashchips.c 1 file changed, 44 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/36/81836/1 diff --git a/flashchips.c b/flashchips.c index 7a40f07..34a2a51 100644 --- a/flashchips.c +++ b/flashchips.c @@ -9227,7 +9227,7 @@ }, { .eraseblocks = { {2 * 1024 * 1024, 1} }, .block_erase = SPI_BLOCK_ERASE_C7, - }, + OB }, }, .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6: Continuously Program (CP) mode, for 73E is quad enable */ .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, @@ -9274,6 +9274,49 @@ { .vendor = "Macronix", + .name = "MX25L1633E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L1635D, + .total_size = 2048, + .page_size = 256, + /* OTP: 64B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP , + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + }, + + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "Macronix", .name = "MX25L1635E", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, -- To view, visit https://review.coreboot.org/c/flashrom/+/81836?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I63ee0182ad6e62b7408136285aa0e927d53f7bc8 Gerrit-Change-Number: 81836 Gerrit-PatchSet: 1 Gerrit-Owner: DZ <danielzhang(a)mxic.com.cn> Gerrit-MessageType: newchange

1 0

[S] Change in flashrom[main]: flashchips: Add support for MXIC MX25L1636E
by DZ (Code Review) 12 Apr '24

12 Apr '24

DZ has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/81835?usp=email ) Change subject: flashchips: Add support for MXIC MX25L1636E ...................................................................... flashchips: Add support for MXIC MX25L1636E The MX25L1636E has been tested by ch341a programmer : read, write, erase and wp. We have tested --wp-enable, --wp-disable, --wp-list and --wp-range commands for write-protect feature. MX25L1636E datasheet is available at the following URL: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8596/MX25L1636E,%203V,%… Change-Id: I415e2d6c89d3d59ba44e22753001c6f69421c39d Signed-off-by: DanielZhang <danielzhang(a)mxic.com.cn> --- M flashchips.c 1 file changed, 11 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/35/81835/1 diff --git a/flashchips.c b/flashchips.c index 7a40f07..c60770b 100644 --- a/flashchips.c +++ b/flashchips.c @@ -9274,15 +9274,15 @@ { .vendor = "Macronix", - .name = "MX25L1635E", + .name = "MX25L1635E/MX25L1636E", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L1635E, .total_size = 2048, .page_size = 256, /* OTP: 64B total; enter 0xB1, exit 0xC1 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_UNTESTED, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_CFGR, + .tested = TEST_OK_PREWB, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, .block_erasers = @@ -9306,6 +9306,14 @@ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {CONFIG, 3, OTP} + }, + + .decode_range = DECODE_RANGE_SPI25, }, { -- To view, visit https://review.coreboot.org/c/flashrom/+/81835?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I415e2d6c89d3d59ba44e22753001c6f69421c39d Gerrit-Change-Number: 81835 Gerrit-PatchSet: 1 Gerrit-Owner: DZ <danielzhang(a)mxic.com.cn> Gerrit-MessageType: newchange

1 0

[L] Change in flashrom[main]: udelay: only use OS time for delays, except on DOS
by Peter Marheine (Code Review) 12 Apr '24

12 Apr '24

Attention is currently required from: Anastasia Klimchuk, Brian Norris, Thomas Heijligen. Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/81545?usp=email ) Change subject: udelay: only use OS time for delays, except on DOS ...................................................................... Patch Set 9: (1 comment) File tests/udelay.c: https://review.coreboot.org/c/flashrom/+/81545/comment/0469c528_8164c12f : PS9, Line 41: This test could fail spuriously on a heavily-loaded system > I see you acknowledge this already, but I just want to mention that this is definitely relevant for […] Since this test is mostly meant to exercise the sleep-free case (as I explained in response to Anastasia's comment on the test code), do you think it would be reasonable to maintain this assertion as-is provided we ensure the tested delay is always short enough to avoid sleeping? I'm imagining 100 microseconds as written now, or 1 less than the minimum sleep time if that is not greater than 100 microseconds. Otherwise I wouldn't mind removing the upper bound. I would expect that our time-polling loop would still be responsive enough even on a heavily-loaded CI system, unless we got unlucky and the delay fell right at the end of a quantum (causing the test to be preempted), but perhaps that would still be too common to be acceptable. -- To view, visit https://review.coreboot.org/c/flashrom/+/81545?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I7ac5450d194a475143698d65d64d8bcd2fd25e3f Gerrit-Change-Number: 81545 Gerrit-PatchSet: 9 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Brian Norris <briannorris(a)chromium.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Fri, 12 Apr 2024 01:22:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Brian Norris <briannorris(a)chromium.org> Gerrit-MessageType: comment

1 0

2025

2024

2023

2022

2021

2020

2019

2018

2017

flashrom-gerrit