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Change subject: flashchips: Split and add write-protect support for MX25L12833F
......................................................................
Patch Set 5: Code-Review+1
(3 comments)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/81792/comment/9503ca9a_49a1434f :
PS5, Line 9038: /* TODO: security register and SBLK/SBULK; */
I am not sure what is SBLK/SBULK but I think this TODO can be removed.
https://review.coreboot.org/c/flashrom/+/81792/comment/7c5c22e9_6db225a1 :
PS5, Line 9086: /* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */
Same: this TODO can be removed
https://review.coreboot.org/c/flashrom/+/81792/comment/0de248eb_38192063 :
PS5, Line 9134: /* TODO: security register and SBLK/SBULK */
Same: this TODO can be removed
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Change subject: udelay: clock_getres() does not provide clock_gettime() resolution
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Patch Set 3:
(1 comment)
Patchset:
PS3:
Brian, do you need this patch given that Peter's patch goes ahead CB:81545 ?
If not you can abandon this one (or you can wait until the other one gets submitted).
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Change subject: flashchips: Add write protect function support for MX25R1635F
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Patch Set 1: Code-Review+2
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Change subject: flashchips: Add support for MXIC MX25R2035F
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/81839/comment/32bffbb1_00c06956 :
PS5, Line 10216: .name = "MX25R2035F",
Same as in the other patch: being sorted alphabetically by name, this should be between R16 and R32
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Change subject: flashchips: Add support for MXIC MX25R4035F
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/81838/comment/b269d112_b000c99d :
PS1, Line 10216: .name = "MX25R4035F",
The entries are sorted by name, so I think this one goes between R32 and R64
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Change subject: flashchips: Add support for MXIC MX25R8035F
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Patch Set 1: Code-Review+2
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Change subject: ich: Add names for region 5, 9, 10, 11, 12, 15
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
File util/ich_descriptors_tool/ich_descriptors_tool.c:
https://review.coreboot.org/c/flashrom/+/81356/comment/2503b8cf_7912b258 :
PS5, Line 42: 10GbE0
> The OpROM is located on 10GbE#2, not 10GbE#1. While I considered changing the output to:
Region 12 (10GbE1/OpROM) is unused.
...this would require significant code modifications due to padding width adjustments. I've decided to postpone this change for now.
Yes, my typo, it would be in the place of 10GbE2 !
I think your idea is very good, to update region name as 10GbE2/OpROM (since it's used in a generic way), but certainly it goes outside the scope of the patch. If you decide to do this later, you will, of course, be very welcome!
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Change subject: ich: Add names for region 5, 9, 10, 11, 12, 15
......................................................................
Patch Set 7:
(1 comment)
File util/ich_descriptors_tool/ich_descriptors_tool.c:
https://review.coreboot.org/c/flashrom/+/81356/comment/910f6bd8_7f65b6da :
PS5, Line 42: 10GbE0
Currently it looks like:
```
--- Details ---
Region 0 (Descr. ) 0x00000000 - 0x00000000
Region 1 (BIOS ) 0x00000000 - 0x00000000
Region 2 (ME ) 0x00000000 - 0x00000000
Region 3 (GbE ) is unused.
Region 4 (Platf. ) is unused.
Region 5 (DevExp ) is unused.
Region 6 (BIOS2 ) is unused.
Region 7 (unknown) is unused.
Region 8 (EC/BMC ) is unused.
Region 9 (unknown) 0x00000000 - 0x00000000
Region 10 (IE ) is unused.
Region 11 (10GbE0 ) is unused.
Region 12 (10GbE1 ) is unused.
Region 13 (unknown) is unused.
Region 14 (unknown) is unused.
Region 15 (PTT ) is unused.
=== Master Section ===
FLMSTR1 0x00000000
FLMSTR2 0x00000000
```
> Is it true then, that for C620 the tool will print 10GbE1 instead of OpROM ?
The OpROM is located on 10GbE#2, not 10GbE#1. While I considered changing the output to:
`Region 12 (10GbE1/OpROM) is unused.`
...this would require significant code modifications due to padding width adjustments. I've decided to postpone this change for now.
> I just want to fully understand.
Absolutely! This is a complex area with some documentation being confidential. I've definitely gained insights while working on this CL.
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Change subject: ich: Add names for region 5, 9, 10, 11, 12, 15
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Patch Set 7:
(1 comment)
File util/ich_descriptors_tool/ich_descriptors_tool.c:
https://review.coreboot.org/c/flashrom/+/81356/comment/ce5005a7_d90ecdd3 :
PS5, Line 42: 10GbE0
> I could only find 2: […]
Thanks so much for your explanation! So the region names can be slightly different from one chipset to another.
But `util/ich_descriptors_tool/ich_descriptors_tool.c` have only one list of region names.
Is it true then, that for C620 the tool will print `10GbE1` instead of `OpROM` ?
I know the tool was like this before, and coreboot code that you linked seems to have one list of region names. I don't think you need to change the tool for the patch, I just want to fully understand.
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