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Brian Norris has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/80807?usp=email )
Change subject: flashrom: Don't throw around "delay 1 second" so lightly
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS1:
> I think that recommendation should be captured in some kind of changelog so there's "real" documentation of the change, though.
Done
> Erase operation verifies the chip straight away after erasing. Without any delay. (Also without respecting the noverify flags, but this we will fix later).
> From the chip point of view, erase is almost the same as write, is that correct?
> So maybe the erase flow is kind of a "proof-of-concept" for what this patch is doing?
Yeah, you might have a point. I noted this in the commit message now.
> I completely forgot that write and verify can be separated in a manual workflow, so silly of me. This changes the situation, maybe we don't need a special option.
Cool, less work for me :)
> > do you want me to start such a mailing list thread, or were you suggesting I do this?
>
> Brian, you gave me two options which are the same :)
Haha, of course I had to fudge my words :)
Anyway, I've done both of them now :)
https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/SFV3…
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Attention is currently required from: Brian Norris, Nikolai Artemiev, Peter Marheine.
Hello Nikolai Artemiev, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/80807?usp=email
to look at the new patch set (#5).
Change subject: flashrom: Don't throw around "delay 1 second" so lightly
......................................................................
flashrom: Don't throw around "delay 1 second" so lightly
Waiting a full second is a very long time, especially when
default_delay() chooses to busy-loop. This code has been around for a
decade, with vague references to user reports:
commit 8ab49e72af8465d4527de2ec37b22cd44f7a1169
Date: Wed Aug 19 13:55:34 2009 +0000
Disallow erase/write for known bad chips so people won't try without a clear understanding
Still, this logic does not belong in the high-level library logic, used
by all programmers and all chips. If there is a timing issue, it should
either be encoded in the appropriate programmer or flashchip timing.
Now, this change has some (hopefully [1] tiny) chance of regression, so
we have the following considerations:
1. emergency_help_message() already provides documentation on how to
contact support, in case we need to handle any user-reported
regressions.
2. If there is any regression here, it's only in the --verify code; so
we can always provide workarounds for testing this, to determine
whether this change may have been at fault. For example, something
like:
flashrom --write /my/new/image.bin --noverify
sleep 1
flashrom --read /tmp/bar.bin
cmp /my/new/image.bin /tmp/bar.bin
If such problems occur, we can collect system/programmer/chip info to
try to encode a more targeted delay into the appropriate
chip/programmer implementation, and avoid penalizing the entire
project like this.
3. we already have (embedded in erase_write()) erase verification that
performs no such delay. So depending on the type of timing error that
this delay was attempting to cover, we may have some proof that this
delay is no longer necessary (or at least, that whatever systems were
needing this delay in the first place are no longer caring about
flashrom).
[1] Famous last words.
BUG=b:325539928
TEST=`flashrom_tester --flashrom_binary=$(which flashrom) \
internal Erase_and_Write Fail_to_verify`,
TEST=`vpd -i RW_VPD -s foo=bar; vpd -i RW_VPD -l; \
vpd -i RW_VPD -d foo; vpd -i RW_VPD -l`
TEST=`elogtool list; elogtool add 0xa7; elogtool list`
on (at least) 2 systems:
#1: Kukui/Kakadu rev2 - MTD programmer /
kernel 5.10.215-24542-g0515a679eb42 /
CrOS ~ 15857.0.0
#2: Zork/Dirinboz rev2 -
chip name: vendor="Winbond" name="W25Q128.JW.DTR" /
BIOS: Google_Dirinboz.13434.688.0 /
kernel 5.4.267-21940-g67f70e251a74 /
CrOS ~ 15753.43.0
Change-Id: Ie09651fede3f9f03425244c94a2da8bae00315fc
Signed-off-by: Brian Norris <briannorris(a)chromium.org>
---
M flashrom.c
1 file changed, 0 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/07/80807/5
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Hello Nikolai Artemiev, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/80807?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: flashrom: Don't throw around "delay 1 second" so lightly
......................................................................
flashrom: Don't throw around "delay 1 second" so lightly
Waiting a full second is a very long time, especially when
default_delay() chooses to busy-loop. This code has been around for a
decade, with vague references to user reports:
commit 8ab49e72af8465d4527de2ec37b22cd44f7a1169
Date: Wed Aug 19 13:55:34 2009 +0000
Disallow erase/write for known bad chips so people won't try without a clear understanding
Still, this logic does not belong in the high-level library logic, used
by all programmers and all chips. If there is a timing issue, it should
either be encoded in the appropriate programmer or flashchip timing.
Now, this change has some (hopefully [1] tiny) chance of regression, so
we have the following considerations:
1. emergency_help_message() already provides documentation on how to
contact support, in case we need to handle any user-reported
regressions.
2. If there is any regression here, it's only in the --verify code; so
we can always provide workarounds for testing this, to determine
whether this change may have been at fault. For example, something
like:
flashrom --read /tmp/foo.bin
flashrom --write /my/new/image.bin --noverify
sleep 1
flashrom --read /tmp/bar.bin
cmp /tmp/foo.bin /tmp/bar.bin
If such problems occur, we can collect system/programmer/chip info to
try to encode a more targeted delay into the appropriate
chip/programmer implementation, and avoid penalizing the entire
project like this.
3. we already have (embedded in erase_write()) erase verification that
performs no such delay. So depending on the type of timing error that
this delay was attempting to cover, we may have some proof that this
delay is no longer necessary (or at least, that whatever systems were
needing this delay in the first place are no longer caring about
flashrom).
[1] Famous last words.
BUG=b:325539928
TEST=`flashrom_tester --flashrom_binary=$(which flashrom) \
internal Erase_and_Write Fail_to_verify`,
TEST=`vpd -i RW_VPD -s foo=bar; vpd -i RW_VPD -l; \
vpd -i RW_VPD -d foo; vpd -i RW_VPD -l`
TEST=`elogtool list; elogtool add 0xa7; elogtool list`
on (at least) 2 systems:
#1: Kukui/Kakadu rev2 - MTD programmer /
kernel 5.10.215-24542-g0515a679eb42 /
CrOS ~ 15857.0.0
#2: Zork/Dirinboz rev2 -
chip name: vendor="Winbond" name="W25Q128.JW.DTR" /
BIOS: Google_Dirinboz.13434.688.0 /
kernel 5.4.267-21940-g67f70e251a74 /
CrOS ~ 15753.43.0
Change-Id: Ie09651fede3f9f03425244c94a2da8bae00315fc
Signed-off-by: Brian Norris <briannorris(a)chromium.org>
---
M flashrom.c
1 file changed, 0 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/07/80807/4
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Hello Evan Benn, Hsuan-ting Chen, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: flashrom_tester: Correct "WP screw" message
......................................................................
flashrom_tester: Correct "WP screw" message
flashrom_tester prints hints on how to modify hardware write protect
state as follows:
...
> connect the battery (and/or open the WP screw)
...
> disconnect the battery (and/or open the WP screw)
...
The first advice should be "[...] close the WP screw".
TEST=`flashrom_tester --flashrom_binary=$(which flashrom) \
internal Erase_and_Write Fail_to_verify`
Change-Id: I45f06db51e92e68bf724b13bdf5b31bba511d270
Signed-off-by: Brian Norris <briannorris(a)chromium.org>
---
M util/flashrom_tester/src/utils.rs
1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/82083/3
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Hello Evan Benn, Hsuan-ting Chen, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: flashrom_tester: Correct "WP screw" message
......................................................................
flashrom_tester: Correct "WP screw" message
flashrom_tester prints hints on how to modify hardware write protect
state as follows:
...
> connect the battery (and/or open the WP screw)
...
> disconnect the battery (and/or open the WP screw)
...
The first advice should be "[...] close the WP screw".
TEST=`flashrom_tester --flashrom_binary=$(which flashrom) \
internal Erase_and_Write Fail_to_verify`
Change-Id: I45f06db51e92e68bf724b13bdf5b31bba511d270
---
M util/flashrom_tester/src/utils.rs
1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/82083/2
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Brian Norris has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/82083?usp=email )
Change subject: flashrom_tester: Correct "WP screw" message
......................................................................
flashrom_tester: Correct "WP screw" message
flashrom_tester prints hints on how to modify hardware write protect
state as follows:
...
> connect the battery (and/or open the WP screw)
...
> disconnect the battery (and/or open the WP screw)
...
The first advice should be "[...] close the WP screw".
TEST=`flashrom_tester --flashrom_binary=$(which flashrom) \
internal Erase_and_Write Fail_to_verify`
Change-Id: I45f06db51e92e68bf724b13bdf5b31bba511d270
---
M util/flashrom_tester/src/utils.rs
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/82083/1
diff --git a/util/flashrom_tester/src/utils.rs b/util/flashrom_tester/src/utils.rs
index 4e8dd7c..b43cf97 100644
--- a/util/flashrom_tester/src/utils.rs
+++ b/util/flashrom_tester/src/utils.rs
@@ -103,6 +103,7 @@
// The easist way to toggle the hardware write-protect is
// to {dis}connect the battery (and/or open the WP screw).
let s = if dis { "dis" } else { "" };
+ let screw_state = if dis { "open" } else { "close" };
// Print a failure message, but not on the first try.
let mut fail_msg = None;
while dis == get_hardware_wp()? {
@@ -112,7 +113,7 @@
fail_msg = Some(format!("Hardware write protect is still {}!", !dis));
// The following message is read by the tast test. Do not modify.
info!("Prompt for hardware WP {}able", s);
- eprintln!(" > {}connect the battery (and/or open the WP screw)", s);
+ eprintln!(" > {}connect the battery (and/or {} the WP screw)", s, screw_state);
pause();
}
Ok(())
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Change subject: doc: Convert serprog docs to rst and add to doc directory
......................................................................
Patch Set 1:
(1 comment)
File doc/supported_hw/supported_prog/serprog/overview.rst:
https://review.coreboot.org/c/flashrom/+/82018/comment/45833a41_84e3820e :
PS1, Line 83: See `the github page <https://github.com/dword1511/serprog-stm32vcp#serprog-stm32vcp>`_ for further details, source code etc.
serprog-stm32vcp has been succeeded by stm32-vserprog of the same author
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Sydney has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/82018?usp=email )
Change subject: doc: Convert serprog docs to rst and add to doc directory
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
Thanks Anastasia for the invitation to review. I looked through the changes and compared them with the wiki and they look good to me.
I would suggest to add some more serprog programmers to the docs but this should happen in a separate change and does not block this change.
The programmers I think which would be interesting to add to the overview are pico-serprog by stacksmashing https://github.com/stacksmashing/pico-serprog and its fork by Riku https://codeberg.org/Riku_V/pico-serprog I could make a change for that ready as I know the projects well. Another notable mention could be the serprog applet of glasgow: https://github.com/GlasgowEmbedded/glasgow/blob/main/software/glasgow/apple…
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Change subject: ichspi.c: Add support for region 9 and beyond in Meteor Lake
......................................................................
Patch Set 10:
(2 comments)
Patchset:
PS10:
> Hsuan Ting, sorry for the delay, and thank you for the patience. I will review this soon! […]
1. I am afraid that I don't have the access to the SPI programming guide for MTL, either. I consulted with Intel expert Jamie (+cc).
2. I could also find these information for MTL:
[BIOS_BM_RAP](https://edc.intel.com/content/www/de/de/design/publications/14…
[BIOS_BM_WAP](https://edc.intel.com/content/www/de/de/design/publications/14…
3. I confirmed with Jamie that we should start to support these from MTL. Also we haven't met this issue in the other platforms. (These issues should be very critical to ChromeOS, so we should be awared of it if it happens)
PS10:
Hi Jamie:
Thanks for your advice on adding region 9 support for MTL!
I've added you as cc for visibility. Feel free to let me know if you have any thoughts or feedback!
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Change subject: ichspi.c: Add support for region 9 and beyond in Meteor Lake
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
Hsuan Ting, sorry for the delay, and thank you for the patience. I will review this soon!
But I wanted to ask my usual question: perhaps there is a datasheet which documents this? is it certain that everything beyond Meteor Lake will follow the same configuration?
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Gerrit-Project: flashrom
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Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com>
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