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Hello build bot (Jenkins), Nico Huber, Caveh Jalali, Tim Wawrzynczak, Rizwan Qureshi, Edward O'Callaghan, Sridhar Siricilla, Nick Vaccaro, Alex Levin, YH Lin, Boris Mittelberg,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/61854
to look at the new patch set (#3).
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
Control register.
This bit remains set until the cycle completes on the SPI interface.
Hardware automatically sets and clears this bit so that software can
determine when read data is valid and/or when it is safe to begin
programming the next command.
Software must initiate the next SPI transaction when this bit is 0.
Added blocking mechanism without timeout to ensure previous SPI
transaction is complete before initiating newer command.
Current debug data suggests that concurrent access to flashrom by user
space utility might run into issues where some operations are getting
timed out without synchronisation.
BUG=b:215255210
TEST=Concurrent flashrom access is not throwing timeout.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484
---
M ichspi.c
1 file changed, 38 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/61854/3
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> > This leaves some questions. Is something broken wrt. arbitration? How does
> arbitration work if two masters set FGO at the same time? is that accounted
> for in the hardware?
>
> Yes this is taken care in the HW. The SPI Ctrlr will queue the transaction of one of the masters until the other is served.
> Thank you Rizwan. That's how I always understood it. However, Subrata's test
result suggest otherwise:
My Bad Nico, I'm also saying the same. This SCIP bit is for each master like when u start a flashrom operation that sets the SCIP bit and attempt to run flashrom using other application (where currently flashrom doesn't bother to look at SCIP even on the same master), we are seeing `timeout` issue in transaction.
Note: there are other tool that uses the flashrom even on running from host (if we leave CSE for now) and if there is no sync mechanism in operations at host side, we will run into the issue.
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Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> This leaves some questions. Is something broken wrt. arbitration? How does
arbitration work if two masters set FGO at the same time? is that accounted
for in the hardware?
Yes this is taken care in the HW. The SPI Ctrlr will queue the transaction of one of the masters until the other is served.
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Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> In regards to H_SCIP. The recommendation is to check this bit before starting a transaction. This indicates a transaction by the same master and not the transactions being served for other masters.
Thank you Rizwan. That's how I always understood it. However, Subrata's test
result suggest otherwise:
> > Have you tested that (and with that I mean that the *host* SCIP bit flips when the
> > CSE uses its own interface)?
> yes, I have verified by making CSE send a storage access command and read the SCIP from host side and host send a command and read the SCIP from CSE side. And there is no specific interface. It's same SPI controller MMIO offset bit 5 read in both cases.
This leaves some questions. Is something broken wrt. arbitration? How does
arbitration work if two masters set FGO at the same time? is that accounted
for in the hardware?
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Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> > > > > > Have you tested that (and with that I mean that the *host* SCIP bit flips when the […]
The SPI controller MMIO registers visible to either masters (CPU and CSE) are separate physical registers
Both the masters are unaware of the of each other's register space
The SPI controller HW is capable to arbitrate between the requests that arrive from individual masters
In regards to H_SCIP. The recommendation is to check this bit before starting a transaction. This indicates a transaction by the same master and not the transactions being served for other masters.
The SBRS register (0xD4) indicates whether a master has an outstanding transaction enqueued or in flight and the transaction type.
hope this clarifies
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Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> > > > > > Have you tested that (and with that I mean that the *host* SCIP bit flips when the
> > > > > > CSE uses its own interface)?
> > > > >
> > > > > yes, I have verified by making CSE send a storage access command and read the SCIP from host side and host send a command and read the SCIP from CSE side. And there is no specific interface. It's same SPI controller MMIO offset bit 5 read in both cases.
> > > >
> > > > Thanks, this is very valuable information! I knew that the CSE uses a similar
> > > > interface, but not that they (the host and the CSE interface) affect each other.
> > > > I just read the register description again and still can't find any clue about
> > > > that. Actually, the description when SCIP will be set looks like it would exclude
> > > > such a case, but it might also just be totally incomplete.
> > > >
> > > > While I pretty much expect such documentation and firmware issues, I have so
> > > > far mostly understood Intel's hardware design choices but I still can't understand
> > > > this one. Now I wonder even more how arbitration with other interfaces worked
> > > > (e.g. memory-mapped access, software sequencing) if at all.
> > >
> > > SW Sq is dropped in ADL so any access to SPI controller is via HW Sq.
> >
> > Yes, but things have worked for 10y+ and I wonder how ;)
>
> Some feature that CSE enables with ADL need sporadic access to CSE RW region. hence, as per CSE team's data, this is expected.
So was everything synchronized before? e.g. applications like AMT didn't need
to access flash? How did it work when a non-volatile variable was updated?
Sorry, my head is full of questions now. Also, when the CSE is booting up,
when does it stop reading from flash? I would have guessed that it doesn't
have enough SRAM to read everything before system DRAM is up and when system
DRAM is up, coreboot already wants to write to flash (e.g. training params
in "MRC cache").
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Change subject: board_enable.c: Add ME unlock function for Clevo laptops
......................................................................
Patch Set 15:
(1 comment)
File board_enable.c:
https://review.coreboot.org/c/flashrom/+/56023/comment/e4dfc80e_d926c6fd
PS2, Line 2335: power off the system and power it on
> After a second thought I think we shall leave the decision to user to do the power off. […]
Ack
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55715 )
Change subject: ite_ec: Implement support for flashing ITE ECs found on TUXEDO laptops
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Patch Set 27:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/55715/comment/9659966f_8b31f0ea
PS27, Line 1: acpi_ec
> Actually no. apic_ec is on purpose. […]
Oh sorry, my fault, I meant line 7 ofc :-)
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
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Patch Set 2:
(1 comment)
Patchset:
PS2:
> > > > > Have you tested that (and with that I mean that the *host* SCIP bit flips when the
> > > > > CSE uses its own interface)?
> > > >
> > > > yes, I have verified by making CSE send a storage access command and read the SCIP from host side and host send a command and read the SCIP from CSE side. And there is no specific interface. It's same SPI controller MMIO offset bit 5 read in both cases.
> > >
> > > Thanks, this is very valuable information! I knew that the CSE uses a similar
> > > interface, but not that they (the host and the CSE interface) affect each other.
> > > I just read the register description again and still can't find any clue about
> > > that. Actually, the description when SCIP will be set looks like it would exclude
> > > such a case, but it might also just be totally incomplete.
> > >
> > > While I pretty much expect such documentation and firmware issues, I have so
> > > far mostly understood Intel's hardware design choices but I still can't understand
> > > this one. Now I wonder even more how arbitration with other interfaces worked
> > > (e.g. memory-mapped access, software sequencing) if at all.
> >
> > SW Sq is dropped in ADL so any access to SPI controller is via HW Sq.
>
> Yes, but things have worked for 10y+ and I wonder how ;)
Some feature that CSE enables with ADL need sporadic access to CSE RW region. hence, as per CSE team's data, this is expected.
>
> >
> > >
> > > Just to be sure, there's no chance that the CSE code is using the host interface
> > > instead of its own, right?
> >
> > No, they can't. CSE has access to SPI region as give via descriptor. And accessing the SPI controller just need to generate the HW seq from CSE side. CSE will have access to it's own region as specified in descriptor base/limit.
>
> I'm not talking about flash regions. Um, you said "It's same SPI controller
> MMIO offset..." but it's just the same register layout, right? Not the same
> physical register?
Yes, it's same register layout. ideally, from code side, it's almost similar flashrom read operation flow that CSE does.
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