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Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> While you are flashing the SPI using flashrom on DUT at S0, there are cases when we are seeing some flashrom failure issue and debug data that we have so far is not very conclusive to say that CSE is doing anything wrong.
Was upstream flashrom used? Why do you assume that the CSE is involved?
I would expect the hardware to coordinate between the different masters. At least,
the SCIP bit can never be enough to synchronize masters. Even with the added
waiting loop, there is still much room for race conditions (e.g. second master
reading SCIP = 0 before the first posted its write to start a cycle).
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Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/61854/comment/a15b4b76_3cb054e8
PS2, Line 23: BUG=b:215255210
> Please describe the issue you encountered.
I have added the issue description below @Nico. So far we don't know if this fix will able to fix the original issue hence tried to capture at the high level what SW expects us to implement and what we missed.
Patchset:
PS2:
> The whole driver works synchronously, i.e. waits for any cycle to finish
> that it started itself. So unless I miss something, checking SCIP would
> only serve us in case of hardware failures or another program trying to
> use the SPI controller at the same time (e.g. broken SMM). In both cases,
> I'd say all bets are off anyway and we should definitely bail out.
>
> Datasheets say to check the SCIP bit; we could just do so once (without
> waiting) and if the bit is set bail out.
@Nico, there are multiple HW agents who also has access to the SPI controller, example: CSE. While you are flashing the SPI using flashrom on DUT at S0, there are cases when we are seeing some flashrom failure issue and debug data that we have so far is not very conclusive to say that CSE is doing anything wrong. There might be case where both CSE and Host CPU attempt to initiate the transaction without any sync mechanism. Apparently on multiple master SPI access case, SW programming says, don't initiate next command unless SCIP is set to zero.
We have verified CSE FW use this implementation to avoid race scenarios but none of HW seq implementation that we have in coreboot/depthcharge/flashrom adheres to the same recommendation so far.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/61854/comment/284f9c57_ac895439
PS2, Line 23: BUG=b:215255210
Please describe the issue you encountered.
Patchset:
PS2:
The whole driver works synchronously, i.e. waits for any cycle to finish
that it started itself. So unless I miss something, checking SCIP would
only serve us in case of hardware failures or another program trying to
use the SPI controller at the same time (e.g. broken SMM). In both cases,
I'd say all bets are off anyway and we should definitely bail out.
Datasheets say to check the SCIP bit; we could just do so once (without
waiting) and if the bit is set bail out.
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Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55715 )
Change subject: ite_ec: Implement support for flashing ITE ECs found on TUXEDO laptops
......................................................................
Patch Set 27:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/55715/comment/88e6fde8_d48c0c29
PS27, Line 1: acpi_ec
> nit: ite_ecfw
Actually no. apic_ec is on purpose. The patch implements the interface described in ACPI specification: https://uefi.org/specs/ACPI/6.4/12_ACPI_Embedded_Controller_Interface_Speci…
ITE EC firmware is compliant with APCI specification to the extent of the registers and functions described in APCI spec and the source file added in this patch,
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Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/61854/comment/eb9c9ef3_248e7cbf
PS1, Line 7: flashrom
> nit: ichspi. […]
Ack
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/61854/comment/879dad7a_9920fea0
PS1, Line 1390: REGREAD32
> Isn't this register 16-bit?
Hardware Sequencing Flash Status and Control
(BIOS_HSFSTS_CTL)—Offset 4h, 32 bit register
https://review.coreboot.org/c/flashrom/+/61854/comment/f5696c66_c8f57313
PS1, Line 1392: } while ((hsfsts & HSFS_SCIP) == HSFS_SCIP);
> This loop could potentially never exit.
It depends on HW operation and here is what EDS says, so, I believe we might not run into such issue. Also, *Software must only program the next command when this bit is 0.*
SPI Cycle In Progress (H_SCIP): Hardware sets this bit when software sets the
Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register.
This bit remains set until the cycle completes on the SPI interface. Hardware
automatically sets and clears this bit so that software can determine when read data
is valid and/or when it is safe to begin programming the next command.
Software must only program the next command when this bit is 0.
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Hello build bot (Jenkins), Nico Huber, Caveh Jalali, Tim Wawrzynczak, Rizwan Qureshi, Edward O'Callaghan, Nick Vaccaro, Alex Levin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/61854
to look at the new patch set (#2).
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
Control register.
This bit remains set until the cycle completes on the SPI interface.
Hardware automatically sets and clears this bit so that software can
determine when read data is valid and/or when it is safe to begin
programming the next command.
Software must initiate the next SPI transaction when this bit is 0.
Added blocking mechanism without timeout to ensure previous SPI
transaction is complete before initiating newer command.
BUG=b:215255210
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484
---
M ichspi.c
1 file changed, 38 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/61854/2
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/61854 )
Change subject: flashrom: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
flashrom: Check SPI Cycle In-Progress prior start HW Seq
As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
Control register.
This bit remains set until the cycle completes on the SPI interface.
Hardware automatically sets and clears this bit so that software can
determine when read data is valid and/or when it is safe to begin
programming the next command.
Software must initiate the next SPI transaction when this bit is 0.
Added blocking mechanism without timeout to ensure previous SPI
transaction is complete before initiating newer command.
BUG=b:215255210
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484
---
M ichspi.c
1 file changed, 38 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/61854/1
diff --git a/ichspi.c b/ichspi.c
index 117ff8d..ac4e3eb 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1366,6 +1366,35 @@
return 1;
}
+/*
+ * As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
+ * sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
+ * Control register.
+ *
+ * This bit remains set until the cycle completes on the SPI interface.
+ * Hardware automatically sets and clears this bit so that software can
+ * determine when read data is valid and/or when it is safe to begin
+ * programming the next command.
+ *
+ * Software must initiate the next SPI transaction when this bit is 0.
+ *
+ * Added blocking mechanism without timeout to ensure previous SPI transaction
+ * is complete before initiating newer command.
+ */
+static void ich_wait_for_hwseq_spi_cycle_complete(void)
+{
+ uint32_t hsfsts;
+
+ msg_pspew("SPI Transaction in progress ");
+ do {
+ hsfsts = REGREAD32(ICH9_REG_HSFS);
+ msg_pspew("..");
+ } while ((hsfsts & HSFS_SCIP) == HSFS_SCIP);
+
+ msg_pspew("\nSPI Transaction done!\n");
+ return;
+}
+
static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
unsigned int len)
{
@@ -1396,6 +1425,9 @@
return -1;
}
+ /* Wait for previous SPI cycle to complete */
+ ich_wait_for_hwseq_spi_cycle_complete();
+
msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
ich_hwseq_set_addr(addr);
@@ -1438,6 +1470,9 @@
/* as well as flash chip page borders as demanded in the Intel datasheets. */
block_len = min(block_len, 256 - (addr & 0xFF));
+ /* Wait for previous SPI cycle to complete */
+ ich_wait_for_hwseq_spi_cycle_complete();
+
ich_hwseq_set_addr(addr);
hsfc = REGREAD16(ICH9_REG_HSFC);
hsfc &= ~hwseq_data.hsfc_fcycle; /* set read operation */
@@ -1474,6 +1509,9 @@
REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
while (len > 0) {
+ /* Wait for previous SPI cycle to complete */
+ ich_wait_for_hwseq_spi_cycle_complete();
+
ich_hwseq_set_addr(addr);
/* Obey programmer limit... */
block_len = min(len, flash->mst->opaque.max_data_write);
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Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61578 )
Change subject: internal.c: Seperate out get_params() from internal_init()
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/61578/comment/6960221d_75d2aa88
PS2, Line 13: TEST=`make`
> Does this need anymore testing? like `flashrom -p internal` for example?
Tested on dooly / Comet Lake DUT.
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