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Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
> Can you please help me to understand how this was applicable here ? […]
@Nico, here is guideline above giving `-2` in coreboot code review, looks like you are ignoring the prior comments and discussion about this thread to understand what is the chipset recommendation from Intel and what is being done in flashrom. As suggested below, please bring your recommendation along with `-2`.
@Rizwan, please help to address the SPI recommendation and point out to the documentation if you can to ease the situation. I honestly don't know what Nico meant by "cover up the actual problem".
If you give a patch a -2, you are responsible for giving concrete recommendations for what could be changed to resolve the issue the patch addresses. If you feel strongly that a patch should NEVER be merged, you are responsible for defending your position and listening to other points of view. Giving a -2 and walking away is not acceptable, and may cause your -2 to be removed by the coreboot leadership after no less than a week. A notification that the -2 will be removed unless there is a response will be sent out at least 2 days before it is removed.
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Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
> Can you please help me to understand how this was applicable here ? […]
@Nico, i didn't understand the comment about "cover up the actual problem", the code change in question is not a work around, but a recommendation in the chipset EDS.
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Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
> Loops are unacceptable here because they only cover up the actual […]
Can you please help me to understand how this was applicable here ?
https://github.com/flashrom/flashrom/blob/master/ichspi.c#L968
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Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 6: Code-Review-2
(1 comment)
Patchset:
PS6:
Loops are unacceptable here because they only cover up the actual
problem and make the whole code look ill-considered.
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Change subject: ite_ecfw: Implement support for flashing ITE ECs found on TUXEDO laptops
......................................................................
Patch Set 28:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/55715/comment/c0aab6e2_e0ddf3a1
PS27, Line 1: acpi_ec
> Oh sorry, my fault, I meant line 7 ofc :-)
Done
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Hello Felix Singer, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/55715
to look at the new patch set (#28).
Change subject: ite_ecfw: Implement support for flashing ITE ECs found on TUXEDO laptops
......................................................................
ite_ecfw: Implement support for flashing ITE ECs found on TUXEDO laptops
Add a new programmer supporting ITE Embedded Controllers found on
TUXEDO laptops. Tested on TUXEDO InfinityBook S 14 Gen6 and 15 Gen6
with EC firmware updates from IBV, EC versions 1.07.02TR1 and
1.07.04TR4.
Example standard command to update EC firmware on a TUXEDO laptop:
"flashrom -p ite_ec:romsize=128K,autoload=disable -w eL14MU02.TR1"
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
Change-Id: I0e42260155ffea38a6f60790871cd8da7b657031
---
M Makefile
M flashrom.8.tmpl
M it87spi.c
A ite_ecfw.c
A ite_ecfw.h
M meson.build
M meson_options.txt
M programmer.h
M programmer_table.c
9 files changed, 1,124 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/15/55715/28
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Attention is currently required from: Nico Huber, Caveh Jalali, Rizwan Qureshi, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Nick Vaccaro, Alex Levin, YH Lin, Boris Mittelberg.
Hello build bot (Jenkins), Nico Huber, Caveh Jalali, Rizwan Qureshi, Tim Wawrzynczak, Edward O'Callaghan, Sridhar Siricilla, Nick Vaccaro, Alex Levin, YH Lin, Boris Mittelberg,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/61854
to look at the new patch set (#6).
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
Control register.
This bit remains set until the cycle completes on the SPI interface.
Hardware automatically sets and clears this bit so that software can
determine when read data is valid and/or when it is safe to begin
programming the next command.
Software must initiate the next SPI transaction when this bit is 0.
Without this synchronisation being implemented, flashrom is running
into below error:
Erasing and writing flash chip... Timeout error between offset
0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED!
Uh oh. Erase/write failed. Checking if anything has changed.
Added non-blocking timeout mechanism to ensure previous SPI transaction
is complete before initiating newer command. Current debug data suggests
that concurrent access to flashrom by user space utility might run into
issues where some operations are getting timed out without
synchronisation.
BUG=b:215255210
TEST=Concurrent flashrom access is not throwing timeout.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484
---
M ichspi.c
1 file changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/61854/6
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Hello build bot (Jenkins), Nico Huber, Caveh Jalali, Rizwan Qureshi, Tim Wawrzynczak, Edward O'Callaghan, Sridhar Siricilla, Nick Vaccaro, Alex Levin, YH Lin, Boris Mittelberg,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/61854
to look at the new patch set (#5).
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
Control register.
This bit remains set until the cycle completes on the SPI interface.
Hardware automatically sets and clears this bit so that software can
determine when read data is valid and/or when it is safe to begin
programming the next command.
Software must initiate the next SPI transaction when this bit is 0.
Without this synchronisation being implemented, flashrom is running
into below error:
Erasing and writing flash chip... Timeout error between offset
0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED!
Uh oh. Erase/write failed. Checking if anything has changed.
Added non-blocking timeout mechanism to ensure previous SPI transaction
is complete before initiating newer command. Current debug data suggests
that concurrent access to flashrom by user space utility might run into
issues where some operations are getting timed out without
synchronisation.
BUG=b:215255210
TEST=Concurrent flashrom access is not throwing timeout.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484
---
M ichspi.c
1 file changed, 44 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/61854/5
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