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Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 4:
(1 comment)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/61854/comment/fa475944_456c50fc
PS3, Line 1392: while
> > @Angel pons already pointed this! I'm closing the comment here. […]
It depends on the criticality of the operation that the application is doing. We can assume that the operation can be retried at a later time I suggest that better be a timeout.
Or may be a command-line option for the user to decide, may be an overkill 😊
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS2:
> If there is a Hardware Sequencing Cycle In Progress and an attempt is made to program any of the control, address, or data register the cycle is blocked and the FCERR bit is set. So a check is required in flashrom on H_SCIP, so that multiple instances (on same master) do not cancel each other's requests.
Please see this, prior to Intel HW seq, we always used SCIP for syncing between the operations.
https://github.com/flashrom/flashrom/blob/master/ichspi.c#L968
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Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/59238 )
Change subject: tests: Add comprehensive comment for chip.c
......................................................................
tests: Add comprehensive comment for chip.c
The following describes the two mechanisms of testing done for
flash chip operations.
BUG=b:181803212
TEST=ninja test
Change-Id: Ie498ec55cce8460fc0b2e1fe27254d3a9f763fac
Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59238
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Singer <felixsinger(a)posteo.net>
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---
M tests/chip.c
1 file changed, 12 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Singer: Looks good to me, approved
Edward O'Callaghan: Looks good to me, approved
diff --git a/tests/chip.c b/tests/chip.c
index fd7094c..798199c 100644
--- a/tests/chip.c
+++ b/tests/chip.c
@@ -11,6 +11,18 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
+ *
+ * This file contains tests for operations on flash chip.
+ *
+ * Two flash chip test variants are used:
+ *
+ * 1) Mock chip state backed by `g_chip_state`.
+ * Example of test: erase_chip_test_success.
+ *
+ * 2) Mock chip operations backed by `dummyflasher` emulation.
+ * Dummyflasher controls chip state and emulates read/write/unlock/erase.
+ * `g_chip_state` is NOT used for this type of tests.
+ * Example of test: erase_chip_with_dummyflasher_test_success.
*/
#include <include/test.h>
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Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/59237 )
Change subject: tests: Set up mock chip memory in consistent and predictable way
......................................................................
tests: Set up mock chip memory in consistent and predictable way
This patch adds a macro MOCK_CHIP_CONTENT which represents a memory
state of a mock chip. The macro is used to initialise mock chip
memory at the beginning of a test (in setup_chip function).
Previously mock chip memory was not reset between tests. For
existing tests that did not matter, however new test for verify
operation (added later in this chain) needs mock chip memory to
be setup in a predictable way.
BUG=b:181803212
TEST=ninja test
Change-Id: I0d7623a601c207bfc62d54ab89d94cda56d85871
Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59237
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---
M tests/chip.c
1 file changed, 2 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Singer: Looks good to me, approved
Edward O'Callaghan: Looks good to me, approved
diff --git a/tests/chip.c b/tests/chip.c
index 5d646eb..fd7094c 100644
--- a/tests/chip.c
+++ b/tests/chip.c
@@ -23,6 +23,7 @@
#include "programmer.h"
#define MOCK_CHIP_SIZE (8*MiB)
+#define MOCK_CHIP_CONTENT 0xff
static struct {
unsigned int unlock_calls; /* how many times unlock function was called */
@@ -93,6 +94,7 @@
flashctx->chip = chip;
g_chip_state.unlock_calls = 0;
+ memset(g_chip_state.buf, MOCK_CHIP_CONTENT, sizeof(g_chip_state.buf));
printf("Creating layout with one included region... ");
assert_int_equal(0, flashrom_layout_new(layout));
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Change subject: tests: Set up mock chip memory in consistent and predictable way
......................................................................
Patch Set 7: Code-Review+2
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Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
Patchset:
PS2:
> > > > > > This leaves some questions. Is something broken wrt. arbitration? How does […]
If there is a Hardware Sequencing Cycle In Progress and an attempt is made to program any of the control, address, or data register the cycle is blocked and the FCERR bit is set. So a check is required in flashrom on H_SCIP, so that multiple instances (on same master) do not cancel each other's requests.
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Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61897 )
Change subject: libflashrom,linux_mtd: add linux_mtd writeprotect support
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
draft version of the patch, will test tomorrow, early comments welcome
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