Attention is currently required from: Edward O'Callaghan, Nikolai Artemiev.
Hello Edward O'Callaghan, Nikolai Artemiev, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/77999?usp=email
to look at the new patch set (#2).
Change subject: raiden: Support target index with generic REQ_ENABLE
......................................................................
raiden: Support target index with generic REQ_ENABLE
Some devices such as the GSC knows how it is wired to AP and EC flash
chips, and can be told which specific device to talk to. Other devices
such as Servo Micro and HyperDebug are generic, and do not know how they
are wired, the caller is responsible for first configure the appropriate
MUXes or buffers, and then tell the debugger which port to use (Servo
Micro has just one SPI port, HyperDebug is the first that has multiple).
The Raiden protocol allows both the cases of USB devices knowing their
wiring and not.
If I were to declare the protocol in Rust, this is how the information
of the Raiden protocol "enable request" would be encoded:
```
enum {
EnableGeneric(u8),
EnableAp,
EnableEc,
...
}
```
The first label `EnableGeneric(u8)` is to be used with HyperDebug that
does not know how its ports are wired, and allow access by index.
The other labels `EnableAp` and `EnableEc` are to be used with the GSC.
The actual transmission of the enum above uses the bRequest and low byte
of wValue of a USB control request, but that is a detail and not
conceptually important.
Until now, `-p raiden_debug_spi:target=AP` or `...:target=EC` could be
used to make flashrom use `EnableAp` or `EnableEc`, and if neither was
given, it would default to `EnableGeneric`, which now that wValue is
used means `EnableGeneric(0)`.
I find it rather straight-forward, that `-p raiden_debug_spi:target=1`,
`...:target=2`, etc. should translate to `EnableGeneric(1)`, etc.
This CL archieves this, by encoding the parameter to `EnableGeneric` as
the second byte of the request_enable integer value.
TEST=run flashrom with HyperDebug
Signed-off-by: Jes B. Klinke <jbk(a)chromium.org>
Change-Id: I03bf4f3210186fb5937b42e298761907b03e08b7
---
M raiden_debug_spi.c
1 file changed, 10 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/99/77999/2
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Gerrit-Change-Number: 77999
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Jes Klinke has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/77999?usp=email )
Change subject: raiden: Support target index with generic REQ_ENABLE
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
This is a copy of: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/…
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Jes Klinke has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/77999?usp=email )
Change subject: raiden: Support target index with generic REQ_ENABLE
......................................................................
raiden: Support target index with generic REQ_ENABLE
Some devices such as the GSC knows how it is wired to AP and EC flash
chips, and can be told which specific device to talk to. Other devices
such as Servo Micro and HyperDebug are generic, and do not know how they
are wired, the caller is responsible for first configure the appropriate
MUXes or buffers, and then tell the debugger which port to use (Servo
Micro has just one SPI port, HyperDebug is the first that has multiple).
The Raiden protocol allows both the cases of USB devices knowing their
wiring and not.
If I were to declare the protocol in Rust, this is how the information
of the "enable request" would be encoded:
```
enum {
EnableGeneric(u8),
EnableAp,
EnableEc,
...
}
```
The first label `EnableGeneric(u8)` is to be used with HyperDebug that
does not know how its ports are wired, and allow access by index.
The other labels `EnableAp` and `EnableEc` are to be used with the GSC.
The actual transmission of the enum above uses the bRequest and low byte
of wValue of a USB control request, but that is a detail and not
conceptually important.
Until now, `target=AP` or `target=EC` could be used to make flashrom use
`EnableAp` or `EnableEc`, and if neither was given, it would default to
`EnableGeneric`, which now that wValue is used means `EnableGeneric(0)`.
I find it rather straight-forward, that `target=1`, `target=2`,
etc. should translate to `EnableGeneric(1)`, etc.
This CL archieves this, by encoding the parameter to `EnableGeneric` as
the second byte of the request_enable integer value.
TEST=run flashrom with HyperDebug
Signed-off-by: Jes B. Klinke <jbk(a)chromium.org>
Change-Id: I03bf4f3210186fb5937b42e298761907b03e08b7
---
M raiden_debug_spi.c
1 file changed, 10 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/99/77999/1
diff --git a/raiden_debug_spi.c b/raiden_debug_spi.c
index c5642ff..4f2e35b 100644
--- a/raiden_debug_spi.c
+++ b/raiden_debug_spi.c
@@ -1460,7 +1460,11 @@
char *target_str = extract_programmer_param_str(cfg, "target");
if (target_str) {
- if (!strcasecmp(target_str, "ap"))
+ char *endptr;
+ int index = strtol(target_str, &endptr, 0);
+ if (*target_str && !*endptr && index >= 0 && index < 256) {
+ request_enable = RAIDEN_DEBUG_SPI_REQ_ENABLE | (index << 8);
+ } else if (!strcasecmp(target_str, "ap"))
request_enable = get_ap_request_type(cfg);
else if (!strcasecmp(target_str, "ec"))
request_enable = RAIDEN_DEBUG_SPI_REQ_ENABLE_EC;
@@ -1470,7 +1474,9 @@
}
}
free(target_str);
- msg_pinfo("Raiden target: %d\n", request_enable);
+ if (request_enable >= 0)
+ msg_pinfo("Raiden target: %d,%d\n",
+ request_enable & 0xFF, (request_enable >> 8) & 0xFF);
return request_enable;
}
@@ -1587,8 +1593,8 @@
LIBUSB_ENDPOINT_OUT |
LIBUSB_REQUEST_TYPE_VENDOR |
LIBUSB_RECIPIENT_INTERFACE,
- request_enable,
- 0,
+ request_enable & 0xFF,
+ (request_enable >> 8) & 0xFF,
device->interface_descriptor->bInterfaceNumber,
NULL,
0,
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Gerrit-Change-Number: 77999
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Gerrit-MessageType: newchange
Attention is currently required from: Patrick Georgi, Stefan Reinauer, Thomas Heijligen.
Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/75706?usp=email )
Change subject: tree: Rename master branch to main
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/75706/comment/025bde69_3c175823 :
PS1, Line 7: Switch over master branch to main
> Rename master branch to main […]
Done
Patchset:
PS1:
> Here are new Dev guidelines! CB:75906 :)
I updated dev guide and uploaded new patchset.
Patchset:
PS2:
I think this patch can be reviewed/approved now, but it needs to be submitted only after the branch is actually renamed (ideally as soon as possible after the renaming).
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Attention is currently required from: Stefan Reinauer.
Anastasia Klimchuk has uploaded a new patch set (#2) to the change originally created by Stefan Reinauer. ( https://review.coreboot.org/c/flashrom/+/75706?usp=email )
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: tree: Rename master branch to main
......................................................................
tree: Rename master branch to main
Change-Id: I8f4a377735f3f6ab4a22006949ff294a218bdf22
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M doc/dev_guide/development_guide.rst
M util/manibuilder/Makefile
M util/manibuilder/README.md
3 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/06/75706/2
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/77581?usp=email )
Change subject: flashchips: Add support for MXIC MX25U25643G
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
xianzheng, CB:76853 already added your chip, so I don't think you need anything else to do. CB:76853 is submitted, so the chip is added. Well done!
What is one last thing you can do here: is to abandon this patch (you should have the button "Abandon" in the top right corner).
If you are planning to add another chip, you will need to create new patch for that.
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Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/77581?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: flashchips: Add support for MXIC MX25U25643G
......................................................................
flashchips: Add support for MXIC MX25U25643G
It is similar to the MX25U25635F and shares its RDID.
Tested by ch341a programmer : read, write and erase.
Datasheet is available at the following URL:
https://www.mxic.com.tw/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/spe…
Change-Id: Id6c4254a02800f04c091009d19a628435fc20fce
Signed-off-by: xianzheng <xianzheng(a)mxic.com.cn>
---
M flashchips.c
M include/flashchips.h
2 files changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/81/77581/4
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Change subject: flashrom_tester: Align WP output format with upstream
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Hi Edware, Could you please help to submit this change? Thanks.
Sorry for the typo. Edward.
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Change subject: flashrom_tester: Align WP output format with upstream
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Hi Edware, Could you please help to submit this change? Thanks.
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Alexander Goncharov has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/77747?usp=email )
Change subject: erasure_layout: Fix double invocation of erasers
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Oh I missed that issue, sorry :(( I assigned to myself so that it's not missed.
I still encounter an error. Added comments and logs in the issue tracker.
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