May 2023 - flashrom-gerrit - mail.coreboot.org

[M] Change in flashrom[master]: spi: add cs=tms option to jlink_spi programmer
by Anastasia Klimchuk (Code Review) 09 May '23

09 May '23

Attention is currently required from: Chen, Alexander Goncharov. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/75011 ) Change subject: spi: add cs=tms option to jlink_spi programmer ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Chen, thank you for the patch! It's a nice and clean change, looks good! I have a question about testing: you probably tested this on hardware? Can you add testing info in commit message? Thanks! -- To view, visit https://review.coreboot.org/c/flashrom/+/75011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0cb467fcc2c403a25f260462de0cd020e7022bb1 Gerrit-Change-Number: 75011 Gerrit-PatchSet: 1 Gerrit-Owner: Chen <c(a)jia.je> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen <c(a)jia.je> Gerrit-Attention: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Comment-Date: Tue, 09 May 2023 12:13:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashrom.c: Enable erase path optimisation
by Anastasia Klimchuk (Code Review) 09 May '23

09 May '23

Attention is currently required from: Simon Buhrow, Thomas Heijligen, Edward O'Callaghan, Aarya, Nikolai Artemiev. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/74872 ) Change subject: flashrom.c: Enable erase path optimisation ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Patchset: PS2: > It's worth noting that `region->write_prot` is used to indicate a different type of protection to no […] Thanks Edward and Nikolai for your help! Bug fixed and merged CB:74882 -- To view, visit https://review.coreboot.org/c/flashrom/+/74872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie13e43b18b20dbb956b569e554953a19eb32ea22 Gerrit-Change-Number: 74872 Gerrit-PatchSet: 4 Gerrit-Owner: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Tue, 09 May 2023 08:50:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Comment-In-Reply-To: Aarya <aarya.chaumal(a)gmail.com> Comment-In-Reply-To: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashrom.c: Enable erase path optimisation
by Aarya (Code Review) 09 May '23

09 May '23

Attention is currently required from: Simon Buhrow, Thomas Heijligen, Edward O'Callaghan, Anastasia Klimchuk. Aarya has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/74872 ) Change subject: flashrom.c: Enable erase path optimisation ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/74872/comment/bd565d45_6c0dd67c PS3, Line 7: :E > Add space after : Done https://review.coreboot.org/c/flashrom/+/74872/comment/d2c37c85_35043b1f PS3, Line 9: flase > false Done https://review.coreboot.org/c/flashrom/+/74872/comment/7d5fed5b_fc2f9d13 PS3, Line 10: optmisatoptimisation > just one "optimisation" is enough :) Done -- To view, visit https://review.coreboot.org/c/flashrom/+/74872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie13e43b18b20dbb956b569e554953a19eb32ea22 Gerrit-Change-Number: 74872 Gerrit-PatchSet: 4 Gerrit-Owner: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Tue, 09 May 2023 07:48:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashrom.c: Enable erase path optimisation
by Aarya (Code Review) 09 May '23

09 May '23

Attention is currently required from: Simon Buhrow, Thomas Heijligen, Edward O'Callaghan, Aarya. Hello Simon Buhrow, build bot (Jenkins), Thomas Heijligen, Edward O'Callaghan, Anastasia Klimchuk, Nikolai Artemiev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/74872 to look at the new patch set (#4). Change subject: flashrom.c: Enable erase path optimisation ...................................................................... flashrom.c: Enable erase path optimisation Set the use_legacy_erase_path flag to false to enable erase path optimisation by default. Change-Id: Ie13e43b18b20dbb956b569e554953a19eb32ea22 Signed-off-by: Aarya Chaumal <aarya.chaumal(a)gmail.com> --- M flashrom.c 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/72/74872/4 -- To view, visit https://review.coreboot.org/c/flashrom/+/74872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie13e43b18b20dbb956b569e554953a19eb32ea22 Gerrit-Change-Number: 74872 Gerrit-PatchSet: 4 Gerrit-Owner: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in flashrom[master]: tests/chip_wp.c: Allow for logging during test
by Anastasia Klimchuk (Code Review) 09 May '23

09 May '23

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/74932 ) Change subject: tests/chip_wp.c: Allow for logging during test ...................................................................... tests/chip_wp.c: Allow for logging during test Hook logging callback so unit-tests print what they are doing. This make debug far easier for a failing test. BUG=none TEST=ninja test. Change-Id: I7ab0ff0915a76eea9857fc876493615c06193a37 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/74932 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M tests/chip_wp.c 1 file changed, 27 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/tests/chip_wp.c b/tests/chip_wp.c index 2686f44..1fa6bb9 100644 --- a/tests/chip_wp.c +++ b/tests/chip_wp.c @@ -24,6 +24,12 @@ #include "programmer.h" #include "tests.h" +static int unittest_print_cb(enum flashrom_log_level level, const char *fmt, va_list ap) +{ + if (level > FLASHROM_MSG_INFO) return 0; + return vfprintf(stderr, fmt, ap); +} + /* * Tests in this file do not use any mocking, because using write-protect * emulation in dummyflasher programmer is sufficient @@ -47,6 +53,8 @@ flashrom_layout_set(flash, *layout); } + flashrom_set_log_callback((flashrom_log_callback *)&unittest_print_cb); + assert_int_equal(0, programmer_init(&programmer_dummy, programmer_param)); /* Assignment below normally happens while probing, but this test is not probing. */ flash->mst = &registered_masters[0]; -- To view, visit https://review.coreboot.org/c/flashrom/+/74932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7ab0ff0915a76eea9857fc876493615c06193a37 Gerrit-Change-Number: 74932 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in flashrom[master]: flashrom: Use WP-based unlocking on opaque masters
by Anastasia Klimchuk (Code Review) 09 May '23

09 May '23

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/74930 ) Change subject: flashrom: Use WP-based unlocking on opaque masters ...................................................................... flashrom: Use WP-based unlocking on opaque masters Flashrom only tries to use WP-based unlocking if it detects that WP operations are supported. However WP support was detected in a way that ignored WP operations provided by opaque masters. This stopped flashrom from automatically unlocking with some opaque masters, particularly linux_mtd. This commit also deletes part of a test that required the chip unlock function to be called before read/write/erase operations because WP unlocking is now used instead of chip unlocking. BUG=b:280111380 BRANCH=none TEST=Checked flashrom automatically unlocked flash on strongbad (MTD) Change-Id: I1774ad64d82ae47cd085df6045e17e283855c01f Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/74930 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M flashrom.c M include/flash.h M spi25_statusreg.c M tests/chip.c 4 files changed, 32 insertions(+), 42 deletions(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved Sergii Dmytruk: Looks good to me, approved diff --git a/flashrom.c b/flashrom.c index 07ed0df..faffe51 100644 --- a/flashrom.c +++ b/flashrom.c @@ -2093,7 +2093,8 @@ /* Given the existence of read locks, we want to unlock for read, erase and write. */ int ret = 1; - if (flash->chip->decode_range != NO_DECODE_RANGE_FUNC) { + if (flash->chip->decode_range != NO_DECODE_RANGE_FUNC || + (flash->mst->buses_supported & BUS_PROG && flash->mst->opaque.wp_write_cfg)) { ret = unlock_flash_wp(flash); if (ret) msg_cerr("Failed to unlock flash status reg with wp support.\n"); diff --git a/include/flash.h b/include/flash.h index 3e9c885..0eace15 100644 --- a/include/flash.h +++ b/include/flash.h @@ -348,7 +348,6 @@ UNLOCK_LH28F008BJT, UNLOCK_SST_FWHUB, UNPROTECT_28SF040, - TEST_UNLOCK_INJECTOR, /* special case must come last. */ }; enum printlock_func { diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 60e0b46..fa276f7 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -914,9 +914,6 @@ return spi_disable_blockprotect_bp2_srwd(flash); } -/* special unit-test hook */ -blockprotect_func_t *g_test_unlock_injector; - blockprotect_func_t *lookup_blockprotect_func_ptr(const struct flashchip *const chip) { switch (chip->unlock) { @@ -948,7 +945,6 @@ return lookup_82802ab_blockprotect_func_ptr(chip); case UNLOCK_SST_FWHUB: return unlock_sst_fwhub; /* sst_fwhub.c */ case UNPROTECT_28SF040: return unprotect_28sf040; /* sst28sf040.c */ - case TEST_UNLOCK_INJECTOR: return g_test_unlock_injector; /* default: non-total function, 0 indicates no unlock function set. * We explicitly do not want a default catch-all case in the switch * to ensure unhandled enum's are compiler warnings. diff --git a/tests/chip.c b/tests/chip.c index 6a17d86..96be7b1 100644 --- a/tests/chip.c +++ b/tests/chip.c @@ -20,7 +20,7 @@ * Example of test: erase_chip_test_success. * * 2) Mock chip operations backed by `dummyflasher` emulation. - * Dummyflasher controls chip state and emulates read/write/unlock/erase. + * Dummyflasher controls chip state and emulates read/write/erase. * `g_chip_state` is NOT used for this type of tests. * Example of test: erase_chip_with_dummyflasher_test_success. */ @@ -40,20 +40,14 @@ #define MOCK_CHIP_CONTENT 0xCC /* 0x00 is a zeroed heap and 0xFF is an erased chip. */ static struct { - unsigned int unlock_calls; /* how many times unlock function was called */ uint8_t buf[MOCK_CHIP_SIZE]; /* buffer of total size of chip, to emulate a chip */ } g_chip_state = { - .unlock_calls = 0, .buf = { 0 }, }; static int read_chip(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { printf("Read chip called with start=0x%x, len=0x%x\n", start, len); - if (!g_chip_state.unlock_calls) { - printf("Error while reading chip: unlock was not called.\n"); - return 1; - } assert_in_range(start + len, 0, MOCK_CHIP_SIZE); @@ -64,10 +58,6 @@ static int write_chip(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) { printf("Write chip called with start=0x%x, len=0x%x\n", start, len); - if (!g_chip_state.unlock_calls) { - printf("Error while writing chip: unlock was not called.\n"); - return 1; - } assert_in_range(start + len, 0, MOCK_CHIP_SIZE); @@ -75,26 +65,9 @@ return 0; } -static int unlock_chip(struct flashctx *flash) -{ - printf("Unlock chip called\n"); - g_chip_state.unlock_calls++; - - if (g_chip_state.unlock_calls > 1) { - printf("Error: Unlock called twice\n"); - return -1; - } - - return 0; -} - static int block_erase_chip(struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen) { printf("Block erase called with blockaddr=0x%x, blocklen=0x%x\n", blockaddr, blocklen); - if (!g_chip_state.unlock_calls) { - printf("Error while erasing chip: unlock was not called.\n"); - return 1; - } assert_in_range(blockaddr + blocklen, 0, MOCK_CHIP_SIZE); @@ -109,7 +82,6 @@ flashctx->chip = chip; - g_chip_state.unlock_calls = 0; memset(g_chip_state.buf, MOCK_CHIP_CONTENT, sizeof(g_chip_state.buf)); printf("Creating layout with one included region... "); @@ -149,7 +121,6 @@ extern write_func_t *g_test_write_injector; extern read_func_t *g_test_read_injector; extern erasefunc_t *g_test_erase_injector; -extern blockprotect_func_t *g_test_unlock_injector; static const struct flashchip chip_8MiB = { .vendor = "aklm", @@ -157,7 +128,6 @@ .tested = TEST_OK_PREW, .read = TEST_READ_INJECTOR, .write = TEST_WRITE_INJECTOR, - .unlock = TEST_UNLOCK_INJECTOR, .block_erasers = {{ /* All blocks within total size of the chip. */ @@ -173,7 +143,6 @@ .tested = TEST_OK_PREW, .read = SPI_CHIP_READ, .write = SPI_CHIP_WRITE256, - .unlock = SPI_DISABLE_BLOCKPROTECT, .page_size = 256, .block_erasers = { @@ -211,7 +180,6 @@ g_test_write_injector = write_chip; g_test_read_injector = read_chip; g_test_erase_injector = block_erase_chip; - g_test_unlock_injector = unlock_chip; struct flashrom_flashctx flashctx = { 0 }; struct flashrom_layout *layout; struct flashchip mock_chip = chip_8MiB; @@ -271,7 +239,6 @@ g_test_write_injector = write_chip; g_test_read_injector = read_chip; g_test_erase_injector = block_erase_chip; - g_test_unlock_injector = unlock_chip; struct flashrom_flashctx flashctx = { 0 }; struct flashrom_layout *layout; struct flashchip mock_chip = chip_8MiB; @@ -347,7 +314,6 @@ g_test_write_injector = write_chip; g_test_read_injector = read_chip; g_test_erase_injector = block_erase_chip; - g_test_unlock_injector = unlock_chip; struct flashrom_flashctx flashctx = { 0 }; struct flashrom_layout *layout; struct flashchip mock_chip = chip_8MiB; @@ -539,7 +505,6 @@ g_test_write_injector = write_chip; g_test_read_injector = read_chip; g_test_erase_injector = block_erase_chip; - g_test_unlock_injector = unlock_chip; struct flashrom_flashctx flashctx = { 0 }; struct flashrom_layout *layout; struct flashchip mock_chip = chip_8MiB; -- To view, visit https://review.coreboot.org/c/flashrom/+/74930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1774ad64d82ae47cd085df6045e17e283855c01f Gerrit-Change-Number: 74930 Gerrit-PatchSet: 5 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in flashrom[master]: spi: add cs=tms option to jlink_spi programmer
by Chen (Code Review) 08 May '23

08 May '23

Chen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/75011 ) Change subject: spi: add cs=tms option to jlink_spi programmer ...................................................................... spi: add cs=tms option to jlink_spi programmer Currently, the code assumes the nCS pin of spi nor flash is connected to either nRESET(pin 15) or nTRST(pin 3). But it is incompatible with the pinout from official JFlash SPI, whereas the nCS pin is wired to TMS(pin 7). This commit adds cs=tms option to share the same pinout as JFlash SPI. It works by toggling TMS in assert_cs and deassert_cs, and sets TMS to zero in jlink_spi_send_command. The default option is set to cs=reset for backward compatibility. Change-Id: I0cb467fcc2c403a25f260462de0cd020e7022bb1 Signed-off-by: Jiajie Chen <c(a)jia.je> --- M jlink_spi.c 1 file changed, 58 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/11/75011/1 diff --git a/jlink_spi.c b/jlink_spi.c index af61fb5..1d6ad9b 100644 --- a/jlink_spi.c +++ b/jlink_spi.c @@ -51,10 +51,16 @@ /* Minimum target voltage required for operation in mV. */ #define MIN_TARGET_VOLTAGE 1200 +enum cs_wiring { + CS_RESET, /* nCS is wired to nRESET(pin 15) */ + CS_TRST, /* nCS is wired to nTRST(pin 3) */ + CS_TMS, /* nCS is wired to TMS/nCS(pin 7) */ +}; + struct jlink_spi_data { struct jaylink_context *ctx; struct jaylink_device_handle *devh; - bool reset_cs; + enum cs_wiring cs; bool enable_target_power; }; @@ -62,20 +68,27 @@ { int ret; - if (jlink_data->reset_cs) { + if (jlink_data->cs == CS_RESET) { ret = jaylink_clear_reset(jlink_data->devh); if (ret != JAYLINK_OK) { msg_perr("jaylink_clear_reset() failed: %s.\n", jaylink_strerror(ret)); return false; } - } else { + } else if (jlink_data->cs == CS_TRST) { ret = jaylink_jtag_clear_trst(jlink_data->devh); if (ret != JAYLINK_OK) { msg_perr("jaylink_jtag_clear_trst() failed: %s.\n", jaylink_strerror(ret)); return false; } + } else { + ret = jaylink_jtag_clear_tms(jlink_data->devh); + + if (ret != JAYLINK_OK) { + msg_perr("jaylink_jtag_clear_tms() failed: %s.\n", jaylink_strerror(ret)); + return false; + } } return true; @@ -85,20 +98,27 @@ { int ret; - if (jlink_data->reset_cs) { + if (jlink_data->cs == CS_RESET) { ret = jaylink_set_reset(jlink_data->devh); if (ret != JAYLINK_OK) { msg_perr("jaylink_set_reset() failed: %s.\n", jaylink_strerror(ret)); return false; } - } else { + } else if (jlink_data->cs == CS_TRST) { ret = jaylink_jtag_set_trst(jlink_data->devh); if (ret != JAYLINK_OK) { msg_perr("jaylink_jtag_set_trst() failed: %s.\n", jaylink_strerror(ret)); return false; } + } else { + ret = jaylink_jtag_set_tms(jlink_data->devh); + + if (ret != JAYLINK_OK) { + msg_perr("jaylink_jtag_set_tms() failed: %s.\n", jaylink_strerror(ret)); + return false; + } } return true; @@ -109,6 +129,7 @@ { uint32_t length; uint8_t *buffer; + static const uint8_t tms_buffer[JTAG_MAX_TRANSFER_SIZE] = {0}; struct jlink_spi_data *jlink_data = flash->mst->spi.data; length = writecnt + readcnt; @@ -136,7 +157,7 @@ int ret; ret = jaylink_jtag_io(jlink_data->devh, - buffer, buffer, buffer, length * 8, JAYLINK_JTAG_VERSION_2); + tms_buffer, buffer, buffer, length * 8, JAYLINK_JTAG_VERSION_2); if (ret != JAYLINK_OK) { msg_perr("jaylink_jtag_io() failed: %s.\n", jaylink_strerror(ret)); @@ -196,7 +217,7 @@ unsigned long speed = 0; struct jaylink_context *jaylink_ctx = NULL; struct jaylink_device_handle *jaylink_devh = NULL; - bool reset_cs; + enum cs_wiring cs; struct jlink_spi_data *jlink_data = NULL; bool enable_target_power; @@ -255,14 +276,16 @@ free(arg); - reset_cs = true; + cs = CS_RESET; arg = extract_programmer_param_str(cfg, "cs"); if (arg) { if (!strcasecmp(arg, "reset")) { - reset_cs = true; + cs = CS_RESET; } else if (!strcasecmp(arg, "trst")) { - reset_cs = false; + cs = CS_TRST; + } else if (!strcasecmp(arg, "tms")) { + cs = CS_TMS; } else { msg_perr("Invalid chip select pin specified: '%s'.\n", arg); free(arg); @@ -272,10 +295,12 @@ free(arg); - if (reset_cs) + if (cs == CS_RESET) msg_pdbg("Using RESET as chip select signal.\n"); - else + else if (cs == CS_TRST) msg_pdbg("Using TRST as chip select signal.\n"); + else + msg_pdbg("Using TMS/CS as chip select signal.\n"); enable_target_power = false; arg = extract_programmer_param_str(cfg, "power"); @@ -506,7 +531,7 @@ /* jaylink_ctx, jaylink_devh are allocated by jaylink_init and jaylink_open */ jlink_data->ctx = jaylink_ctx; jlink_data->devh = jaylink_devh; - jlink_data->reset_cs = reset_cs; + jlink_data->cs = cs; jlink_data->enable_target_power = enable_target_power; /* Ensure that the CS signal is not active initially. */ -- To view, visit https://review.coreboot.org/c/flashrom/+/75011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0cb467fcc2c403a25f260462de0cd020e7022bb1 Gerrit-Change-Number: 75011 Gerrit-PatchSet: 1 Gerrit-Owner: Chen <c(a)jia.je> Gerrit-MessageType: newchange

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[S] Change in flashrom[master]: flashrom: rename sb600spi.c to amd_spi.c
by Anastasia Klimchuk (Code Review) 08 May '23

08 May '23

Attention is currently required from: Martin L Roth, Thomas Heijligen, Arthur Heymans. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/74952 ) Change subject: flashrom: rename sb600spi.c to amd_spi.c ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > > The promontary support works well in that patch series linked. […] Thinking a bit more about it, and returning back to the point of the patch. I like amd_spi.c more than amd_sb600_spi.c : it's a shorter name without loss of information. Commit message explains that "sb600" doesn't give any information, so why keep it in the name? So I support renaming to amd_spi.c (what is going on on the other forks is not that relevant for this question) And I am still interested if there are any longer term plans that maybe Martin you have? -- To view, visit https://review.coreboot.org/c/flashrom/+/74952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I13859de27e602cc6496684e6cb66b2dc2e21531a Gerrit-Change-Number: 74952 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 08 May 2023 10:26:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: makefile: remove gitconfig target
by Anastasia Klimchuk (Code Review) 08 May '23

08 May '23

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/74924 ) Change subject: makefile: remove gitconfig target ...................................................................... makefile: remove gitconfig target There's basically no benefit to running `make` over directly running the script that configures hooks, and implementing similar support in Meson is difficult. Remove the Makefile target to achieve feature parity between the build systems. Ticket: https://ticket.coreboot.org/issues/486 Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> Change-Id: I278408bd515c5a5599b5c45c597cc66485a87082 Reviewed-on: https://review.coreboot.org/c/flashrom/+/74924 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M Makefile 1 file changed, 19 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/Makefile b/Makefile index 6004402..e6d4554 100644 --- a/Makefile +++ b/Makefile @@ -1098,9 +1098,6 @@ libpayload: clean make CC="CC=i386-elf-gcc lpgcc" AR=i386-elf-ar RANLIB=i386-elf-ranlib -gitconfig: - git rev-parse 2>/dev/null && ./util/git-hooks/install.sh - .PHONY: all install clean distclean config _export export tarball libpayload # Disable implicit suffixes and built-in rules (for performance and profit) -- To view, visit https://review.coreboot.org/c/flashrom/+/74924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I278408bd515c5a5599b5c45c597cc66485a87082 Gerrit-Change-Number: 74924 Gerrit-PatchSet: 5 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in flashrom[master]: makefile: remove gitconfig target
by Anastasia Klimchuk (Code Review) 08 May '23

08 May '23

Attention is currently required from: Thomas Heijligen, Peter Marheine. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/74924 ) Change subject: makefile: remove gitconfig target ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/74924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I278408bd515c5a5599b5c45c597cc66485a87082 Gerrit-Change-Number: 74924 Gerrit-PatchSet: 4 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Mon, 08 May 2023 02:02:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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