Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/60230 )
Change subject: spi25_statusreg.c: add SR3 read/write support
......................................................................
Patch Set 13:
(1 comment)
Patchset:
PS13:
I created a follow up https://ticket.coreboot.org/issues/377
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59278 )
Change subject: programmer.h: Make pacc global state static local
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/59278/comment/8c01ecd5_ad13ceb0
PS3, Line 17: flow now.
> Yes, I finally got a 15 min to spare to rebase it and send it up https://review.coreboot. […]
I squashed the two together so CB:62951 is now off HEAD so it should be easier to review. We could abandon this one?
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62951 )
Change subject: pcidev: Construct a API to handle phantom pci controllers
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62951/comment/83ccb81b_88938f79
PS2, Line 9: habe
> nit: ha*v*e
Done
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Hello build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62951
to look at the new patch set (#3).
Change subject: pcidev: Construct a API to handle phantom pci controllers
......................................................................
pcidev: Construct a API to handle phantom pci controllers
On Intel the SPI PCI device can have hiden PCI vendor
and device IDs. So we need a PCI access method that works
even when the OS doesn't know the PCI device.
This however does not generalise since it would bring along other
constraints (e.g. on PCI domains, extended PCIe config space).
Fortunately the logic exists inside chipset_enable.c however
the interaction with the rest of the pcidev workers are quite
invasive and hard to reason about. Therefore here we implement
a definable API to manage this special casing by having methods
define on a handle with a known life-time.
BUG=b:220950271
TEST=`sudo ./flashrom -p internal -r /tmp/bios`
on Found chipset "Intel Kaby Lake U w/ iHDCP2.2 Prem.".
Change-Id: Ic75573a14c9997a2d0347cd683ffc0c78d1b3a4f
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M chipset_enable.c
M include/programmer.h
M pcidev.c
3 files changed, 82 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/51/62951/3
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Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62405 )
Change subject: board_enable.c: Port to use pcidev_find_vendorclass() helper
......................................................................
board_enable.c: Port to use pcidev_find_vendorclass() helper
Change-Id: I3d8e3dbd5eeb057d7c959a82678cca2345fc69d9
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62405
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Thomas Heijligen <src(a)posteo.de>
---
M board_enable.c
1 file changed, 10 insertions(+), 16 deletions(-)
Approvals:
build bot (Jenkins): Verified
Thomas Heijligen: Looks good to me, approved
diff --git a/board_enable.c b/board_enable.c
index d740806..7b9e9f6 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -1555,26 +1555,20 @@
int i, allowed;
/* First, look for a known LPC bridge */
- for (dev = pacc->devices; dev; dev = dev->next) {
- uint16_t device_class;
- /* libpci before version 2.2.4 does not store class info. */
- device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
- if ((dev->vendor_id == 0x8086) &&
- (device_class == 0x0601)) { /* ISA bridge */
- /* Is this device in our list? */
- for (i = 0; intel_ich_gpio_table[i].id; i++)
- if (dev->device_id == intel_ich_gpio_table[i].id)
- break;
-
- if (intel_ich_gpio_table[i].id)
- break;
- }
- }
-
+ dev = pcidev_find_vendorclass(0x8086, 0x0601); /* ISA bridge */
if (!dev) {
msg_perr("\nERROR: No known Intel LPC bridge found.\n");
return -1;
}
+ /* Is this device in our list? */
+ for (i = 0; intel_ich_gpio_table[i].id; i++)
+ if (dev->device_id == intel_ich_gpio_table[i].id)
+ break;
+
+ if (!intel_ich_gpio_table[i].id) {
+ msg_perr("\nERROR: No known Intel LPC bridge found.\n");
+ return -1;
+ }
/*
* According to the datasheets, all Intel ICHs have the GPIO bar 5:1
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59291 )
Change subject: flashrom: Drop read_flash_to_file() usage
......................................................................
Patch Set 14:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/59291/comment/a567608a_55c87e72
PS14, Line 9: Aspire towards a goal of making cli_classic more of just
: a user of libflashrom than having quasi-parallel paths in
: flashrom.c
:
: This converts remaining read_flash_to_file() usage to the
: do_read() provider wrapper around libflashrom.
> Nit: Using 72 characters per line would save one line.
Ack. It's readable though so leaving as-is.
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Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Peter Marheine,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/63903
to look at the new patch set (#8).
Change subject: libflashrom: Move documentation to header
......................................................................
libflashrom: Move documentation to header
The doxygen documentation was in the libflashrom.c file. Move the
documentation to the libflashrom.h file. This allows foreign function
interface binding generators (eg rust bindgen) that operate on the .h
file to generate documentation for the target language. Some doxygen
errors were also corrected, mostly undocumented or wrongly labeled
parameters.
To test, I have diffed and inspected the doxygen documentation before
and after the change. All functions are documented the same, and the
structs and enums are now also included in the docs.
Change-Id: I856b74d5bfea13722539be15496755a95e701eea
Signed-off-by: Evan Benn <evanbenn(a)chromium.org>
---
M Doxyfile
M flashrom.c
M include/libflashrom.h
M layout.c
M libflashrom.c
M writeprotect.c
6 files changed, 440 insertions(+), 473 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/03/63903/8
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