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Change subject: ichspi: Introduce FCYCLE_MASK(n) macro
......................................................................
Patch Set 5:
(4 comments)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/62891/comment/64d0162f_e7eff9d0
PS5, Line 141: 2 bits
Can you elaborate more than just saying 2 bits so to help the reader who may not have access to the datasheet?
https://review.coreboot.org/c/flashrom/+/62891/comment/572201ee_9b2dfb24
PS5, Line 143: 1-2: FLASH Cycle
`1-n: FLASH Cycle`
https://review.coreboot.org/c/flashrom/+/62891/comment/38fed04e_6752ca59
PS5, Line 145: #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
isn't this removable now since you would have
`HSFC_FCYCLE_MASK(HSFC_FCYCLE_BIT_WIDTH_ICH9)`
https://review.coreboot.org/c/flashrom/+/62891/comment/52909fa7_67612bb7
PS5, Line 506: _p
unrelated pp change to this patch.
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Change subject: hwaccess: replace macros by C code
......................................................................
Patch Set 6: Code-Review+1
(2 comments)
Patchset:
PS5:
> Does anybody have a preference regarding `ULL` vs. `ull`? […]
The only thing I can think about is: lowercase l looks like uppercase I. But uppercase L does not have this issue :)
File hwaccess.h:
https://review.coreboot.org/c/flashrom/+/62898/comment/166d8ae0_6b2bd2ce
PS6, Line 28: swap
It used to be "swab" and now it is "swap" (one char difference in the name). Is this intentional?
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Change subject: ichspi: Unify timeout (30sec) across all SPI operations
......................................................................
Patch Set 7: Code-Review+1
(5 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62867/comment/f388a77c_82417d3c
PS7, Line 7: Unify timeout (30sec) across all SPI operations
`Unify timeouts across all SPI operations to 30s`
https://review.coreboot.org/c/flashrom/+/62867/comment/4f24dd8a_8c3f8b06
PS7, Line 9: This patch removes taking `timeout` argument for different operations
: using `ich_hwseq_wait_for_cycle_complete()`. Make use of 30sec unified
: timeout for all SPI operations.
```
Here we drop the `timeout` parameter from `ich_hwseq_wait_for_cycle_complete()` in favor of a fixed timeout of 30 seconds for any given SPI operation as recommended by the SPI programming guide:
```
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/62867/comment/5c79e077_acebd202
PS7, Line 31: multi-master accessing the
`multi-mastering access of the`
https://review.coreboot.org/c/flashrom/+/62867/comment/165d3c57_bb6ac915
PS7, Line 31: might
`may`
https://review.coreboot.org/c/flashrom/+/62867/comment/5fe3cdab_8942fb41
PS7, Line 36: it's impossible to know
: * the actual status of the SPI bus
I thought that is the point of the `HSFS_SCIP` bit? The phrasing may need adjustment here to clarify the difference, ideally to mention how these two ingredients interplay with each other.
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Change subject: flashrom.8.tmpl: Clarify man entries for -w/-v/-x
......................................................................
Patch Set 5: Code-Review+2
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62643
to look at the new patch set (#7).
Change subject: writeprotect.c: refactor and fix wp_mode functions
......................................................................
writeprotect.c: refactor and fix wp_mode functions
This is a follow up on commit 12dbc4e04508aecfff53ad95b6f68865da1b4f07.
Use a lookup table in get_wp_mode() and drop the srp_bit_present check,
since a chip without SRP is just FLASHROM_WP_MODE_DISABLED.
Add a srp_bit_present check to set_wp_mode() if the mode requires it.
BUG=b:182223106
BRANCH=none
TEST=flashrom --wp-{enable,disable,status} on AMD dut
Change-Id: Ib6c347453f9216e5816e4ed35bf9783fd3c720e0
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M writeprotect.c
1 file changed, 13 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/43/62643/7
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