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Change subject: ichspi.c: Read chip ID and use it to populate `flash->chip`
......................................................................
Patch Set 16: Code-Review+1
(1 comment)
Patchset:
PS16:
Tested on Lenovo W530 (8+4MB flash chips)
```
$ sudo ./flashrom -p internal --flash-name
flashrom v1.2-1130-g7902b2b5-dirty on Linux 5.19.9-1.el8.elrepo.x86_64 (x86_64)
flashrom is free software, get the source code at https://flashrom.org
Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
coreboot table found at 0x7ff62000.
Found chipset "Intel QM77".
Enabling flash write... SPI Configuration is locked down.
FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write.
FREG1: BIOS region (0x00500000-0x00bfffff) is read-write.
FREG2: Management Engine region (0x00003000-0x004fffff) is read-write.
FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write.
Enabling hardware sequencing due to multiple flash chips detected.
OK.
Multiple flash components detected, skipping flash identification.
Found Programmer flash chip "Opaque flash chip" (12288 kB, Programmer-specific) on internal.
vendor="Programmer" name="Opaque flash chip"
$
```
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Change subject: flashchips: Add WP settings for Flash Chip `W25Q512NW`
......................................................................
Patch Set 8: Code-Review+1
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Change subject: flashchips: Add WP settings for Flash Chip `W25Q512NW`
......................................................................
Patch Set 8: Code-Review+2
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Change subject: flashchips.c: Indent definition of W25Q512NW-IM properly
......................................................................
Patch Set 5: Code-Review+2
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Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/70126 )
Change subject: programmer: Add get_region to spi/opaque masters
......................................................................
programmer: Add get_region to spi/opaque masters
Add a get_region function to spi and opaque masters so that they can
expose access permissions for multiple regions within the flash.
A get_region() implementation is added for the ichspi driver in a
following patch.
Finally, another patch uses get_region() to make read_flash() and
write_flash() skip inaccessable regions, making read, write, and erase
operations work on Intel platforms with active an CSME coprocessor.
This logic will be integrated with layout in the future, but for now
this moves ichspi support forward without making refactoring too hard
later on.
BUG=b:260440773
BRANCH=none
TEST=ninja test
Change-Id: I8c43f6b705f36ef18842a04ba6241d3a0b36b232
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/70126
Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M include/programmer.h
1 file changed, 33 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Edward O'Callaghan: Looks good to me, approved
diff --git a/include/programmer.h b/include/programmer.h
index aaa1407..67e7b4a 100644
--- a/include/programmer.h
+++ b/include/programmer.h
@@ -313,6 +313,7 @@
int (*shutdown)(void *data);
bool (*probe_opcode)(const struct flashctx *flash, uint8_t opcode);
void (*delay) (const struct flashctx *flash, unsigned int usecs);
+ void (*get_region)(const struct flashctx *flash, unsigned int addr, struct flash_region *region);
void *data;
};
@@ -416,6 +417,7 @@
enum flashrom_wp_result (*wp_write_cfg)(struct flashctx *, const struct flashrom_wp_cfg *);
enum flashrom_wp_result (*wp_read_cfg)(struct flashrom_wp_cfg *, struct flashctx *);
enum flashrom_wp_result (*wp_get_ranges)(struct flashrom_wp_ranges **, struct flashctx *);
+ void (*get_region)(const struct flashctx *flash, unsigned int addr, struct flash_region *region);
int (*shutdown)(void *data);
void *data;
};
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