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Hello build bot (Jenkins), Simon Buhrow, Thomas Heijligen,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/65879
to look at the new patch set (#46).
Change subject: flashrom.c:Add function to get a flattened view of the chip erase blocks
......................................................................
flashrom.c:Add function to get a flattened view of the chip erase blocks
Add a function to flatten out the addresses of the flash chip as per the
different erase functions. This function will return a list of layouts
which is dynamically allocated. So after use all the layouts as well as
the list itself should be freed. The free_erase_layout function does
that.
Change-Id: Iafe78de00daa55f7114bd4ce09465dd88074ece4
Signed-off-by: Aarya Chaumal <aarya.chaumal(a)gmail.com>
---
M flashrom.c
M include/flash.h
2 files changed, 109 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/65879/46
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70516 )
Change subject: flashrom: Check for flash access restricitons in write_flash()
......................................................................
Patch Set 5:
(2 comments)
File flashrom.c:
https://review.coreboot.org/c/flashrom/+/70516/comment/b85c1ce4_1e2ea5ca
PS5, Line 367: }
```
}
free(region.name);
```
https://review.coreboot.org/c/flashrom/+/70516/comment/2ffa92db_08c08a1a
PS5, Line 371:
spurious
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70866 )
Change subject: flashchips.c: Mark W25Q128.V WP as tested
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/70866/comment/aefcddac_14917196
PS1, Line 9: b:?
> What does it mean? :)
Done
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Hello build bot (Jenkins), Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/70866
to look at the new patch set (#3).
Change subject: flashchips.c: Mark W25Q128.V WP as tested
......................................................................
flashchips.c: Mark W25Q128.V WP as tested
BUG=b:258755442
TEST=`-p internal --wp-status`.
Change-Id: Ifbd5ee76f2087764ab8841ca96de6990cb31260d
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M flashchips.c
1 file changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/66/70866/3
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Hello build bot (Jenkins), Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/70866
to look at the new patch set (#2).
Change subject: flashchips.c: Mark W25Q128.V WP as tested
......................................................................
flashchips.c: Mark W25Q128.V WP as tested
BUG=b:?
TEST=`-p internal --wp-status`.
Change-Id: Ifbd5ee76f2087764ab8841ca96de6990cb31260d
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M flashchips.c
1 file changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/66/70866/2
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Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70388 )
Change subject: chipset_enable.c: add PCI ID for TGL-UP3
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/70388/comment/b5d147f5_8936c8ef
PS2, Line 7: SPI controller
> Drop, since it's not for the SPI controller?
Fair point.
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Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/70388
to look at the new patch set (#3).
Change subject: chipset_enable.c: add PCI ID for TGL-UP3
......................................................................
chipset_enable.c: add PCI ID for TGL-UP3
Add PCI ID for the Tiger Lake UP3 (Industrial SKU) SoC.
Change-Id: Ie93af14eb5857bfe51964f6565e475b6249dd407
Signed-off-by: Jan Samek <jan.samek(a)siemens.com>
---
M chipset_enable.c
1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/70388/3
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