December 2022 - flashrom-gerrit

[S] Change in flashrom[master]: flashchips.c: Add reg_bits for W25Q512NW-IM
by Subrata Banik (Code Review) 14 Dec '22

14 Dec '22

Attention is currently required from: Kapil Porwal, Edward O'Callaghan, Nikolai Artemiev. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70548 ) Change subject: flashchips.c: Add reg_bits for W25Q512NW-IM ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: i have landed this https://review.coreboot.org/c/flashrom/+/67827/7/flashchips.c -- To view, visit https://review.coreboot.org/c/flashrom/+/70548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I97c24682bb0c8ea67ef5617567cd99f6526ba2da Gerrit-Change-Number: 70548 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 14 Dec 2022 12:50:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashchips.c: Add reg_bits for W25Q512NW-IM
by Kapil Porwal (Code Review) 14 Dec '22

14 Dec '22

Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70548 ) Change subject: flashchips.c: Add reg_bits for W25Q512NW-IM ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/flashrom/+/70548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I97c24682bb0c8ea67ef5617567cd99f6526ba2da Gerrit-Change-Number: 70548 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Dec 2022 12:47:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in flashrom[master]: spi.c: Add AT45 & SF25F erasefn opcode mapping
by Thomas Heijligen (Code Review) 14 Dec '22

14 Dec '22

Thomas Heijligen has submitted this change. ( https://review.coreboot.org/c/flashrom/+/67717 ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: spi.c: Add AT45 & SF25F erasefn opcode mapping ...................................................................... spi.c: Add AT45 & SF25F erasefn opcode mapping Change-Id: I798a91f1e20b63662715c68e6d43d03fc6005d51 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67717 Reviewed-by: Thomas Heijligen <src(a)posteo.de> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M include/chipdrivers.h M spi.c 2 files changed, 61 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Thomas Heijligen: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved diff --git a/include/chipdrivers.h b/include/chipdrivers.h index d2e13b4..71b8795 100644 --- a/include/chipdrivers.h +++ b/include/chipdrivers.h @@ -53,7 +53,7 @@ int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_dc(struct flashctx *flash, unsigned int addr, unsigned int blocklen); enum block_erase_func spi25_get_erasefn_from_opcode(uint8_t opcode); -uint8_t spi_get_opcode_from_erasefn(enum block_erase_func func); +const uint8_t *spi_get_opcode_from_erasefn(enum block_erase_func func); int spi_chip_write_1(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int spi_nbyte_read(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); diff --git a/spi.c b/spi.c index 8983e81..e708ba9 100644 --- a/spi.c +++ b/spi.c @@ -168,28 +168,56 @@ return register_master(&rmst); } +/* + * The following array has erasefn and opcode list pair. The opcode list pair is + * 0 termintated and must have size one more than the maximum number of opcodes + * used by any erasefn. Also the opcodes must be in increasing order. + */ static const struct { enum block_erase_func func; - uint8_t opcode; + uint8_t opcode[3]; } function_opcode_list[] = { - {SPI_BLOCK_ERASE_20, 0x20}, - {SPI_BLOCK_ERASE_21, 0x21}, - {SPI_BLOCK_ERASE_50, 0x50}, - {SPI_BLOCK_ERASE_52, 0x52}, - {SPI_BLOCK_ERASE_53, 0x53}, - {SPI_BLOCK_ERASE_5C, 0x5c}, - {SPI_BLOCK_ERASE_60, 0x60}, - {SPI_BLOCK_ERASE_62, 0x62}, - {SPI_BLOCK_ERASE_81, 0x81}, - {SPI_BLOCK_ERASE_C4, 0xc4}, - {SPI_BLOCK_ERASE_C7, 0xc7}, - {SPI_BLOCK_ERASE_D7, 0xd7}, - {SPI_BLOCK_ERASE_D8, 0xd8}, - {SPI_BLOCK_ERASE_DB, 0xdb}, - {SPI_BLOCK_ERASE_DC, 0xdc}, + {SPI_BLOCK_ERASE_20, {0x20}}, + {SPI_BLOCK_ERASE_21, {0x21}}, + {SPI_BLOCK_ERASE_50, {0x50}}, + {SPI_BLOCK_ERASE_52, {0x52}}, + {SPI_BLOCK_ERASE_53, {0x53}}, + {SPI_BLOCK_ERASE_5C, {0x5c}}, + {SPI_BLOCK_ERASE_60, {0x60}}, + {SPI_BLOCK_ERASE_62, {0x62}}, + {SPI_BLOCK_ERASE_81, {0x81}}, + {SPI_BLOCK_ERASE_C4, {0xc4}}, + {SPI_BLOCK_ERASE_C7, {0xc7}}, + {SPI_BLOCK_ERASE_D7, {0xd7}}, + {SPI_BLOCK_ERASE_D8, {0xd8}}, + {SPI_BLOCK_ERASE_DB, {0xdb}}, + {SPI_BLOCK_ERASE_DC, {0xdc}}, + //AT45CS1282 + {SPI_ERASE_AT45CS_SECTOR, {0x50, 0x7c, 0}}, + //AT45DB** + {SPI_ERASE_AT45DB_PAGE, {0x81}}, + {SPI_ERASE_AT45DB_BLOCK, {0x50}}, + {SPI_ERASE_AT45DB_SECTOR, {0x7c}}, + {SPI_ERASE_AT45DB_CHIP, {0xc7}}, + //SF25F** + {S25FL_BLOCK_ERASE, {0xdc}}, + {S25FS_BLOCK_ERASE_D8, {0xd8}}, }; -uint8_t spi_get_opcode_from_erasefn(enum block_erase_func func) +/* + * @brief Get erase function pointer from passed opcode list. + * + * Get the pointer to the erase function which uses passed opcodes and is used + * by the passed flashcip. The passed opcode_list must have opcodes in + * increasing order. + * + * @param chip Pointer to the flashchip structure. + * @param opcode_list Pointer to the array of opcodes. + * @param opcode_count Number of opcodes in 'opcode_list' + * + * @result Pointer to erase function matching 'chip' and 'opcode_list' or NULL on failure + */ +const uint8_t *spi_get_opcode_from_erasefn(enum block_erase_func func) { size_t i; for (i = 0; i < ARRAY_SIZE(function_opcode_list); i++) { @@ -198,6 +226,6 @@ } msg_cinfo("%s: unknown erase function (0x%d). Please report " "this at flashrom(a)flashrom.org\n", __func__, func); - return 0x00; //Assuming 0x00 is not a erase function opcode + return NULL; } -- To view, visit https://review.coreboot.org/c/flashrom/+/67717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I798a91f1e20b63662715c68e6d43d03fc6005d51 Gerrit-Change-Number: 67717 Gerrit-PatchSet: 12 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aarya <aarya.chaumal(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in flashrom[master]: spi25.c: Rename spi_get_erasefn_from_opcode to spi25_get_erasefn_from...
by Thomas Heijligen (Code Review) 14 Dec '22

14 Dec '22

Thomas Heijligen has submitted this change. ( https://review.coreboot.org/c/flashrom/+/67716 ) ( 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: spi25.c: Rename spi_get_erasefn_from_opcode to spi25_get_erasefn_from_opcode ...................................................................... spi25.c: Rename spi_get_erasefn_from_opcode to spi25_get_erasefn_from_opcode This function works only with spi25 chips Change-Id: Ie054160b0fdd34bcb128285c6a047e3a3fa8be0c Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67716 Reviewed-by: Thomas Heijligen <src(a)posteo.de> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M include/chipdrivers.h M sfdp.c M spi25.c 3 files changed, 23 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Thomas Heijligen: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved diff --git a/include/chipdrivers.h b/include/chipdrivers.h index 34e3af8..d2e13b4 100644 --- a/include/chipdrivers.h +++ b/include/chipdrivers.h @@ -52,7 +52,7 @@ int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_dc(struct flashctx *flash, unsigned int addr, unsigned int blocklen); -enum block_erase_func spi_get_erasefn_from_opcode(uint8_t opcode); +enum block_erase_func spi25_get_erasefn_from_opcode(uint8_t opcode); uint8_t spi_get_opcode_from_erasefn(enum block_erase_func func); int spi_chip_write_1(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int spi_nbyte_read(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); diff --git a/sfdp.c b/sfdp.c index ccf840f..5eddb21 100644 --- a/sfdp.c +++ b/sfdp.c @@ -81,7 +81,7 @@ { int i; uint32_t total_size = chip->total_size * 1024; - enum block_erase_func erasefn = spi_get_erasefn_from_opcode(opcode); + enum block_erase_func erasefn = spi25_get_erasefn_from_opcode(opcode); if (erasefn == NO_BLOCK_ERASE_FUNC || total_size == 0 || block_size == 0 || total_size % block_size != 0) { diff --git a/spi25.c b/spi25.c index cae6200..f54e4c8 100644 --- a/spi25.c +++ b/spi25.c @@ -621,7 +621,7 @@ static const struct { enum block_erase_func func; uint8_t opcode; -} function_opcode_list[] = { +} spi25_function_opcode_list[] = { {SPI_BLOCK_ERASE_20, 0x20}, {SPI_BLOCK_ERASE_21, 0x21}, {SPI_BLOCK_ERASE_50, 0x50}, @@ -639,12 +639,12 @@ {SPI_BLOCK_ERASE_DC, 0xdc}, }; -enum block_erase_func spi_get_erasefn_from_opcode(uint8_t opcode) +enum block_erase_func spi25_get_erasefn_from_opcode(uint8_t opcode) { size_t i; - for (i = 0; i < ARRAY_SIZE(function_opcode_list); i++) { - if (function_opcode_list[i].opcode == opcode) - return function_opcode_list[i].func; + for (i = 0; i < ARRAY_SIZE(spi25_function_opcode_list); i++) { + if (spi25_function_opcode_list[i].opcode == opcode) + return spi25_function_opcode_list[i].func; } msg_cinfo("%s: unknown erase opcode (0x%02x). Please report " "this at flashrom(a)flashrom.org\n", __func__, opcode); -- To view, visit https://review.coreboot.org/c/flashrom/+/67716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie054160b0fdd34bcb128285c6a047e3a3fa8be0c Gerrit-Change-Number: 67716 Gerrit-PatchSet: 11 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in flashrom[master]: spi25.c: Move spi_get_opcode_from_erasefn() to spi.c
by Thomas Heijligen (Code Review) 14 Dec '22

14 Dec '22

Thomas Heijligen has submitted this change. ( https://review.coreboot.org/c/flashrom/+/67715 ) ( 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: spi25.c: Move spi_get_opcode_from_erasefn() to spi.c ...................................................................... spi25.c: Move spi_get_opcode_from_erasefn() to spi.c Split spi_get_opcode_from_erasefn() out into spi.c to add support for non spi25 flashes next. Change-Id: Id654e998d0af2d3f5845336bb98b38d724519038 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67715 Reviewed-by: Thomas Heijligen <src(a)posteo.de> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M spi.c M spi25.c 2 files changed, 51 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Thomas Heijligen: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved diff --git a/spi.c b/spi.c index eeb1362..8983e81 100644 --- a/spi.c +++ b/spi.c @@ -167,3 +167,37 @@ rmst.spi.data = data; return register_master(&rmst); } + +static const struct { + enum block_erase_func func; + uint8_t opcode; +} function_opcode_list[] = { + {SPI_BLOCK_ERASE_20, 0x20}, + {SPI_BLOCK_ERASE_21, 0x21}, + {SPI_BLOCK_ERASE_50, 0x50}, + {SPI_BLOCK_ERASE_52, 0x52}, + {SPI_BLOCK_ERASE_53, 0x53}, + {SPI_BLOCK_ERASE_5C, 0x5c}, + {SPI_BLOCK_ERASE_60, 0x60}, + {SPI_BLOCK_ERASE_62, 0x62}, + {SPI_BLOCK_ERASE_81, 0x81}, + {SPI_BLOCK_ERASE_C4, 0xc4}, + {SPI_BLOCK_ERASE_C7, 0xc7}, + {SPI_BLOCK_ERASE_D7, 0xd7}, + {SPI_BLOCK_ERASE_D8, 0xd8}, + {SPI_BLOCK_ERASE_DB, 0xdb}, + {SPI_BLOCK_ERASE_DC, 0xdc}, +}; + +uint8_t spi_get_opcode_from_erasefn(enum block_erase_func func) +{ + size_t i; + for (i = 0; i < ARRAY_SIZE(function_opcode_list); i++) { + if (function_opcode_list[i].func == func) + return function_opcode_list[i].opcode; + } + msg_cinfo("%s: unknown erase function (0x%d). Please report " + "this at flashrom(a)flashrom.org\n", __func__, func); + return 0x00; //Assuming 0x00 is not a erase function opcode +} + diff --git a/spi25.c b/spi25.c index da870be..cae6200 100644 --- a/spi25.c +++ b/spi25.c @@ -651,18 +651,6 @@ return NO_BLOCK_ERASE_FUNC; } -uint8_t spi_get_opcode_from_erasefn(enum block_erase_func func) -{ - size_t i; - for (i = 0; i < ARRAY_SIZE(function_opcode_list); i++) { - if (function_opcode_list[i].func == func) - return function_opcode_list[i].opcode; - } - msg_cinfo("%s: unknown erase function (0x%d). Please report " - "this at flashrom(a)flashrom.org\n", __func__, func); - return 0x00; //Assuming 0x00 is not a erase function opcode -} - static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) { const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_WRITE && spi_master_4ba(flash); -- To view, visit https://review.coreboot.org/c/flashrom/+/67715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id654e998d0af2d3f5845336bb98b38d724519038 Gerrit-Change-Number: 67715 Gerrit-PatchSet: 10 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aarya <aarya.chaumal(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in flashrom[master]: flashchips: Add WP settings for Flash Chip `W25Q512NW`
by Subrata Banik (Code Review) 14 Dec '22

14 Dec '22

Attention is currently required from: Subrata Banik, Edward O'Callaghan, Nikolai Artemiev. Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Nikolai Artemiev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/67827 to look at the new patch set (#7). Change subject: flashchips: Add WP settings for Flash Chip `W25Q512NW` ...................................................................... flashchips: Add WP settings for Flash Chip `W25Q512NW` This patch adds WP register bits and decode range for Flash Chip `W25Q512NW`. TEST=Able to flash AP FW, wp-enable/disable on Google/rex device which has flash chip `W25Q512NW`. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ic5148f71404466dcf7772e3eb6e1800eb8666696 --- M flashchips.c 1 file changed, 29 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/27/67827/7 -- To view, visit https://review.coreboot.org/c/flashrom/+/67827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic5148f71404466dcf7772e3eb6e1800eb8666696 Gerrit-Change-Number: 67827 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in flashrom[master]: flashchips: Add WP settings for Flash Chip `W25Q512NW`
by Subrata Banik (Code Review) 14 Dec '22

14 Dec '22

Attention is currently required from: Edward O'Callaghan, Nikolai Artemiev. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67827 ) Change subject: flashchips: Add WP settings for Flash Chip `W25Q512NW` ...................................................................... Patch Set 5: (2 comments) Patchset: PS5: > swap the reformatting patch to be before this one. Ack File flashchips.c: https://review.coreboot.org/c/flashrom/+/67827/comment/3ceb9e91_07f2373f PS5, Line 18679: TEST_OK_PREW > I think you need `TEST_OK_PREWB` these days. Ack -- To view, visit https://review.coreboot.org/c/flashrom/+/67827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic5148f71404466dcf7772e3eb6e1800eb8666696 Gerrit-Change-Number: 67827 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 14 Dec 2022 07:01:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashchips: Add WP settings for Flash Chip `W25Q512NW`
by Subrata Banik (Code Review) 14 Dec '22

14 Dec '22

Attention is currently required from: Subrata Banik, Nikolai Artemiev. Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Nikolai Artemiev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/67827 to look at the new patch set (#6). Change subject: flashchips: Add WP settings for Flash Chip `W25Q512NW` ...................................................................... flashchips: Add WP settings for Flash Chip `W25Q512NW` This patch adds WP register bits and decode range for Flash Chip `W25Q512NW`. TEST=Able to flash AP FW, wp-enable/disable on Google/rex device which has flash chip `W25Q512NW`. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ic5148f71404466dcf7772e3eb6e1800eb8666696 --- M flashchips.c 1 file changed, 29 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/27/67827/6 -- To view, visit https://review.coreboot.org/c/flashrom/+/67827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic5148f71404466dcf7772e3eb6e1800eb8666696 Gerrit-Change-Number: 67827 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[master]: flashchips.c: Indent definition of W25Q512NW-IM properly
by Subrata Banik (Code Review) 14 Dec '22

14 Dec '22

Attention is currently required from: Felix Singer. Subrata Banik has uploaded a new patch set (#3) to the change originally created by Felix Singer. ( https://review.coreboot.org/c/flashrom/+/68151 ) Change subject: flashchips.c: Indent definition of W25Q512NW-IM properly ...................................................................... flashchips.c: Indent definition of W25Q512NW-IM properly Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: Icfd2a49383da0f8f0a4e3295aba81ce1d200652c --- M flashchips.c 1 file changed, 49 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/51/68151/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/68151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Icfd2a49383da0f8f0a4e3295aba81ce1d200652c Gerrit-Change-Number: 68151 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newpatchset

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[S] Change in flashrom[master]: flashchips: Add WP settings for Flash Chip `W25Q512NW`
by Angel Pons (Code Review) 14 Dec '22

14 Dec '22

Attention is currently required from: Subrata Banik, Nikolai Artemiev. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67827 ) Change subject: flashchips: Add WP settings for Flash Chip `W25Q512NW` ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/flashrom/+/67827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic5148f71404466dcf7772e3eb6e1800eb8666696 Gerrit-Change-Number: 67827 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 14 Dec 2022 01:45:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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flashrom-gerrit December 2022