Sean Anderson has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43608 )
Change subject: buspirate: Add option for setting the aux pin
......................................................................
buspirate: Add option for setting the aux pin
This adds a parameter to drive the aux pin low (or high if you
explicitly want the previous behavior). Some boards need to have a reset
pin driven low before the firmware can be safely flashed. With the Bus
Pirate, this is most easily done with the auxiliary pin.
Change-Id: Ieeecfdf1afc06dadda9b8f99547cd74854ca6775
Signed-off-by: Sean Anderson <seanga2(a)gmail.com>
---
M buspirate_spi.c
M flashrom.8.tmpl
2 files changed, 33 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/43608/1
diff --git a/buspirate_spi.c b/buspirate_spi.c
index fdfc0e4..1ccb107 100644
--- a/buspirate_spi.c
+++ b/buspirate_spi.c
@@ -228,6 +228,7 @@
int serialspeed_index = -1;
int ret = 0;
int pullup = 0;
+ int aux = 1;
dev = extract_programmer_param("dev");
if (dev && !strlen(dev)) {
@@ -277,6 +278,17 @@
}
free(tmp);
+ tmp = extract_programmer_param("aux");
+ if (tmp) {
+ if (strcasecmp("high", tmp) == 0)
+ ; /* Default */
+ else if (strcasecmp("low", tmp) == 0)
+ aux = 0;
+ else
+ msg_perr("Invalid AUX state, driving high by default.\n");
+ }
+ free(tmp);
+
/* Default buffer size is 19: 16 bytes data, 3 bytes control. */
#define DEFAULT_BUFSIZE (16 + 3)
bp_commbuf = malloc(DEFAULT_BUFSIZE);
@@ -520,11 +532,18 @@
}
/* Initial setup (SPI peripherals config): Enable power, CS high, AUX */
- bp_commbuf[0] = 0x40 | 0x0b;
+ bp_commbuf[0] = 0x40 | 0x09;
if (pullup == 1) {
bp_commbuf[0] |= (1 << 2);
msg_pdbg("Enabling pull-up resistors.\n");
}
+ if (aux) {
+ bp_commbuf[0] |= (1 << 1);
+ msg_pdbg("Driving AUX high.\n");
+ } else {
+ msg_pdbg("Driving AUX low.\n");
+ }
+
ret = buspirate_sendrecv(bp_commbuf, 1, 1);
if (ret)
return 1;
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index db50d59..caf860c 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -902,6 +902,19 @@
.URLB "http://dangerousprototypes.com/docs/Practical_guide_to_Bus_Pirate_pull-up_r…" \
"in a guide by dangerousprototypes" .
Only the external supply voltage (Vpu) is supported as of this writing.
+.sp
+An optional aux parameter specifies the state of the Bus Pirate auxiliary pin.
+This may be used to drive the auxiliary pin high or low before a transfer.
+Syntax is
+.sp
+.B " flashrom -p buspirate_spi:aux=state"
+.sp
+where
+.B state
+can be
+.BR high " or " low .
+The default
+.BR state " is " high .
.SS
.BR "pickit2_spi " programmer
.IP
--
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Gerrit-Change-Id: Ieeecfdf1afc06dadda9b8f99547cd74854ca6775
Gerrit-Change-Number: 43608
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/71565
to look at the new patch set (#2).
Change subject: sb600spi.c: Move promontory code into a mmap_read=yes mode
......................................................................
sb600spi.c: Move promontory code into a mmap_read=yes mode
The only reason promontory code is handled differently is because memory
mapped reads can be faster than manual SPI sequencing. This is not
hardware specific so move it to an option 'mmap_read=yes'.
Tested on an amd picasso and genoa board.
Change-Id: I13eb5a646d3569170b3911ae7b3127cd3e6022aa
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M flashrom.8.tmpl
M sb600spi.c
2 files changed, 71 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/65/71565/2
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/71119 )
Change subject: flashrom.c: Add switch for legacy impl of erasure path
......................................................................
Patch Set 7: Code-Review+1
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/65844 )
Change subject: flashrom.c:Add a function to get list of sectors that need erasing
......................................................................
Patch Set 74: Code-Review+2
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Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/71269 )
Change subject: flashrom.c: Guard against sending spi commands on non-spi mst
......................................................................
flashrom.c: Guard against sending spi commands on non-spi mst
Validate (flash->chip->bustype == BUS_SPI) as ich copies the
chip flags in the opaque master and tries incorrectly
to issue 4BA commands which results in failure.
The issue was detected only in the case of chips >16MB, in
this case 'W25Q256FV' that has the feature bits:
```
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN |
FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ |
FEATURE_WRSR2,
```
The regression was noticed from,
commit 0741727925b841c2479b993204ce58c5eb75185a ichspi.c: Read chip ID and use it to populate `flash->chip`
TEST=In the case of 'W25Q256FV' on TigerLake.
Change-Id: I7cce4f9c032d33c01bf616e27a50b9727a40fe1b
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M flashrom.c
1 file changed, 28 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/69/71269/1
diff --git a/flashrom.c b/flashrom.c
index 62f38f8..f6862c4 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -1944,7 +1944,8 @@
}
/* Enable/disable 4-byte addressing mode if flash chip supports it */
- if (flash->chip->feature_bits & (FEATURE_4BA_ENTER | FEATURE_4BA_ENTER_WREN | FEATURE_4BA_ENTER_EAR7)) {
+ if ((flash->chip->bustype == BUS_SPI) &&
+ (flash->chip->feature_bits & (FEATURE_4BA_ENTER | FEATURE_4BA_ENTER_WREN | FEATURE_4BA_ENTER_EAR7))) {
int ret;
if (spi_master_4ba(flash))
ret = spi_enter_4ba(flash);
--
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Hello Felix Singer, build bot (Jenkins), Angel Pons, Nikolai Artemiev,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/70895
to look at the new patch set (#7).
Change subject: cli_classic.c: Allow ctrl of behaviour with WO and RO regions
......................................................................
cli_classic.c: Allow ctrl of behaviour with WO and RO regions
Add two force flags to the flashrom CLI frontend,
--force-skip-nonreadable - skip reading non-readbale regions without failure,
--force-skip-nonwritable - skip writing non-writable regions without failure.
Each flag allows the user to finely control the behaviour of
flashrom read and write operations when flashrom encounters a
known permission problem. This can be useful in cases such as
wanting to write a pre-padded BIOS image across flash where locked
regions just wish to be left untouched without the need to craft a
custom layout file for each case. Alternatively, to read a copy of
flash complete with padding for regions that are known not to be
readable at runtime however the user does not know the layout of
flash or just wishes to have a padded binary read back.
Change-Id: Iff753b748765410ea38b845613c361db7ad16a61
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M cli_classic.c
M flashrom.8.tmpl
2 files changed, 57 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/70895/7
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70895 )
Change subject: cli_classic.c: Allow ctrl of behaviour with WO and RO regions
......................................................................
Patch Set 5:
(2 comments)
Patchset:
PS5:
> Using these options is dangerous, as flashrom's behaviour on successful invocations becomes non-dete […]
Done. It isn't "non-deterministic" that is the wrong term, it is "runtime deterministic". However I understand your concern and have made not in the man page for the --force-skip-nonwritable flag.
File flashrom.8.tmpl:
https://review.coreboot.org/c/flashrom/+/70895/comment/c1084c06_0aedc67a
PS5, Line 175: compelete
> typo: complete
Done
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