December 2022 - flashrom-gerrit

Change in flashrom[master]: flaschips.c: Fix building with CONFIG_DUMMY=no
by Arthur Heymans (Code Review) April 21, 2023

April 21, 2023

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47166 ) Change subject: flaschips.c: Fix building with CONFIG_DUMMY=no ...................................................................... flaschips.c: Fix building with CONFIG_DUMMY=no With CONFIG_DUMMY=yes dummuflasher.c is not linked in so there is definition of probe_variable_size. Change-Id: Ib9bae93fadc55cf133e837e63419da104a6298be Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M flashchips.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/66/47166/1 diff --git a/flashchips.c b/flashchips.c index 48efb85..1681f42 100644 --- a/flashchips.c +++ b/flashchips.c @@ -19081,3 +19081,7 @@ }; const unsigned int flashchips_size = ARRAY_SIZE(flashchips); + +#if !CONFIG_DUMMY +int probe_variable_size(struct flashctx *flash) { return 0; }; +#endif -- To view, visit https://review.coreboot.org/c/flashrom/+/47166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib9bae93fadc55cf133e837e63419da104a6298be Gerrit-Change-Number: 47166 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in flashrom[master]: buspirate: Add option for setting the aux pin
by Sean Anderson (Code Review) April 13, 2023

April 13, 2023

Sean Anderson has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43608 ) Change subject: buspirate: Add option for setting the aux pin ...................................................................... buspirate: Add option for setting the aux pin This adds a parameter to drive the aux pin low (or high if you explicitly want the previous behavior). Some boards need to have a reset pin driven low before the firmware can be safely flashed. With the Bus Pirate, this is most easily done with the auxiliary pin. Change-Id: Ieeecfdf1afc06dadda9b8f99547cd74854ca6775 Signed-off-by: Sean Anderson <seanga2(a)gmail.com> --- M buspirate_spi.c M flashrom.8.tmpl 2 files changed, 33 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/43608/1 diff --git a/buspirate_spi.c b/buspirate_spi.c index fdfc0e4..1ccb107 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -228,6 +228,7 @@ int serialspeed_index = -1; int ret = 0; int pullup = 0; + int aux = 1; dev = extract_programmer_param("dev"); if (dev && !strlen(dev)) { @@ -277,6 +278,17 @@ } free(tmp); + tmp = extract_programmer_param("aux"); + if (tmp) { + if (strcasecmp("high", tmp) == 0) + ; /* Default */ + else if (strcasecmp("low", tmp) == 0) + aux = 0; + else + msg_perr("Invalid AUX state, driving high by default.\n"); + } + free(tmp); + /* Default buffer size is 19: 16 bytes data, 3 bytes control. */ #define DEFAULT_BUFSIZE (16 + 3) bp_commbuf = malloc(DEFAULT_BUFSIZE); @@ -520,11 +532,18 @@ } /* Initial setup (SPI peripherals config): Enable power, CS high, AUX */ - bp_commbuf[0] = 0x40 | 0x0b; + bp_commbuf[0] = 0x40 | 0x09; if (pullup == 1) { bp_commbuf[0] |= (1 << 2); msg_pdbg("Enabling pull-up resistors.\n"); } + if (aux) { + bp_commbuf[0] |= (1 << 1); + msg_pdbg("Driving AUX high.\n"); + } else { + msg_pdbg("Driving AUX low.\n"); + } + ret = buspirate_sendrecv(bp_commbuf, 1, 1); if (ret) return 1; diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index db50d59..caf860c 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -902,6 +902,19 @@ .URLB "http://dangerousprototypes.com/docs/Practical_guide_to_Bus_Pirate_pull-up_r…" \ "in a guide by dangerousprototypes" . Only the external supply voltage (Vpu) is supported as of this writing. +.sp +An optional aux parameter specifies the state of the Bus Pirate auxiliary pin. +This may be used to drive the auxiliary pin high or low before a transfer. +Syntax is +.sp +.B " flashrom -p buspirate_spi:aux=state" +.sp +where +.B state +can be +.BR high " or " low . +The default +.BR state " is " high . .SS .BR "pickit2_spi " programmer .IP -- To view, visit https://review.coreboot.org/c/flashrom/+/43608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ieeecfdf1afc06dadda9b8f99547cd74854ca6775 Gerrit-Change-Number: 43608 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Anderson <seanga2(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in flashrom[master]: sb600spi.c: Move promontory code into a mmap_read=yes mode
by Arthur Heymans (Code Review) Dec. 28, 2022

Dec. 28, 2022

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/71565 to look at the new patch set (#2). Change subject: sb600spi.c: Move promontory code into a mmap_read=yes mode ...................................................................... sb600spi.c: Move promontory code into a mmap_read=yes mode The only reason promontory code is handled differently is because memory mapped reads can be faster than manual SPI sequencing. This is not hardware specific so move it to an option 'mmap_read=yes'. Tested on an amd picasso and genoa board. Change-Id: I13eb5a646d3569170b3911ae7b3127cd3e6022aa Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M flashrom.8.tmpl M sb600spi.c 2 files changed, 71 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/65/71565/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/71565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I13eb5a646d3569170b3911ae7b3127cd3e6022aa Gerrit-Change-Number: 71565 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[master]: sb600spi.c: Move promontory code into a mmap_read=yes mode
by Arthur Heymans (Code Review) Dec. 28, 2022

Dec. 28, 2022

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/71565 ) Change subject: sb600spi.c: Move promontory code into a mmap_read=yes mode ...................................................................... sb600spi.c: Move promontory code into a mmap_read=yes mode The only reason promontory code is handled differently is because memory mapped reads can be faster than manual SPI sequencing. This is not hardware specific so move it to an option 'mmap_read=yes'. Change-Id: I13eb5a646d3569170b3911ae7b3127cd3e6022aa Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M flashrom.8.tmpl M sb600spi.c 2 files changed, 69 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/65/71565/1 diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 0eabee5..6e2b4eb 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -599,6 +599,15 @@ -The default is to use the frequency that is currently configured. .sp An optional +.B mmap_read +parameter allows to do memory mapped reads instead of through manual SPI sequencing. +This allows the programmer to use faster modes which can be set with the +.B spireadmode +parameter. This mode is however limited to 16MiB flashchips or smaller as more does not get mapped. +.sp +.B " flashrom \-p internal:mmap_read=yes +.sp +An optional .B spireadmode parameter specifies the read mode of the SPI bus where applicable (Bolton or later). Syntax is diff --git a/sb600spi.c b/sb600spi.c index 5b9ac45..3e1339c 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -572,9 +572,14 @@ return amd_imc_shutdown(dev); } -static int promontory_read_memmapped(struct flashctx *flash, uint8_t *buf, +static int amd_read_memmapped(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { + if (flash->chip->total_size > (16 * MiB) / KiB) { + msg_perr("No more than 16 MiB can be memory mapped.\n" + "Try again without mmap_read=yes"); + return -1; + } struct sb600spi_data * data = (struct sb600spi_data *)flash->mst->spi.data; if (!data->flash) { map_flash(flash); @@ -584,6 +589,34 @@ return 0; } +static int handle_mmap_read(const struct programmer_cfg *cfg, + struct spi_master *master) +{ + bool mmap_read = false; + char *param_value = extract_programmer_param_str(cfg, "mmap_read"); + if (param_value && !strcmp(param_value, "yes")) { + mmap_read = true; + msg_pspew("mmap_read enabled.\n"); + } else if (param_value && !strlen(param_value)) { + msg_perr("Missing argument for mmap_read.\n"); + free(param_value); + return 1; + } else if (param_value) { + msg_perr("Unknown argument for mmap_read: \"%s\" (not \"yes\").\n", param_value); + free(param_value); + return 1; + } + free(param_value); + + if (!mmap_read) + return 0; + + master->max_data_read = MAX_DATA_READ_UNLIMITED; + master->read = amd_read_memmapped; + + return 0; +} + static int sb600spi_shutdown(void *data) { struct sb600spi_data *sb600_data = data; @@ -595,7 +628,7 @@ return 0; } -static const struct spi_master spi_master_sb600 = { +static struct spi_master spi_master_sb600 = { .max_data_read = FIFO_SIZE_OLD, .max_data_write = FIFO_SIZE_OLD - 3, .command = sb600_spi_send_command, @@ -608,7 +641,7 @@ .probe_opcode = default_spi_probe_opcode, }; -static const struct spi_master spi_master_yangtze = { +static struct spi_master spi_master_yangtze = { .max_data_read = FIFO_SIZE_YANGTZE - 3, /* Apparently the big SPI 100 buffer is not a ring buffer. */ .max_data_write = FIFO_SIZE_YANGTZE - 3, .command = spi100_spi_send_command, @@ -621,19 +654,6 @@ .probe_opcode = default_spi_probe_opcode, }; -static const struct spi_master spi_master_promontory = { - .max_data_read = MAX_DATA_READ_UNLIMITED, - .max_data_write = FIFO_SIZE_YANGTZE - 3, - .command = spi100_spi_send_command, - .multicommand = default_spi_send_multicommand, - .map_flash_region = physmap, - .unmap_flash_region = physunmap, - .read = promontory_read_memmapped, - .write_256 = default_spi_write_256, - .shutdown = sb600spi_shutdown, - .probe_opcode = default_spi_probe_opcode, -}; - int sb600_probe_spi(const struct programmer_cfg *cfg, struct pci_dev *dev) { struct pci_dev *smbus_dev; @@ -809,13 +829,18 @@ data->flash = NULL; data->spibar = sb600_spibar; + struct spi_master *master; + /* Starting with Yangtze the SPI controller got a different interface with a much bigger buffer. */ if (amd_gen < CHIPSET_YANGTZE) - register_spi_master(&spi_master_sb600, data); - else if (amd_gen == CHIPSET_YANGTZE) - register_spi_master(&spi_master_yangtze, data); - else - register_spi_master(&spi_master_promontory, data); + master = &spi_master_sb600; + else if (amd_gen >= CHIPSET_YANGTZE) + master = &spi_master_yangtze; + + if (handle_mmap_read(cfg, master)) + return ERROR_FLASHROM_FATAL; + + register_spi_master(master, data); return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/71565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I13eb5a646d3569170b3911ae7b3127cd3e6022aa Gerrit-Change-Number: 71565 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in flashrom[master]: flashrom.c:Add function to get a flattened view of the chip erase blocks
by Edward O'Callaghan (Code Review) Dec. 28, 2022

Dec. 28, 2022

Attention is currently required from: Simon Buhrow, Nico Huber, Thomas Heijligen, Paul Menzel, Aarya. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/65879 ) Change subject: flashrom.c:Add function to get a flattened view of the chip erase blocks ...................................................................... Patch Set 55: (1 comment) File erasure_layout.c: https://review.coreboot.org/c/flashrom/+/65879/comment/a77259ce_7a9f939e PS55, Line 58: chipoff_t addr = 0; : : for (int i = 0; addr < chip->total_size * 1024; i++) { : const struct eraseblock *block = &chip->block_erasers[eraser_idx].eraseblocks[i]; : block_count += block->count; : addr += block->size * block->count; : } ``` static size_t calculate_block_count(const struct flashchip *chip, size_t eraser_idx) { size_t block_count = 0; chipoff_t addr = 0; for (size_t i = 0; addr < chip->total_size * 1024; i++) { const struct eraseblock *block = &chip->block_erasers[eraser_idx].eraseblocks[i]; block_count += block->count; addr += block->size * block->count; } return block_count; } ``` -- To view, visit https://review.coreboot.org/c/flashrom/+/65879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iafe78de00daa55f7114bd4ce09465dd88074ece4 Gerrit-Change-Number: 65879 Gerrit-PatchSet: 55 Gerrit-Owner: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Dec 2022 11:22:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in flashrom[master]: flashrom.c:Add function to get a flattened view of the chip erase blocks
by Edward O'Callaghan (Code Review) Dec. 28, 2022

Dec. 28, 2022

Attention is currently required from: Simon Buhrow, Nico Huber, Thomas Heijligen, Paul Menzel, Aarya. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/65879 ) Change subject: flashrom.c:Add function to get a flattened view of the chip erase blocks ...................................................................... Patch Set 55: (1 comment) File erasure_layout.c: https://review.coreboot.org/c/flashrom/+/65879/comment/66334cbb_43abe22f PS55, Line 82: layout[layout_idx].layout_list[block_num].start_addr = start_addr; : layout[layout_idx].layout_list[block_num].end_addr = end_addr; : layout[layout_idx].layout_list[block_num].selected = false; : layout[layout_idx].layout_list[block_num].block_num = block_num; : if (layout_idx > 0) { : layout[layout_idx].layout_list[block_num].first_sub_block_index = sub_block_index; : while (layout[layout_idx-1].layout_list[sub_block_index].start_addr >= start_addr && : layout[layout_idx-1].layout_list[sub_block_index].end_addr <= end_addr && : sub_block_index < layout[layout_idx-1].block_count) { : sub_block_index++; : } : layout[layout_idx].layout_list[block_num].last_sub_block_index = sub_block_index - 1; : } ``` static void init_eraseblock(struct erase_layout *layout, size_t idx, size_t block_num, [..]) { struct eraseblock_data *edata = &layout[idx].layout_list[block_num]; edata->start_addr = start_addr; edata->end_addr = end_addr; edata->selected = false; edata->block_num = block_num; if (!idx) return; edata->first_sub_block_index = sub_block_index; do { struct eraseblock_data *subedata = &layout[idx - 1].layout_list[sub_block_index]; const sub_block_count = layout[idx - 1].block_count; bool sub_block_inc = subedata->start_addr >= start_addr && subedata->end_addr <= end_addr && sub_block_index < sub_block_count; sub_block_index++; } while (sub_block_inc); edata->last_sub_block_index = sub_block_index - 1; } ``` something like this. -- To view, visit https://review.coreboot.org/c/flashrom/+/65879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iafe78de00daa55f7114bd4ce09465dd88074ece4 Gerrit-Change-Number: 65879 Gerrit-PatchSet: 55 Gerrit-Owner: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Dec 2022 01:03:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashrom.c: Add switch for legacy impl of erasure path
by Edward O'Callaghan (Code Review) Dec. 28, 2022

Dec. 28, 2022

Attention is currently required from: Felix Singer, Thomas Heijligen, Aarya. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/71119 ) Change subject: flashrom.c: Add switch for legacy impl of erasure path ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/flashrom/+/71119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib5660db0067c1c799dcb5c8e83b4a4826b236442 Gerrit-Change-Number: 71119 Gerrit-PatchSet: 7 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Dec 2022 00:41:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashrom.c:Add a function to get list of sectors that need erasing
by Edward O'Callaghan (Code Review) Dec. 28, 2022

Dec. 28, 2022

Attention is currently required from: Simon Buhrow, Aarya. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/65844 ) Change subject: flashrom.c:Add a function to get list of sectors that need erasing ...................................................................... Patch Set 74: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/65844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic57ca1cca3d1646543f6b5939ba9c35db8d08256 Gerrit-Change-Number: 65844 Gerrit-PatchSet: 74 Gerrit-Owner: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Dec 2022 00:41:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashrom.c: Guard against sending spi commands on non-spi mst
by Edward O'Callaghan (Code Review) Dec. 26, 2022

Dec. 26, 2022

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/71269 ) Change subject: flashrom.c: Guard against sending spi commands on non-spi mst ...................................................................... flashrom.c: Guard against sending spi commands on non-spi mst Validate (flash->chip->bustype == BUS_SPI) as ich copies the chip flags in the opaque master and tries incorrectly to issue 4BA commands which results in failure. The issue was detected only in the case of chips >16MB, in this case 'W25Q256FV' that has the feature bits: ``` .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | FEATURE_WRSR2, ``` The regression was noticed from, commit 0741727925b841c2479b993204ce58c5eb75185a ichspi.c: Read chip ID and use it to populate `flash->chip` TEST=In the case of 'W25Q256FV' on TigerLake. Change-Id: I7cce4f9c032d33c01bf616e27a50b9727a40fe1b Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M flashrom.c 1 file changed, 28 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/69/71269/1 diff --git a/flashrom.c b/flashrom.c index 62f38f8..f6862c4 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1944,7 +1944,8 @@ } /* Enable/disable 4-byte addressing mode if flash chip supports it */ - if (flash->chip->feature_bits & (FEATURE_4BA_ENTER | FEATURE_4BA_ENTER_WREN | FEATURE_4BA_ENTER_EAR7)) { + if ((flash->chip->bustype == BUS_SPI) && + (flash->chip->feature_bits & (FEATURE_4BA_ENTER | FEATURE_4BA_ENTER_WREN | FEATURE_4BA_ENTER_EAR7))) { int ret; if (spi_master_4ba(flash)) ret = spi_enter_4ba(flash); -- To view, visit https://review.coreboot.org/c/flashrom/+/71269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7cce4f9c032d33c01bf616e27a50b9727a40fe1b Gerrit-Change-Number: 71269 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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[M] Change in flashrom[master]: cli_classic.c: Allow ctrl of behaviour with WO and RO regions
by Edward O'Callaghan (Code Review) Dec. 24, 2022

Dec. 24, 2022

Attention is currently required from: Angel Pons, Nikolai Artemiev. Hello Felix Singer, build bot (Jenkins), Angel Pons, Nikolai Artemiev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/70895 to look at the new patch set (#7). Change subject: cli_classic.c: Allow ctrl of behaviour with WO and RO regions ...................................................................... cli_classic.c: Allow ctrl of behaviour with WO and RO regions Add two force flags to the flashrom CLI frontend, --force-skip-nonreadable - skip reading non-readbale regions without failure, --force-skip-nonwritable - skip writing non-writable regions without failure. Each flag allows the user to finely control the behaviour of flashrom read and write operations when flashrom encounters a known permission problem. This can be useful in cases such as wanting to write a pre-padded BIOS image across flash where locked regions just wish to be left untouched without the need to craft a custom layout file for each case. Alternatively, to read a copy of flash complete with padding for regions that are known not to be readable at runtime however the user does not know the layout of flash or just wishes to have a padded binary read back. Change-Id: Iff753b748765410ea38b845613c361db7ad16a61 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M cli_classic.c M flashrom.8.tmpl 2 files changed, 57 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/70895/7 -- To view, visit https://review.coreboot.org/c/flashrom/+/70895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iff753b748765410ea38b845613c361db7ad16a61 Gerrit-Change-Number: 70895 Gerrit-PatchSet: 7 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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