November 2022 - flashrom-gerrit

[M] Change in flashrom[1.3.x_infdev]: sb600spi.c: Drop "Promontory" support
by Angel Pons (Code Review) 04 Nov '22

04 Nov '22

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/flashrom/+/68823 ) Change subject: sb600spi.c: Drop "Promontory" support ...................................................................... Abandoned Sorry, let's go with CB:68824 instead. We've got the `1.3.x` release branch now. -- To view, visit https://review.coreboot.org/c/flashrom/+/68823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x_infdev Gerrit-Change-Id: I1457946dce68321b496d9ffa40a0c5ab46455f72 Gerrit-Change-Number: 68823 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in flashrom[master]: tests: ensure chip erase operation is executed
by Nikolai Artemiev (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Nikolai Artemiev. Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/69130 to look at the new patch set (#2). Change subject: tests: ensure chip erase operation is executed ...................................................................... tests: ensure chip erase operation is executed The `full_chip_erase_with_wp_dummyflasher_test_success` test case checks that erasing a write-protected region of a dummyflasher chip fails. However erase optimization may cause the erase operation to be skipped if the flash contents are already erased, so the erase operation appears to succeed and the test case fails. Writing a non-erased value to the chip ensures that an erase operation will be executed and (hopefully) fail due to write protection. BUG=b:237620197 BRANCH=none TEST=ninja test Change-Id: Ia00444dcd2ad96c64832a13201efbd064cd7302d Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M include/flash.h M tests/chip_wp.c 2 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/30/69130/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/69130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia00444dcd2ad96c64832a13201efbd064cd7302d Gerrit-Change-Number: 69130 Gerrit-PatchSet: 2 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[1.3.x]: sb600spi.c: Drop "Promontory" support
by Angel Pons (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Nico Huber, Thomas Heijligen, Edward O'Callaghan, Anastasia Klimchuk, Swift Geek (Sebastian Grzywna). Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/68824 ) Change subject: sb600spi.c: Drop "Promontory" support ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Sorry, mind re-reviewing this? The 1.3.x_infdev branch is going away. -- To view, visit https://review.coreboot.org/c/flashrom/+/68824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: I1457946dce68321b496d9ffa40a0c5ab46455f72 Gerrit-Change-Number: 68824 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 00:13:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in flashrom[1.3.x]: sb600spi.c: Drop "Promontory" support
by Angel Pons (Code Review) 04 Nov '22

04 Nov '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/68824 ) Change subject: sb600spi.c: Drop "Promontory" support ...................................................................... sb600spi.c: Drop "Promontory" support The "Promontory" code is riddled with issues, some of them can result in soft bricks. Moreover, Promontory doesn't have a SPI controller. Drop support for "Promontory" in flashrom for now: it's holding back the entire project and it's unlikely that it'll be fixed in a timely manner. Change-Id: I1457946dce68321b496d9ffa40a0c5ab46455f72 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M sb600spi.c 1 file changed, 16 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/24/68824/1 diff --git a/sb600spi.c b/sb600spi.c index 6020145..2e7be81 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -48,7 +48,6 @@ CHIPSET_HUDSON234, CHIPSET_BOLTON, CHIPSET_YANGTZE, - CHIPSET_PROMONTORY, }; #define FIFO_SIZE_OLD 8 @@ -124,18 +123,6 @@ if (rev == 0x4a) { msg_pdbg("Yangtze detected.\n"); return CHIPSET_YANGTZE; - /** - * FCH chipsets called 'Promontory' are one's with the - * so-called SPI100 ip core that uses memory mapping and - * not a ring buffer for transactions. Typically this is - * found on both Stoney Ridge and Zen platforms. - * - * The revisions I have found by searching various lspci - * outputs are as follows: 0x4b, 0x59, 0x61 & 0x71. - */ - } else if (rev == 0x4b || rev == 0x51 || rev == 0x59 || rev == 0x61 || rev == 0x71) { - msg_pdbg("Promontory (rev 0x%02x) detected.\n", rev); - return CHIPSET_PROMONTORY; } else { msg_pwarn("FCH device found but SMBus revision 0x%02x does not match known values.\n" "Please report this to flashrom(a)flashrom.org and include this log and\n" @@ -572,18 +559,6 @@ return amd_imc_shutdown(dev); } -static int promontory_read_memmapped(struct flashctx *flash, uint8_t *buf, - unsigned int start, unsigned int len) -{ - struct sb600spi_data * data = (struct sb600spi_data *)flash->mst->spi.data; - if (!data->flash) { - map_flash(flash); - data->flash = flash; /* keep a copy of flashctx for unmap() on tear-down. */ - } - mmio_readn((void *)(flash->virtual_memory + start), buf, len); - return 0; -} - static int sb600spi_shutdown(void *data) { struct sb600spi_data *sb600_data = data; @@ -623,20 +598,6 @@ .probe_opcode = default_spi_probe_opcode, }; -static const struct spi_master spi_master_promontory = { - .max_data_read = MAX_DATA_READ_UNLIMITED, - .max_data_write = FIFO_SIZE_YANGTZE - 3, - .command = spi100_spi_send_command, - .multicommand = default_spi_send_multicommand, - .map_flash_region = physmap, - .unmap_flash_region = physunmap, - .read = promontory_read_memmapped, - .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, - .shutdown = sb600spi_shutdown, - .probe_opcode = default_spi_probe_opcode, -}; - int sb600_probe_spi(const struct programmer_cfg *cfg, struct pci_dev *dev) { struct pci_dev *smbus_dev; @@ -740,7 +701,6 @@ case CHIPSET_SB89XX: case CHIPSET_HUDSON234: case CHIPSET_YANGTZE: - case CHIPSET_PROMONTORY: msg_pdbg(", SpiBusy=%i", (tmp >> 31) & 0x1); default: break; } @@ -817,8 +777,6 @@ register_spi_master(&spi_master_sb600, data); else if (amd_gen == CHIPSET_YANGTZE) register_spi_master(&spi_master_yangtze, data); - else - register_spi_master(&spi_master_promontory, data); return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/68824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: I1457946dce68321b496d9ffa40a0c5ab46455f72 Gerrit-Change-Number: 68824 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in flashrom[master]: ichspi.c: heap allocate hwseq_data to remove global
by Edward O'Callaghan (Code Review) 03 Nov '22

03 Nov '22

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/68774 ) Change subject: ichspi.c: heap allocate hwseq_data to remove global ...................................................................... ichspi.c: heap allocate hwseq_data to remove global Align hwseq path in ichspi with the rest of the flashrom tree by making hwseq_data a heap allocation within the life-time of the driver managed by the driver registration API. Change-Id: Ib362c5ab2d3e8afee2c3c7d3135cc4414d6bd6c3 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68774 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M ichspi.c 1 file changed, 35 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/ichspi.c b/ichspi.c index bbd2c91..b3beaea 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1255,13 +1255,13 @@ return result; } -static struct hwseq_data { +struct hwseq_data { uint32_t size_comp0; uint32_t size_comp1; uint32_t addr_mask; bool only_4k; uint32_t hsfc_fcycle; -} g_hwseq_data; +}; static struct hwseq_data *get_hwseq_data_from_context(const struct flashctx *flash) { @@ -1591,6 +1591,12 @@ return 0; } +static int ich_hwseq_shutdown(void *data) +{ + free(data); + return 0; +} + static int ich_spi_send_multicommand(const struct flashctx *flash, struct spi_command *cmds) { @@ -1804,6 +1810,7 @@ .erase = ich_hwseq_block_erase, .read_register = ich_hwseq_read_status, .write_register = ich_hwseq_write_status, + .shutdown = ich_hwseq_shutdown, }; static int init_ich7_spi(void *spibar, enum ich_chipset ich_gen) @@ -1947,7 +1954,8 @@ enum ich_spi_mode ich_spi_mode = ich_auto; size_t num_freg, num_pr, reg_pr0; - init_chipset_properties(&swseq_data, &g_hwseq_data, &num_freg, &num_pr, &reg_pr0, ich_gen); + struct hwseq_data hwseq_data; + init_chipset_properties(&swseq_data, &hwseq_data, &num_freg, &num_pr, &reg_pr0, ich_gen); int ret = get_ich_spi_mode_param(cfg, &ich_spi_mode); if (ret) @@ -2167,16 +2175,20 @@ msg_perr("Could not determine density of flash component %d.\n", 0); return ERROR_FATAL; } - g_hwseq_data.size_comp0 = tmpi; + hwseq_data.size_comp0 = tmpi; tmpi = getFCBA_component_density(ich_gen, &desc, 1); if (tmpi < 0) { msg_perr("Could not determine density of flash component %d.\n", 1); return ERROR_FATAL; } - g_hwseq_data.size_comp1 = tmpi; + hwseq_data.size_comp1 = tmpi; - register_opaque_master(&opaque_master_ich_hwseq, &g_hwseq_data); + struct hwseq_data *opaque_hwseq_data = calloc(1, sizeof(struct hwseq_data)); + if (!opaque_hwseq_data) + return ERROR_FATAL; + memcpy(opaque_hwseq_data, &hwseq_data, sizeof(*opaque_hwseq_data)); + register_opaque_master(&opaque_master_ich_hwseq, opaque_hwseq_data); } else { register_spi_master(&spi_master_ich9, NULL); } -- To view, visit https://review.coreboot.org/c/flashrom/+/68774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib362c5ab2d3e8afee2c3c7d3135cc4414d6bd6c3 Gerrit-Change-Number: 68774 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: merged

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[S] Change in flashrom[master]: ichspi.c: derive hsfc_fcycle from ctx in ich_start_hwseq_xfer()
by Edward O'Callaghan (Code Review) 03 Nov '22

03 Nov '22

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/68773 ) Change subject: ichspi.c: derive hsfc_fcycle from ctx in ich_start_hwseq_xfer() ...................................................................... ichspi.c: derive hsfc_fcycle from ctx in ich_start_hwseq_xfer() Allow helpers to derive driver specific data from the driver specific context instead of being a closure over a static global variable. Change-Id: Ib0ccf4b32fd1e2be2ecc3a4a4c6e397c8e901a0a Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68773 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M ichspi.c 1 file changed, 20 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/ichspi.c b/ichspi.c index 5d9fe0c..bbd2c91 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1350,6 +1350,7 @@ uint32_t addr_mask) { uint16_t hsfc; + struct hwseq_data *hwseq_data = get_hwseq_data_from_context(flash); /* Sets flash_addr in FADDR */ ich_hwseq_set_addr(flash_addr, addr_mask); @@ -1359,7 +1360,7 @@ /* Set up transaction parameters. */ hsfc = REGREAD16(ICH9_REG_HSFC); - hsfc &= ~g_hwseq_data.hsfc_fcycle; /* clear operation */ + hsfc &= ~hwseq_data->hsfc_fcycle; /* clear operation */ hsfc |= hsfc_cycle; hsfc |= HSFC_FDBC_VAL(len - 1); hsfc |= HSFC_FGO; /* start */ -- To view, visit https://review.coreboot.org/c/flashrom/+/68773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib0ccf4b32fd1e2be2ecc3a4a4c6e397c8e901a0a Gerrit-Change-Number: 68773 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in flashrom[master]: ichspi.c: plumb flashctx through hwseq xfer helper
by Edward O'Callaghan (Code Review) 03 Nov '22

03 Nov '22

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/68772 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: ichspi.c: plumb flashctx through hwseq xfer helper ...................................................................... ichspi.c: plumb flashctx through hwseq xfer helper Change is a NOP to prepare ichspi to remove hwseq_data being a global symbol in CB:68774. This allows for the helper functions to derive their data from the driver data context. Change-Id: I67b5aa6350930d912e5036473ac3e792debac0bd Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68772 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M ichspi.c 1 file changed, 26 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/ichspi.c b/ichspi.c index 6d3535c..5d9fe0c 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1345,7 +1345,8 @@ } /* Fire up a transfer using the hardware sequencer. */ -static void ich_start_hwseq_xfer(uint32_t hsfc_cycle, uint32_t flash_addr, size_t len, +static void ich_start_hwseq_xfer(const struct flashctx *flash, + uint32_t hsfc_cycle, uint32_t flash_addr, size_t len, uint32_t addr_mask) { uint16_t hsfc; @@ -1376,7 +1377,7 @@ } /* Execute SPI flash transfer */ -static int ich_exec_sync_hwseq_xfer(uint32_t hsfc_cycle, uint32_t flash_addr, +static int ich_exec_sync_hwseq_xfer(const struct flashctx *flash, uint32_t hsfc_cycle, uint32_t flash_addr, size_t len, enum ich_chipset ich_gen, uint32_t addr_mask) { if (ich_wait_for_hwseq_spi_cycle_complete()) { @@ -1384,7 +1385,7 @@ return 1; } - ich_start_hwseq_xfer(hsfc_cycle, flash_addr, len, addr_mask); + ich_start_hwseq_xfer(flash, hsfc_cycle, flash_addr, len, addr_mask); return ich_hwseq_wait_for_cycle_complete(len, ich_gen, addr_mask); } @@ -1399,7 +1400,7 @@ } msg_pdbg("Reading Status register\n"); - if (ich_exec_sync_hwseq_xfer(HSFC_CYCLE_RD_STATUS, 0, len, ich_generation, + if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_RD_STATUS, 0, len, ich_generation, hwseq_data->addr_mask)) { msg_perr("Reading Status register failed\n!!"); return -1; @@ -1422,7 +1423,7 @@ ich_fill_data(&value, len, ICH9_REG_FDATA0); - if (ich_exec_sync_hwseq_xfer(HSFC_CYCLE_WR_STATUS, 0, len, ich_generation, + if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_WR_STATUS, 0, len, ich_generation, hwseq_data->addr_mask)) { msg_perr("Writing Status register failed\n!!"); return -1; @@ -1518,7 +1519,7 @@ msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); - if (ich_exec_sync_hwseq_xfer(HSFC_CYCLE_BLOCK_ERASE, addr, 0, ich_generation, + if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_BLOCK_ERASE, addr, 0, ich_generation, hwseq_data->addr_mask)) return -1; return 0; @@ -1546,7 +1547,7 @@ /* as well as flash chip page borders as demanded in the Intel datasheets. */ block_len = min(block_len, 256 - (addr & 0xFF)); - if (ich_exec_sync_hwseq_xfer(HSFC_CYCLE_READ, addr, block_len, ich_generation, + if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_READ, addr, block_len, ich_generation, hwseq_data->addr_mask)) return 1; ich_read_data(buf, block_len, ICH9_REG_FDATA0); @@ -1579,7 +1580,7 @@ block_len = min(block_len, 256 - (addr & 0xFF)); ich_fill_data(buf, block_len, ICH9_REG_FDATA0); - if (ich_exec_sync_hwseq_xfer(HSFC_CYCLE_WRITE, addr, block_len, ich_generation, + if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_WRITE, addr, block_len, ich_generation, hwseq_data->addr_mask)) return -1; addr += block_len; -- To view, visit https://review.coreboot.org/c/flashrom/+/68772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I67b5aa6350930d912e5036473ac3e792debac0bd Gerrit-Change-Number: 68772 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: merged

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[S] Change in flashrom[master]: tests: ensure chip erase operation is executed
by Anastasia Klimchuk (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Nikolai Artemiev. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69130 ) Change subject: tests: ensure chip erase operation is executed ...................................................................... Patch Set 1: Code-Review+1 (4 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/69130/comment/e5843999_2310a8f9 PS1, Line 18: exectued exectued -> executed (typo) https://review.coreboot.org/c/flashrom/+/69130/comment/aa4d1430_795fa99d PS1, Line 18: (hopefully) "and is expected to fail" Patchset: PS1: Thanks for the patch. Very good timing! File include/flash.h: https://review.coreboot.org/c/flashrom/+/69130/comment/13da1304_8665acb7 PS1, Line 159: #define UNERASED_VALUE(flash) Will this ever be needed outside of tests? If not, we have tests/include/test.h for this kind of macros. Also please add comment, even a short one, if you move to tests/include/test.h. Thanks! -- To view, visit https://review.coreboot.org/c/flashrom/+/69130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia00444dcd2ad96c64832a13201efbd064cd7302d Gerrit-Change-Number: 69130 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Thu, 03 Nov 2022 23:53:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in flashrom[master]: tests: ensure chip erase operation is executed
by Edward O'Callaghan (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Nikolai Artemiev, Anastasia Klimchuk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69130 ) Change subject: tests: ensure chip erase operation is executed ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/69130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia00444dcd2ad96c64832a13201efbd064cd7302d Gerrit-Change-Number: 69130 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 03 Nov 2022 23:45:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in flashrom[master]: writeprotect,ichspi,spi25: handle register access constraints
by Nikolai Artemiev (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Subrata Banik, Edward O'Callaghan. Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69129 ) Change subject: writeprotect,ichspi,spi25: handle register access constraints ...................................................................... Patch Set 2: (1 comment) File ichspi.c: https://review.coreboot.org/c/flashrom/+/69129/comment/6504e066_86a8eec3 PS1, Line 1398: SPI_INVALID_OPCODE > Add a code comment. Done -- To view, visit https://review.coreboot.org/c/flashrom/+/69129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2145749dcc51f4556550650dab5aa1049f879c45 Gerrit-Change-Number: 69129 Gerrit-PatchSet: 2 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Thu, 03 Nov 2022 23:28:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Comment-In-Reply-To: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: comment

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flashrom-gerrit November 2022