October 2022 - flashrom-gerrit

Change in flashrom[master]: Fix a handful of compiler warnings
by Ryan O'Leary (Code Review) Aug. 29, 2026

Aug. 29, 2026

Ryan O'Leary has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36946 ) Change subject: Fix a handful of compiler warnings ...................................................................... Fix a handful of compiler warnings These warnings (which I believe are not enabled by default) were generated by -Wformat-security and -Wenum-conversion. Change-Id: I3d01f4ff620f4c4111dd675d49ce3254f2360b29 Signed-off-by: Ryan O'Leary <ryanoleary(a)google.com> --- M libflashrom.c M print.c M programmer.h 3 files changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/46/36946/1 diff --git a/libflashrom.c b/libflashrom.c index 0dec22e..b15b5f6 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -188,7 +188,8 @@ for (; i < boards_known_size; ++i) { supported_boards[i].vendor = binfo[i].vendor; supported_boards[i].name = binfo[i].name; - supported_boards[i].working = binfo[i].working; + supported_boards[i].working = + (enum flashrom_test_state)binfo[i].working; } } else { msg_gerr("Memory allocation error!\n"); @@ -226,8 +227,9 @@ supported_chipsets[i].chipset = chipset[i].device_name; supported_chipsets[i].vendor_id = chipset[i].vendor_id; supported_chipsets[i].chipset_id = chipset[i].device_id; - supported_chipsets[i].status = chipset[i].status; - } + supported_chipsets[i].status = + (enum flashrom_test_state)chipset[i].status; + } } else { msg_gerr("Memory allocation error!\n"); } diff --git a/print.c b/print.c index 596fc53..173c7da 100644 --- a/print.c +++ b/print.c @@ -401,7 +401,7 @@ for (i = 0; i < maxboardlen - strlen(b->name); i++) msg_ginfo(" "); - msg_pinfo(test_state_to_text(b->working)); + msg_pinfo("%s", test_state_to_text(b->working)); for (e = board_matches; e->vendor_name != NULL; e++) { if (strcmp(e->vendor_name, b->vendor) diff --git a/programmer.h b/programmer.h index 5a21b2e..96add05 100644 --- a/programmer.h +++ b/programmer.h @@ -307,7 +307,7 @@ /* cbtable.c */ int cb_parse_table(const char **vendor, const char **model); -int cb_check_image(const uint8_t *bios, unsigned int size); +int cb_check_image(const uint8_t *image, unsigned int size); /* dmi.c */ #if defined(__i386__) || defined(__x86_64__) -- To view, visit https://review.coreboot.org/c/flashrom/+/36946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3d01f4ff620f4c4111dd675d49ce3254f2360b29 Gerrit-Change-Number: 36946 Gerrit-PatchSet: 1 Gerrit-Owner: Ryan O'Leary <ryanoleary(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: util/ich_descriptor_tool: use clang's style suggestion
by Idwer Vollering (Code Review) Aug. 29, 2026

Aug. 29, 2026

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34945 ) Change subject: util/ich_descriptor_tool: use clang's style suggestion ...................................................................... util/ich_descriptor_tool: use clang's style suggestion Tested on: FreeBSD clang version 8.0.1 (tags/RELEASE_801/final 366581) (based on LLVM 8.0.1) Target: x86_64-unknown-freebsd13.0 Change-Id: Ie80c4c4d70c8ccf357ba8e65f454fc4d4fa8c058 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- M util/ich_descriptors_tool/ich_descriptors_tool.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/45/34945/1 diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 2db0f62..9fcb2ba 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -152,7 +152,7 @@ const char *fn = NULL; const char *csn = NULL; enum ich_chipset cs = CHIPSET_ICH_UNKNOWN; - struct ich_descriptors desc = { 0 }; + struct ich_descriptors desc = { { 0 } }; while ((opt = getopt(argc, argv, "df:c:")) != -1) { switch (opt) { -- To view, visit https://review.coreboot.org/c/flashrom/+/34945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie80c4c4d70c8ccf357ba8e65f454fc4d4fa8c058 Gerrit-Change-Number: 34945 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: realtek_mst_i2c_spi.c: Add bootloader slot param
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40772 ) Change subject: realtek_mst_i2c_spi.c: Add bootloader slot param ...................................................................... realtek_mst_i2c_spi.c: Add bootloader slot param Add spi_master parameter that allows the user to specify which firmware paritition slot to select in the bootloader upon flashing a new image. BUG=b:155051790 BRANCH=none TEST=builds Change-Id: I1fa6b30ea67e7feb0651dd4b4dc3d5c308fc83c8 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M realtek_mst_i2c_spi.c 1 file changed, 23 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/72/40772/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 6f7dd70..03c0893 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -38,6 +38,7 @@ struct realtek_mst_i2c_spi_data { int fd; + int slot; /* 0: slot A, 1: slot B, -1: undefined slot */ }; static int realtek_mst_i2c_spi_write_data(int fd, uint16_t addr, void *buf, uint16_t len) @@ -355,9 +356,9 @@ return ret; } -static int get_params(int *i2c_bus) +static int get_params(int *i2c_bus, int *slot) { - char *bus_str = NULL; + char *bus_str = NULL, *slot_str = NULL; int ret = SPI_GENERIC_ERROR; bus_str = extract_programmer_param("bus"); @@ -387,9 +388,26 @@ } else { msg_perr("%s: Bus number not specified.\n", __func__); } + + slot_str = extract_programmer_param("slot"); + if (slot_str) { + msg_pinfo("Using bootloader slot %s.\n", slot_str); + switch (slot_str[0]) { + case 'A': *slot = 0; break; + case 'B': *slot = 1; break; + default: + msg_perr("%s: Invalid slot specified.\n", __func__); + *slot = -1; + } + ret = 0; + goto get_params_done; + } + get_params_done: if (bus_str) free(bus_str); + if (slot_str) + free(slot_str); return ret; } @@ -397,9 +415,9 @@ int realtek_mst_i2c_spi_init(void) { int ret = 0; - int i2c_bus = 0; + int i2c_bus = 0, bl_slot = 0; - if (get_params(&i2c_bus)) + if (get_params(&i2c_bus, &bl_slot)) return SPI_GENERIC_ERROR; int fd = i2c_open(i2c_bus, REGISTER_ADDRESS, 0); @@ -428,6 +446,7 @@ } data->fd = fd; + data->slot = bl_slot; ret |= register_shutdown(realtek_mst_i2c_spi_shutdown, data); spi_master_i2c_realtek_mst.data = data; -- To view, visit https://review.coreboot.org/c/flashrom/+/40772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1fa6b30ea67e7feb0651dd4b4dc3d5c308fc83c8 Gerrit-Change-Number: 40772 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 4

Change in flashrom[master]: realtek_mst_i2c_spi.c: Fix wp gpio toggle
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/41125 ) Change subject: realtek_mst_i2c_spi.c: Fix wp gpio toggle ...................................................................... realtek_mst_i2c_spi.c: Fix wp gpio toggle Allow for toggling the GPIO pin 108 that is routed to the WP pin in the reference design. This need not always apply however is largely harmless for a better out-of-the-box experience. BUG=b:152558985,b:148745673 BRANCH=none TEST=builds && A double cycle of erase+write works. Change-Id: I825df3179cdd16f7c7ecf556b5ca29bfe6394346 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M realtek_mst_i2c_spi.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/25/41125/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 64458dd..6cb87fe 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -34,6 +34,7 @@ #define MCU_MODE 0x6F #define ENTER_ISP_MODE 0x80 #define START_WRITE_XFER 0xA0 +#define BUF_XFER_STATUS_MASK 0x10 #define WRITE_XFER_STATUS_MASK 0x20 #define MCU_DATA_PORT 0x70 @@ -145,7 +146,7 @@ return ret; } -static int realtek_mst_i2c_spi_disable_protection(int fd) +static int realtek_mst_i2c_spi_toggle_protection(int fd, int enable) { int ret = 0; uint8_t val = 0; @@ -164,8 +165,9 @@ ret |= realtek_mst_i2c_spi_write_register(fd, 0xF5, (val & 0xF8) | 0x01); /* Set pin value to high, 0xFFD7[0] = 1. */ + uint8_t en = enable ? 0x00 : 0x01; ret |= realtek_mst_i2c_spi_read_register(fd, 0xD7, &val); - ret |= realtek_mst_i2c_spi_write_register(fd, 0xD7, (val & 0xFE) | 0x01); + ret |= realtek_mst_i2c_spi_write_register(fd, 0xD7, (val & 0xFE) | en); return ret; } @@ -331,7 +333,7 @@ if (fd < 0) return SPI_GENERIC_ERROR; - ret = realtek_mst_i2c_spi_disable_protection(fd); + ret = realtek_mst_i2c_spi_toggle_protection(fd, 0); if (ret) return ret; @@ -349,7 +351,8 @@ break; /* Wait for empty buffer. */ - ret |= realtek_mst_i2c_spi_wait_command_done(fd, MCU_MODE, 0x10, 0x10, 1); + ret |= realtek_mst_i2c_spi_wait_command_done(fd, MCU_MODE, + BUF_XFER_STATUS_MASK, 0x10, 1); if (ret) break; @@ -362,8 +365,7 @@ break; } - - /* TODO: re-enable the write protection? */ + ret |= realtek_mst_i2c_spi_toggle_protection(fd, 1); return ret; } -- To view, visit https://review.coreboot.org/c/flashrom/+/41125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I825df3179cdd16f7c7ecf556b5ca29bfe6394346 Gerrit-Change-Number: 41125 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: [WIP] Add uncrustify on/off markers where appropriate
by David Hendricks (Code Review) Aug. 29, 2026

Aug. 29, 2026

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/42555 ) Change subject: [WIP] Add uncrustify on/off markers where appropriate ...................................................................... [WIP] Add uncrustify on/off markers where appropriate Change-Id: I146a32e921d1c828a7d05ebb88373abe22e89053 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M board_enable.c M chipset_enable.c M print.c 3 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/55/42555/1 diff --git a/board_enable.c b/board_enable.c index 9cf0103..e95fcff 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2349,6 +2349,7 @@ */ /* Please keep this list alphabetically ordered by vendor/board name. */ +/* *INDENT-OFF* */ const struct board_match board_matches[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */ @@ -2530,6 +2531,7 @@ #endif { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */ }; +/* *INDENT-ON* */ int selfcheck_board_enables(void) { diff --git a/chipset_enable.c b/chipset_enable.c index 632679c..49f4f2e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1690,6 +1690,7 @@ #define B_S (BUS_SPI) /* Please keep this list numerically sorted by vendor/device ID. */ +/* *INDENT-OFF* */ const struct penable chipset_enables[] = { #if defined(__i386__) || defined(__x86_64__) {0x1002, 0x4377, B_PFL, OK, "ATI", "SB400", enable_flash_sb400}, @@ -2066,6 +2067,7 @@ #endif {0}, }; +/* *INDENT-ON* */ int chipset_flash_enable(void) { diff --git a/print.c b/print.c index feca45e..06561ec 100644 --- a/print.c +++ b/print.c @@ -515,6 +515,7 @@ #endif /* Please keep this list alphabetically ordered by vendor/board. */ +/* *INDENT-OFF* */ const struct board_info boards_known[] = { #if defined(__i386__) || defined(__x86_64__) B("A-Trend", "ATC-6220", OK, "http://www.motherboard.cz/mb/atrend/atc6220.htm", NULL), @@ -1142,8 +1143,10 @@ {0}, }; +/* *INDENT-ON* */ /* Please keep this list alphabetically ordered by vendor/board. */ +/* *INDENT-OFF* */ const struct board_info laptops_known[] = { #if defined(__i386__) || defined(__x86_64__) B("Acer", "Aspire 1520", OK, "http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspir…", NULL), @@ -1176,4 +1179,5 @@ {0}, }; +/* *INDENT-ON* */ #endif -- To view, visit https://review.coreboot.org/c/flashrom/+/42555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I146a32e921d1c828a7d05ebb88373abe22e89053 Gerrit-Change-Number: 42555 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: spi25.c: Improve spi_simple_write_cmd() diags and readability
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47452 ) Change subject: spi25.c: Improve spi_simple_write_cmd() diags and readability ...................................................................... spi25.c: Improve spi_simple_write_cmd() diags and readability Clearly initialise the cmds[] array of structures with explicit values and improve failure diagnostic line to inline failing op. BUG=b:170690915 BRANCH=none TEST=shows opcode Change-Id: Ib9fc82558035e511ee485fb5aab0bcd3e164c6ba Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M spi25.c 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/52/47452/1 diff --git a/spi25.c b/spi25.c index 213273f..41fa3dd 100644 --- a/spi25.c +++ b/spi25.c @@ -324,20 +324,22 @@ { struct spi_command cmds[] = { { - .readarr = 0, .writecnt = JEDEC_WREN_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, }, { - .readarr = 0, .writecnt = 1, .writearr = (const unsigned char[]){ op }, + .readcnt = 0, + .readarr = NULL, }, NULL_SPI_CMD, }; const int result = spi_send_multicommand(flash, cmds); if (result) - msg_cerr("%s failed during command execution\n", __func__); + msg_cerr("%s: opcode=0x%x failed during command execution\n", __func__, op); const int status = poll_delay ? spi_poll_wip(flash, poll_delay) : 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/47452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib9fc82558035e511ee485fb5aab0bcd3e164c6ba Gerrit-Change-Number: 47452 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 6

Change in flashrom[master]: ichspi: WIP Move global state into spi_master 'data' field
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43504 ) Change subject: ichspi: WIP Move global state into spi_master 'data' field ...................................................................... ichspi: WIP Move global state into spi_master 'data' field NOT-FOR-MERGE-YET. Change-Id: I368846039445f5e52a7c84a91676ee13b4aab9be Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 42 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/04/43504/1 diff --git a/ichspi.c b/ichspi.c index b90b864..19ce8cf 100644 --- a/ichspi.c +++ b/ichspi.c @@ -239,6 +239,10 @@ static void *ich_spibar = NULL; +struct ich_spi_data { + enum ich_chipset ich_gen; +}; + typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode uint8_t spi_type; //This commands spi type @@ -494,7 +498,7 @@ return 0xFF; } -static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt) +static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt, enum ich_chipset ich_gen) { uint8_t spi_type; @@ -524,7 +528,7 @@ int oppos = 2; // use original JEDEC_BE_D8 offset curopcodes->opcode[oppos].opcode = opcode; curopcodes->opcode[oppos].spi_type = spi_type; - program_opcodes(curopcodes, 0, ich_generation); + program_opcodes(curopcodes, 0, ich_gen); oppos = find_opcode(curopcodes, opcode); msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); return oppos; @@ -1079,8 +1083,11 @@ { /* max_data_read == max_data_write for all Intel/VIA SPI masters */ uint8_t maxlength = flash->mst->spi.max_data_read; + const struct ich_spi_data *ich_data = + (const struct ich_spi_data *)flash->mst->spi.data; + enum ich_chipset ich_gen = ich_data->ich_gen; - if (ich_generation == CHIPSET_ICH_UNKNOWN) { + if (ich_gen == CHIPSET_ICH_UNKNOWN) { msg_perr("%s: unsupported chipset\n", __func__); return -1; } @@ -1092,7 +1099,7 @@ return SPI_INVALID_LENGTH; } - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_ICH7: case CHIPSET_TUNNEL_CREEK: case CHIPSET_CENTERTON: @@ -1115,12 +1122,15 @@ uint32_t addr = 0; uint8_t *data; int count; + const struct ich_spi_data *ich_data = + (const struct ich_spi_data *)flash->mst->spi.data; + enum ich_chipset ich_gen = ich_data->ich_gen; /* find cmd in opcodes-table */ opcode_index = find_opcode(curopcodes, cmd); if (opcode_index == -1) { if (!ichspi_lock) - opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt); + opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt, ich_gen); if (opcode_index == SPI_INVALID_LENGTH) { msg_pdbg("OPCODE 0x%02x has unsupported length, will not execute.\n", cmd); return SPI_INVALID_LENGTH; @@ -1380,6 +1390,9 @@ uint32_t erase_block; uint16_t hsfc; uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + const struct ich_spi_data *ich_data = + (const struct ich_spi_data *)flash->mst->spi.data; + enum ich_chipset ich_gen = ich_data->ich_gen; erase_block = ich_hwseq_get_erase_block_size(addr); if (len != erase_block) { @@ -1416,10 +1429,10 @@ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ hsfc |= HSFC_FGO; /* start */ msg_pdbg("HSFC used for block erasing: "); - prettyprint_ich9_reg_hsfc(hsfc, ich_generation); + prettyprint_ich9_reg_hsfc(hsfc, ich_gen); REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, len, ich_generation)) + if (ich_hwseq_wait_for_cycle_complete(timeout, len, ich_gen)) return -1; return 0; } @@ -1430,6 +1443,9 @@ uint16_t hsfc; uint16_t timeout = 100 * 60; uint8_t block_len; + const struct ich_spi_data *ich_data = + (const struct ich_spi_data *)flash->mst->spi.data; + enum ich_chipset ich_gen = ich_data->ich_gen; if (addr + len > flash->chip->total_size * 1024) { msg_perr("Request to read from an inaccessible memory address " @@ -1456,7 +1472,7 @@ hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_generation)) + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_gen)) return 1; ich_read_data(buf, block_len, ICH9_REG_FDATA0); addr += block_len; @@ -1471,6 +1487,9 @@ uint16_t hsfc; uint16_t timeout = 100 * 60; uint8_t block_len; + const struct ich_spi_data *ich_data = + (const struct ich_spi_data *)flash->mst->spi.data; + enum ich_chipset ich_gen = ich_data->ich_gen; if (addr + len > flash->chip->total_size * 1024) { msg_perr("Request to write to an inaccessible memory address " @@ -1498,7 +1517,7 @@ hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_generation)) + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_gen)) return -1; addr += block_len; buf += block_len; @@ -1539,7 +1558,7 @@ * No need to bother with fixups. */ if (!ichspi_lock) { - oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt); + oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt, ich_gen); if (oppos == -1) continue; curopcodes->opcode[oppos].atomic = preoppos + 1; @@ -1686,7 +1705,7 @@ msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr)); } -static const struct spi_master spi_master_ich7 = { +static struct spi_master spi_master_ich7 = { .max_data_read = 64, .max_data_write = 64, .command = ich_spi_send_command, @@ -1696,7 +1715,7 @@ .write_aai = default_spi_write_aai, }; -static const struct spi_master spi_master_ich9 = { +static struct spi_master spi_master_ich9 = { .max_data_read = 64, .max_data_write = 64, .command = ich_spi_send_command, @@ -1733,6 +1752,16 @@ ich_generation = ich_gen; ich_spibar = spibar; + struct ich_spi_data *ich_data = calloc(1, sizeof(struct ich_spi_data)); + if (!ich_data) { + msg_perr("Unable to allocate space for extra SPI master data.\n"); + return SPI_GENERIC_ERROR; + } + + ich_data->ich_gen = ich_gen; + spi_master_ich7.data = ich_data; + spi_master_ich9.data = ich_data; + spi_master_via.data = ich_data; memset(&desc, 0x00, sizeof(struct ich_descriptors)); @@ -2046,7 +2075,7 @@ return 0; } -static const struct spi_master spi_master_via = { +static struct spi_master spi_master_via = { .max_data_read = 16, .max_data_write = 16, .command = ich_spi_send_command, -- To view, visit https://review.coreboot.org/c/flashrom/+/43504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I368846039445f5e52a7c84a91676ee13b4aab9be Gerrit-Change-Number: 43504 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: realtek_mst_i2c_spi.c: Make consistent with std=c99
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47909 ) Change subject: realtek_mst_i2c_spi.c: Make consistent with std=c99 ...................................................................... realtek_mst_i2c_spi.c: Make consistent with std=c99 Use 'modern' C to scope iterator declarations only to the loop constructs they are used in. BUG=none TEST=builds Change-Id: I9d9d1bf01209a7840f7b3fa2c6f7592375a74330 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M realtek_mst_i2c_spi.c 1 file changed, 4 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/47909/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 538b07a..151f7f6 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -205,7 +205,6 @@ const unsigned char *writearr, unsigned char *readarr) { - unsigned i; int max_timeout_mul = 1; int ret = 0; @@ -262,7 +261,7 @@ ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, ctrl_reg_val); ret |= realtek_mst_i2c_spi_write_register(fd, 0x61, writearr[0]); /* opcode */ - for (i = 0; i < writecnt; ++i) + for (unsigned i = 0; i < writecnt; ++i) ret |= realtek_mst_i2c_spi_write_register(fd, 0x64 + i, writearr[i + 1]); ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, ctrl_reg_val | 0x1); if (ret) @@ -272,7 +271,7 @@ if (ret) return ret; - for (i = 0; i < readcnt; ++i) + for (unsigned i = 0; i < readcnt; ++i) ret |= realtek_mst_i2c_spi_read_register(fd, 0x67 + i, &readarr[i]); return ret; @@ -306,7 +305,6 @@ static int realtek_mst_i2c_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { - unsigned i; int ret = 0; if (start & 0xff) @@ -339,7 +337,7 @@ uint8_t dummy; realtek_mst_i2c_spi_read_register(fd, MCU_DATA_PORT, &dummy); - for (i = 0; i < len; i += PAGE_SIZE) { + for (unsigned i = 0; i < len; i += PAGE_SIZE) { ret |= realtek_mst_i2c_spi_read_data(fd, REGISTER_ADDRESS, buf + i, min(len - i, PAGE_SIZE)); if (ret) @@ -352,7 +350,6 @@ static int realtek_mst_i2c_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) { - unsigned i; int ret = 0; if (start & 0xff) @@ -369,7 +366,7 @@ ret |= realtek_mst_i2c_spi_write_register(fd, 0x6D, 0x02); /* write opcode */ ret |= realtek_mst_i2c_spi_write_register(fd, 0x71, (PAGE_SIZE - 1)); /* fit len=256 */ - for (i = 0; i < len; i += PAGE_SIZE) { + for (unsigned i = 0; i < len; i += PAGE_SIZE) { uint16_t page_len = min(len - i, PAGE_SIZE); if (len - i < PAGE_SIZE) ret |= realtek_mst_i2c_spi_write_register(fd, 0x71, page_len-1); -- To view, visit https://review.coreboot.org/c/flashrom/+/47909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9d9d1bf01209a7840f7b3fa2c6f7592375a74330 Gerrit-Change-Number: 47909 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: lspcon_i2c_spi.c: Make consistent with std=c99
by Edward O'Callaghan (Code Review) Aug. 29, 2026

Aug. 29, 2026

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47910 ) Change subject: lspcon_i2c_spi.c: Make consistent with std=c99 ...................................................................... lspcon_i2c_spi.c: Make consistent with std=c99 Use 'modern' C to scope iterator declarations only to the loop constructs they are used in. BUG=none TEST=builds Change-Id: Id61f8416416d2f625d424760e00f94dc730105f4 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M lspcon_i2c_spi.c 1 file changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/10/47910/1 diff --git a/lspcon_i2c_spi.c b/lspcon_i2c_spi.c index 7b9f1c0..6ee2840 100644 --- a/lspcon_i2c_spi.c +++ b/lspcon_i2c_spi.c @@ -127,14 +127,13 @@ static int lspcon_i2c_spi_register_control(int fd, packet_t *packet) { - int i; int ret = lspcon_i2c_spi_write_register(fd, SWSPI_WDATA, packet->command); if (ret) return ret; /* Higher 4 bits are read size. */ int write_size = packet->data_size & 0x0f; - for (i = 0; i < write_size; ++i) { + for (unsigned i = 0; i < write_size; ++i) { ret |= lspcon_i2c_spi_write_register(fd, SWSPI_WDATA, packet->data[i]); } @@ -256,7 +255,6 @@ const unsigned char *writearr, unsigned char *readarr) { - unsigned int i; if (writecnt > 16 || readcnt > 16 || writecnt == 0) { msg_perr("%s: Invalid read/write count for send command.\n", __func__); @@ -285,7 +283,7 @@ if (ret) return ret; - for (i = 0; i < readcnt; ++i) { + for (unsigned i = 0; i < readcnt; ++i) { ret |= lspcon_i2c_spi_read_register(fd, SWSPI_RDATA, &readarr[i]); } @@ -340,7 +338,6 @@ static int lspcon_i2c_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { - unsigned int i; int ret = 0; if (start & 0xff) return default_spi_read(flash, buf, start, len); @@ -349,7 +346,7 @@ if (fd < 0) return SPI_GENERIC_ERROR; - for (i = 0; i < len; i += PAGE_SIZE) { + for (unsigned i = 0; i < len; i += PAGE_SIZE) { ret |= lspcon_i2c_spi_map_page(fd, start + i); ret |= lspcon_i2c_spi_read_data(fd, PAGE_ADDRESS, buf + i, min(len - i, PAGE_SIZE)); } -- To view, visit https://review.coreboot.org/c/flashrom/+/47910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id61f8416416d2f625d424760e00f94dc730105f4 Gerrit-Change-Number: 47910 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: sb600spi.c: add rev 0x51 to the leading comment block
by Idwer Vollering (Code Review) Aug. 29, 2026

Aug. 29, 2026

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48879 ) Change subject: sb600spi.c: add rev 0x51 to the leading comment block ...................................................................... sb600spi.c: add rev 0x51 to the leading comment block Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Change-Id: Ic74cff04f2d1fd92ad92aa37f71e5852f02d86a6 --- M sb600spi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/48879/1 diff --git a/sb600spi.c b/sb600spi.c index ef9da4b..b9560e2 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -127,7 +127,7 @@ * found on both Stoney Ridge and Zen platforms. * * The revisions I have found by searching various lspci - * outputs are as follows: 0x4b, 0x59 & 0x61. + * outputs are as follows: 0x4b, 0x51, 0x59 & 0x61. */ } else if (rev == 0x4b || rev == 0x51 || rev == 0x59 || rev == 0x61) { msg_pdbg("Promontory (rev 0x%02x) detected.\n", rev); -- To view, visit https://review.coreboot.org/c/flashrom/+/48879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic74cff04f2d1fd92ad92aa37f71e5852f02d86a6 Gerrit-Change-Number: 48879 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

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