October 2022 - flashrom-gerrit

[M] Change in flashrom[master]: tree/: Rename 'internal_delay()' to 'default_delay()'
by Edward O'Callaghan (Code Review) 26 Oct '22

26 Oct '22

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/68855 ) Change subject: tree/: Rename 'internal_delay()' to 'default_delay()' ...................................................................... tree/: Rename 'internal_delay()' to 'default_delay()' The non-custom driver programmer delay implementation 'internal_delay()' is unrelated specifically to the 'internal' programmer. The delay implementation is simply a platform-agnostic host delay implementation. Therefore, rename to simply default_delay(). Change-Id: I5e04adf16812ceb1480992c92bca25ed80f8897a Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M amd_imc.c M atavia.c M bitbang_spi.c M ch341a_spi.c M dediprog.c M dummyflasher.c M flashrom.c M ichspi.c M include/flash.h M include/programmer.h M it87spi.c M nicintel_eeprom.c M pony_spi.c M raiden_debug_spi.c M serial.c M serprog.c M udelay.c M wbsio_spi.c 18 files changed, 62 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/55/68855/1 diff --git a/amd_imc.c b/amd_imc.c index 2ee8332..093d42d 100644 --- a/amd_imc.c +++ b/amd_imc.c @@ -60,7 +60,7 @@ msg_pwarn("IMC MBOX: Timeout!\n"); return 1; } - internal_delay(1000); + default_delay(1000); } return 0; } diff --git a/atavia.c b/atavia.c index 33f6067..13c21de 100644 --- a/atavia.c +++ b/atavia.c @@ -90,7 +90,7 @@ ready = true; break; } else { - internal_delay(1); + default_delay(1); continue; } } @@ -170,7 +170,7 @@ /* Test if a flash chip is attached. */ pci_write_long(dev, PCI_ROM_ADDRESS, (uint32_t)PCI_ROM_ADDRESS_MASK); - internal_delay(90); + default_delay(90); uint32_t base = pci_read_long(dev, PCI_ROM_ADDRESS); msg_pdbg2("BROM base=0x%08x\n", base); if ((base & PCI_ROM_ADDRESS_MASK) == 0) { diff --git a/bitbang_spi.c b/bitbang_spi.c index bd7bf1a..0b0bf8a 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -76,10 +76,10 @@ bitbang_spi_set_sck_set_mosi(master, 0, 0, spi_data); else bitbang_spi_set_sck(master, 0, spi_data); - internal_delay(master->half_period); + default_delay(master->half_period); ret <<= 1; ret |= bitbang_spi_set_sck_get_miso(master, 1, spi_data); - internal_delay(master->half_period); + default_delay(master->half_period); } return ret; } @@ -90,9 +90,9 @@ for (i = 7; i >= 0; i--) { bitbang_spi_set_sck_set_mosi(master, 0, (val >> i) & 1, spi_data); - internal_delay(master->half_period); + default_delay(master->half_period); bitbang_spi_set_sck(master, 1, spi_data); - internal_delay(master->half_period); + default_delay(master->half_period); } } @@ -122,9 +122,9 @@ readarr[i] = bitbang_spi_read_byte(master, data->spi_data); bitbang_spi_set_sck(master, 0, data->spi_data); - internal_delay(master->half_period); + default_delay(master->half_period); bitbang_spi_set_cs(master, 1, data->spi_data); - internal_delay(master->half_period); + default_delay(master->half_period); /* FIXME: Run bitbang_spi_release_bus here or in programmer init? */ bitbang_spi_release_bus(master, data->spi_data); diff --git a/ch341a_spi.c b/ch341a_spi.c index d42ffe1..558bb32 100644 --- a/ch341a_spi.c +++ b/ch341a_spi.c @@ -326,10 +326,10 @@ { /* There is space for 28 bytes instructions of 750 ns each in the CS packet (32 - 4 for the actual CS * instructions), thus max 21 us, but we avoid getting too near to this boundary and use - * internal_delay() for durations over 20 us. */ + * default_delay() for durations over 20 us. */ if ((usecs + stored_delay_us) > 20) { unsigned int inc = 20 - stored_delay_us; - internal_delay(usecs - inc); + default_delay(usecs - inc); usecs = inc; } stored_delay_us += usecs; diff --git a/dediprog.c b/dediprog.c index 6c41f28..723f4a8 100644 --- a/dediprog.c +++ b/dediprog.c @@ -316,7 +316,7 @@ if (voltage_selector == 0) { /* Wait some time as the original driver does. */ - internal_delay(200 * 1000); + default_delay(200 * 1000); } ret = dediprog_write(dediprog_handle, CMD_SET_VCC, voltage_selector, 0, NULL, 0); if (ret != 0x0) { @@ -326,7 +326,7 @@ } if (voltage_selector != 0) { /* Wait some time as the original driver does. */ - internal_delay(200 * 1000); + default_delay(200 * 1000); } return 0; } diff --git a/dummyflasher.c b/dummyflasher.c index 8a3f089..3dd3072 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -897,7 +897,7 @@ msg_pspew(" 0x%02x", readarr[i]); msg_pspew("\n"); - internal_delay((writecnt + readcnt) * emu_data->delay_us); + default_delay((writecnt + readcnt) * emu_data->delay_us); return 0; } diff --git a/flashrom.c b/flashrom.c index 3218d9e..38ecb6d 100644 --- a/flashrom.c +++ b/flashrom.c @@ -259,18 +259,18 @@ return; /** - * Drivers should either use internal_delay() directly or their + * Drivers should either use default_delay() directly or their * own custom delay. Only core flashrom logic calls programmer_delay() * which should always have a valid flash context. A NULL context * more than likely indicates a layering violation or BUG however - * for now dispatch a internal_delay() as a safe default for the NULL + * for now dispatch a default_delay() as a safe default for the NULL * base case. */ if (!flash) { msg_perr("%s called with NULL flash context. " "Please report a bug at flashrom(a)flashrom.org\n", __func__); - return internal_delay(usecs); + return default_delay(usecs); } if (flash->mst->buses_supported & BUS_SPI) { @@ -280,7 +280,7 @@ if (flash->mst->par.delay) flash->mst->par.delay(usecs); } else - internal_delay(usecs); + default_delay(usecs); } int read_memmapped(struct flashctx *flash, uint8_t *buf, unsigned int start, diff --git a/ichspi.c b/ichspi.c index 14c0dd8..fcd54c5 100644 --- a/ichspi.c +++ b/ichspi.c @@ -875,7 +875,7 @@ timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) { - internal_delay(10); + default_delay(10); } if (!timeout) { msg_perr("Error: SCIP never cleared!\n"); @@ -951,7 +951,7 @@ /* Wait for Cycle Done Status or Flash Cycle Error. */ while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) && --timeout) { - internal_delay(10); + default_delay(10); } if (!timeout) { msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n", REGREAD16(ICH7_REG_SPIS)); @@ -991,7 +991,7 @@ timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ while ((REGREAD8(swseq_data.reg_ssfsc) & SSFS_SCIP) && --timeout) { - internal_delay(10); + default_delay(10); } if (!timeout) { msg_perr("Error: SCIP never cleared!\n"); @@ -1071,7 +1071,7 @@ /* Wait for Cycle Done Status or Flash Cycle Error. */ while (((REGREAD32(swseq_data.reg_ssfsc) & (SSFS_FDONE | SSFS_FCERR)) == 0) && --timeout) { - internal_delay(10); + default_delay(10); } if (!timeout) { msg_perr("timeout, REG_SSFS=0x%08x\n", REGREAD32(swseq_data.reg_ssfsc)); @@ -1319,7 +1319,7 @@ while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & (HSFS_FDONE | HSFS_FCERR)) == 0) && --timeout_us) { - internal_delay(8); + default_delay(8); } REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); if (!timeout_us) { diff --git a/include/flash.h b/include/flash.h index 633601d..6a0782a 100644 --- a/include/flash.h +++ b/include/flash.h @@ -60,7 +60,7 @@ const char *descr, uintptr_t phys_addr, size_t len); void master_unmap_flash_region(const struct registered_master *mast, void *virt_addr, size_t len); -/* NOTE: flashctx is not used in internal_delay. In this case, a context should be NULL. */ +/* NOTE: flashctx is not used in default_delay. In this case, a context should be NULL. */ void programmer_delay(const struct flashrom_flashctx *flash, unsigned int usecs); #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) diff --git a/include/programmer.h b/include/programmer.h index b379cf6..1ff93c9 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -210,7 +210,7 @@ void myusec_delay(unsigned int usecs); void myusec_calibrate_delay(void); void internal_sleep(unsigned int usecs); -void internal_delay(unsigned int usecs); +void default_delay(unsigned int usecs); #if CONFIG_INTERNAL == 1 /* board_enable.c */ diff --git a/it87spi.c b/it87spi.c index fc29e51..34dbea0 100644 --- a/it87spi.c +++ b/it87spi.c @@ -146,7 +146,7 @@ if((status & SPI_SR_WIP) == 0) return 0; - internal_delay(1000); + default_delay(1000); } return 0; } diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index 3078684..db7a6b5 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -213,7 +213,7 @@ eewr |= BIT(EEWR_CMDV); pci_mmio_writel(eewr, eebar + EEWR); - internal_delay(5); + default_delay(5); int i; for (i = 0; i < MAX_ATTEMPTS; i++) if (pci_mmio_readl(eebar + EEWR) & BIT(EEWR_DONE)) @@ -338,7 +338,7 @@ nicintel_ee_bitbang(eebar, 0x00, &rdsr); nicintel_ee_bitset(eebar, EEC, EE_CS, 1); - internal_delay(1); + default_delay(1); if (!(rdsr & SPI_SR_WIP)) { return 0; } @@ -379,7 +379,7 @@ nicintel_ee_bitset(eebar, EEC, EE_CS, 0); nicintel_ee_bitbang(eebar, JEDEC_WREN, NULL); nicintel_ee_bitset(eebar, EEC, EE_CS, 1); - internal_delay(1); + default_delay(1); /* data */ nicintel_ee_bitset(eebar, EEC, EE_CS, 0); @@ -394,7 +394,7 @@ break; } nicintel_ee_bitset(eebar, EEC, EE_CS, 1); - internal_delay(1); + default_delay(1); if (nicintel_ee_ready(eebar)) goto out; } diff --git a/pony_spi.c b/pony_spi.c index 408fa12..0647f91 100644 --- a/pony_spi.c +++ b/pony_spi.c @@ -244,7 +244,7 @@ for (i = 1; i <= 10; i++) { data_out = i & 1; sp_set_pin(PIN_RTS, data_out); - internal_delay(1000); + default_delay(1000); /* If DSR does not change, we are not connected to what we think */ if (data_out != sp_get_pin(PIN_DSR)) { diff --git a/raiden_debug_spi.c b/raiden_debug_spi.c index 2478133..8260abd 100644 --- a/raiden_debug_spi.c +++ b/raiden_debug_spi.c @@ -892,7 +892,7 @@ /* Reattempting will not result in a recovery. */ return status; } - internal_delay(RETRY_INTERVAL_US); + default_delay(RETRY_INTERVAL_US); continue; } @@ -927,7 +927,7 @@ /* Reattempting will not result in a recovery. */ return status; } - internal_delay(RETRY_INTERVAL_US); + default_delay(RETRY_INTERVAL_US); } } @@ -962,7 +962,7 @@ " config attempt = %d\n" " status = 0x%05x\n", config_attempt + 1, status); - internal_delay(RETRY_INTERVAL_US); + default_delay(RETRY_INTERVAL_US); continue; } @@ -972,7 +972,7 @@ " config attempt = %d\n" " status = 0x%05x\n", config_attempt + 1, status); - internal_delay(RETRY_INTERVAL_US); + default_delay(RETRY_INTERVAL_US); continue; } @@ -1016,7 +1016,7 @@ config_attempt + 1, rsp_config.packet_v2.packet_id, rsp_config.packet_size); - internal_delay(RETRY_INTERVAL_US); + default_delay(RETRY_INTERVAL_US); } return USB_SPI_HOST_INIT_FAILURE; } @@ -1240,7 +1240,7 @@ /* Reattempting will not result in a recovery. */ return status; } - internal_delay(RETRY_INTERVAL_US); + default_delay(RETRY_INTERVAL_US); continue; } for (read_attempt = 0; read_attempt < READ_RETRY_ATTEMPTS; @@ -1277,7 +1277,7 @@ } /* Device needs to reset its transmit index. */ restart_response_v2(ctx_data); - internal_delay(RETRY_INTERVAL_US); + default_delay(RETRY_INTERVAL_US); } } } diff --git a/serial.c b/serial.c index 72f9ef6..a0ef632 100644 --- a/serial.c +++ b/serial.c @@ -403,7 +403,7 @@ if (!tmp) { msg_pdbg2("Empty write\n"); empty_writes--; - internal_delay(500); + default_delay(500); if (empty_writes == 0) { msg_perr("Serial port is unresponsive!\n"); return 1; @@ -510,7 +510,7 @@ ret = 0; break; } - internal_delay(1000); /* 1ms units */ + default_delay(1000); /* 1ms units */ } if (really_read != NULL) *really_read = rd_bytes; @@ -596,7 +596,7 @@ break; } } - internal_delay(1000); /* 1ms units */ + default_delay(1000); /* 1ms units */ } if (really_wrote != NULL) *really_wrote = wr_bytes; diff --git a/serprog.c b/serprog.c index 259fee0..dd40ae3 100644 --- a/serprog.c +++ b/serprog.c @@ -157,7 +157,7 @@ goto err_out; } /* A second should be enough to get all the answers to the buffer */ - internal_delay(1000 * 1000); + default_delay(1000 * 1000); sp_flush_incoming(); /* Then try up to 8 times to send syncnop and get the correct special * @@ -577,7 +577,7 @@ msg_pspew("%s usecs=%d\n", __func__, usecs); if (!sp_check_commandavail(S_CMD_O_DELAY)) { msg_pdbg2("serprog_delay used, but programmer doesn't support delays natively - emulating\n"); - internal_delay(usecs); + default_delay(usecs); return; } if ((sp_max_write_n) && (sp_write_n_bytes)) diff --git a/udelay.c b/udelay.c index 6c0efc4..82ddcbd 100644 --- a/udelay.c +++ b/udelay.c @@ -235,7 +235,7 @@ } /* Precise delay. */ -void internal_delay(unsigned int usecs) +void default_delay(unsigned int usecs) { /* If the delay is >1 s, use internal_sleep because timing does not need to be so precise. */ if (usecs > 1000000) { @@ -255,7 +255,7 @@ get_cpu_speed(); } -void internal_delay(unsigned int usecs) +void default_delay(unsigned int usecs) { udelay(usecs); } diff --git a/wbsio_spi.c b/wbsio_spi.c index b643eb4..d635a09 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -155,7 +155,7 @@ OUTB(writearr[0], data->spibase); OUTB(mode, data->spibase + 1); - internal_delay(10); + default_delay(10); if (!readcnt) return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/68855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5e04adf16812ceb1480992c92bca25ed80f8897a Gerrit-Change-Number: 68855 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in flashrom[master]: flashchips: add support for MX77L25650F chip
by Artur Kowalski (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Felix Singer. Artur Kowalski has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/68557 ) Change subject: flashchips: add support for MX77L25650F chip ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/68557/comment/31f3f490_070f114a PS1, Line 7: flashrom > flashchips fixed https://review.coreboot.org/c/flashrom/+/68557/comment/8e293850_de30f7d3 PS1, Line 9: read and write > What about erasing? Erasing was done before writing and it worked properly, updated commit message accordingly File flashchips.c: https://review.coreboot.org/c/flashrom/+/68557/comment/26a2d324_26f4766a PS1, Line 10215: // TODO: add 64K block erase > What about this todo? We haven't tested 64K erase so I didn't add it here. -- To view, visit https://review.coreboot.org/c/flashrom/+/68557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iaea5485f8b59b8538dc47beada2c308376ea027c Gerrit-Change-Number: 68557 Gerrit-PatchSet: 3 Gerrit-Owner: Artur Kowalski <artur.kowalski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Tue, 25 Oct 2022 10:28:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashchips: add support for MX77L25650F chip
by Artur Kowalski (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Artur Kowalski. Hello build bot (Jenkins), Maciej Pijanowski, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/68557 to look at the new patch set (#2). Change subject: flashchips: add support for MX77L25650F chip ...................................................................... flashchips: add support for MX77L25650F chip Add basic support Macronix MX77L25650F. Can read, write and erase the chip as long as write protection is not enabled (WP is not supported at the moment so can't disable it). Change-Id: Iaea5485f8b59b8538dc47beada2c308376ea027c Signed-off-by: Artur Kowalski <artur.kowalski(a)3mdeb.com> --- M flashchips.c M include/flashchips.h 2 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/57/68557/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/68557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iaea5485f8b59b8538dc47beada2c308376ea027c Gerrit-Change-Number: 68557 Gerrit-PatchSet: 2 Gerrit-Owner: Artur Kowalski <artur.kowalski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Artur Kowalski <artur.kowalski(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[master]: flashrom_tester: Use Path type for test data
by Evan Benn (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Angel Pons, Peter Marheine. Hello build bot (Jenkins), Angel Pons, Peter Marheine, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/68643 to look at the new patch set (#3). Change subject: flashrom_tester: Use Path type for test data ...................................................................... flashrom_tester: Use Path type for test data Update many str types to Path. BUG=b:243460685 BRANCH=None TEST=/usr/bin/flashrom_tester --flashrom_binary /usr/sbin/flashrom host Change-Id: I4a0b25c8c70fa6dfd682fba3db7d3bf06b2eb7ac Signed-off-by: Evan Benn <evanbenn(a)chromium.org> --- M util/flashrom_tester/flashrom/src/cmd.rs M util/flashrom_tester/flashrom/src/flashromlib.rs M util/flashrom_tester/flashrom/src/lib.rs M util/flashrom_tester/src/rand_util.rs M util/flashrom_tester/src/tester.rs M util/flashrom_tester/src/tests.rs 6 files changed, 127 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/43/68643/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/68643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4a0b25c8c70fa6dfd682fba3db7d3bf06b2eb7ac Gerrit-Change-Number: 68643 Gerrit-PatchSet: 3 Gerrit-Owner: Evan Benn <evanbenn(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in flashrom[master]: include/flash.h: Turn defines into a flashrom error enum type
by Edward O'Callaghan (Code Review) 25 Oct '22

25 Oct '22

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/68778 ) Change subject: include/flash.h: Turn defines into a flashrom error enum type ...................................................................... include/flash.h: Turn defines into a flashrom error enum type Change-Id: I6d0e6626b15ce54672a560741a1f1b3d3c2a3ab1 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M include/flash.h 1 file changed, 23 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/68778/1 diff --git a/include/flash.h b/include/flash.h index 8ee603d..d7fa3b4 100644 --- a/include/flash.h +++ b/include/flash.h @@ -436,18 +436,20 @@ void finalize_flash_access(struct flashctx *); int register_chip_restore(chip_restore_fn_cb_t func, struct flashctx *flash, uint8_t status); -/* Something happened that shouldn't happen, but we can go on. */ -#define ERROR_FLASHROM_NONFATAL 0x100 +typedef enum { + /* Something happened that shouldn't happen, but we can go on. */ + ERROR_FLASHROM_NONFATAL = 0x100, + /* Something happened that shouldn't happen, we'll abort. */ + ERROR_FLASHROM_FATAL = -0xee, -/* Something happened that shouldn't happen, we'll abort. */ -#define ERROR_FLASHROM_FATAL -0xee -#define ERROR_FLASHROM_BUG -200 -/* We reached one of the hardcoded limits of flashrom. This can be fixed by - * increasing the limit of a compile-time allocation or by switching to dynamic - * allocation. - * Note: If this warning is triggered, check first for runaway registrations. - */ -#define ERROR_FLASHROM_LIMIT -201 + ERROR_FLASHROM_BUG = -200, + /* We reached one of the hardcoded limits of flashrom. This can be fixed by + * increasing the limit of a compile-time allocation or by switching to dynamic + * allocation. + * Note: If this warning is triggered, check first for runaway registrations. + */ + ERROR_FLASHROM_LIMIT = -201, +} flashrom_error_t; /* cli_common.c */ void print_chip_support_status(const struct flashchip *chip); -- To view, visit https://review.coreboot.org/c/flashrom/+/68778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6d0e6626b15ce54672a560741a1f1b3d3c2a3ab1 Gerrit-Change-Number: 68778 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in flashrom[master]: tree/: Rename ERROR_NONFATAL to ERROR_FLASHROM_NONFATAL
by Edward O'Callaghan (Code Review) 25 Oct '22

25 Oct '22

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/68777 ) Change subject: tree/: Rename ERROR_NONFATAL to ERROR_FLASHROM_NONFATAL ...................................................................... tree/: Rename ERROR_NONFATAL to ERROR_FLASHROM_NONFATAL Change-Id: I5c30fec0cebab2b7d10e2789761889abc3a14dd3 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M chipset_enable.c M include/flash.h M sb600spi.c 3 files changed, 23 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/68777/1 diff --git a/chipset_enable.c b/chipset_enable.c index e2838a5..d8ed3ce 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -822,7 +822,7 @@ return ret_spi; if (((boot_buses & BUS_FWH) && ret_fwh) || ((boot_buses & BUS_SPI) && ret_spi)) - return ERROR_NONFATAL; + return ERROR_FLASHROM_NONFATAL; /* Suppress unknown laptop warning if we booted from SPI. */ if (boot_buses & BUS_SPI) @@ -964,7 +964,7 @@ const int ret_spi = ich_init_spi(cfg, spibar, pch_generation); if (ret_spi != ERROR_FLASHROM_FATAL) { if (ret_bc || ret_spi) - ret = ERROR_NONFATAL; + ret = ERROR_FLASHROM_NONFATAL; else ret = 0; } @@ -1083,7 +1083,7 @@ return ret_spi; if (((boot_buses & BUS_FWH) && ret_fwh) || ((boot_buses & BUS_SPI) && ret_spi)) - return ERROR_NONFATAL; + return ERROR_FLASHROM_NONFATAL; /* Suppress unknown laptop warning if we booted from SPI. */ if (boot_buses & BUS_SPI) @@ -1346,7 +1346,7 @@ if (pci_read_byte(dev, AMD_ENREG) != new) { msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", AMD_ENREG, new, name); - return ERROR_NONFATAL; + return ERROR_FLASHROM_NONFATAL; } msg_pdbg2("Set ROM enable bit successfully.\n"); @@ -1470,7 +1470,7 @@ { rpci_write_byte(dev, 0x92, 0); if (enable_flash_nvidia_common(cfg, dev, name)) - return ERROR_NONFATAL; + return ERROR_FLASHROM_NONFATAL; else return 0; } @@ -1545,7 +1545,7 @@ err++; if (err > 0) - return ERROR_NONFATAL; + return ERROR_FLASHROM_NONFATAL; else return 0; } @@ -1620,7 +1620,7 @@ rpci_write_word(dev, 0x90, wordval); if (enable_flash_nvidia_common(cfg, dev, name)) - return ERROR_NONFATAL; + return ERROR_FLASHROM_NONFATAL; else return 0; } @@ -1661,7 +1661,7 @@ msg_pinfo("Please send the log files created by \"flashrom -p internal -o logfile\" to\n" "flashrom(a)flashrom.org with \"your board name: flashrom -V\" as the subject to\n" "help us finish support for your chipset. Thanks.\n"); - return ERROR_NONFATAL; + return ERROR_FLASHROM_NONFATAL; } /* Force enable SPI and disable LPC? Not a good idea. */ @@ -2240,7 +2240,7 @@ msg_pinfo("FAILED!\n"); else if (ret == 0) msg_pinfo("OK.\n"); - else if (ret == ERROR_NONFATAL) + else if (ret == ERROR_FLASHROM_NONFATAL) msg_pinfo("PROBLEMS, continuing anyway\n"); if (ret == ERROR_FLASHROM_FATAL) { msg_perr("FATAL ERROR!\n"); diff --git a/include/flash.h b/include/flash.h index 7f59274..8ee603d 100644 --- a/include/flash.h +++ b/include/flash.h @@ -437,7 +437,7 @@ int register_chip_restore(chip_restore_fn_cb_t func, struct flashctx *flash, uint8_t status); /* Something happened that shouldn't happen, but we can go on. */ -#define ERROR_NONFATAL 0x100 +#define ERROR_FLASHROM_NONFATAL 0x100 /* Something happened that shouldn't happen, we'll abort. */ #define ERROR_FLASHROM_FATAL -0xee diff --git a/sb600spi.c b/sb600spi.c index 68a5690..8c018a3 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -665,7 +665,7 @@ enum amd_chipset amd_gen = determine_generation(dev); if (amd_gen == CHIPSET_AMD_UNKNOWN) - return ERROR_NONFATAL; + return ERROR_FLASHROM_NONFATAL; /* How to read the following table and similar ones in this file: * "?" means we have no datasheet for this chipset generation or it doesn't have any relevant info. @@ -748,7 +748,7 @@ if (((tmp >> 22) & 0x1) == 0 || ((tmp >> 23) & 0x1) == 0) { msg_perr("ERROR: State of SpiAccessMacRomEn or SpiHostAccessRomEn prohibits full access.\n"); - return ERROR_NONFATAL; + return ERROR_FLASHROM_NONFATAL; } if (amd_gen >= CHIPSET_SB89XX) { @@ -765,7 +765,7 @@ smbus_dev = pcidev_find(0x1022, 0x790b); /* AMD FP4 */ if (!smbus_dev) { msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); - return ERROR_NONFATAL; + return ERROR_FLASHROM_NONFATAL; } /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ -- To view, visit https://review.coreboot.org/c/flashrom/+/68777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5c30fec0cebab2b7d10e2789761889abc3a14dd3 Gerrit-Change-Number: 68777 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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[M] Change in flashrom[master]: tree/: Rename ERROR_FATAL to ERROR_FLASHROM_FATAL
by Edward O'Callaghan (Code Review) 25 Oct '22

25 Oct '22

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/68776 ) Change subject: tree/: Rename ERROR_FATAL to ERROR_FLASHROM_FATAL ...................................................................... tree/: Rename ERROR_FATAL to ERROR_FLASHROM_FATAL Change-Id: I51ee789f9a1443bfff1e3c85c9b40b5023db6062 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M atavia.c M bitbang_spi.c M chipset_enable.c M flashrom.c M ichspi.c M include/flash.h M internal.c M sb600spi.c M tests/dummyflasher.c 9 files changed, 52 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/76/68776/1 diff --git a/atavia.c b/atavia.c index b392999..1eebc97 100644 --- a/atavia.c +++ b/atavia.c @@ -151,14 +151,14 @@ if (strlen(arg) == 0) { msg_perr("Missing argument for offset.\n"); free(arg); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } char *endptr; atavia_offset = (void *)strtoul(arg, &endptr, 0); if (*endptr) { msg_perr("Error: Invalid offset specified: \"%s\".\n", arg); free(arg); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } msg_pinfo("Mapping addresses to base %p.\n", atavia_offset); } diff --git a/bitbang_spi.c b/bitbang_spi.c index 5e4b566..f7ded1f 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -166,7 +166,7 @@ struct bitbang_spi_master_data *data = calloc(1, sizeof(*data)); if (!data) - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; data->master = master; if (spi_data) diff --git a/chipset_enable.c b/chipset_enable.c index d6103c1..e2838a5 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -275,7 +275,7 @@ switch (ich_generation) { case CHIPSET_ICH_UNKNOWN: - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; /* Non-SPI-capable */ case CHIPSET_ICH: case CHIPSET_ICH2345: @@ -409,7 +409,7 @@ uint32_t ilb_base = pci_read_long(dev, 0x50) & 0xfffffe00; /* bits 31:9 */ if (ilb_base == 0) { msg_perr("Error: Invalid ILB_BASE_ADDRESS\n"); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } ilb = rphysmap("BYT IBASE", ilb_base, 512); fwh_sel1 = 0x18; @@ -468,7 +468,7 @@ msg_perr("Error: fwh_idsel= specified, but no value given.\n"); idsel_garbage_out: free(idsel); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } free(idsel); @@ -779,13 +779,13 @@ /* Map RCBA to virtual memory */ void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000); if (rcrb == ERROR_PTR) - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb); /* Handle FWH-related parameters and initialization */ int ret_fwh = enable_flash_ich_fwh(cfg, dev, ich_generation, bios_cntl); - if (ret_fwh == ERROR_FATAL) + if (ret_fwh == ERROR_FLASHROM_FATAL) return ret_fwh; /* @@ -801,7 +801,7 @@ switch (ich_generation) { case CHIPSET_BAYTRAIL: case CHIPSET_ICH_UNKNOWN: - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; case CHIPSET_ICH7: case CHIPSET_ICH8: case CHIPSET_TUNNEL_CREEK: @@ -818,7 +818,7 @@ /* This adds BUS_SPI */ int ret_spi = ich_init_spi(cfg, spibar, ich_generation); - if (ret_spi == ERROR_FATAL) + if (ret_spi == ERROR_FLASHROM_FATAL) return ret_spi; if (((boot_buses & BUS_FWH) && ret_fwh) || ((boot_buses & BUS_SPI) && ret_spi)) @@ -920,7 +920,7 @@ struct pci_dev *const dev, const char *const name, const int slot, const int func, const enum ich_chipset pch_generation) { - int ret = ERROR_FATAL; + int ret = ERROR_FLASHROM_FATAL; /* * The SPI PCI device is usually hidden (by hiding PCI vendor @@ -951,7 +951,7 @@ const enum chipbustype boot_buses = enable_flash_ich_report_gcs(spi_dev, pch_generation, NULL); const int ret_bc = enable_flash_ich_bios_cntl_config_space(spi_dev, pch_generation, 0xdc); - if (ret_bc == ERROR_FATAL) + if (ret_bc == ERROR_FLASHROM_FATAL) goto _freepci_ret; const uint32_t phys_spibar = pci_read_long(spi_dev, PCI_BASE_ADDRESS_0) & 0xfffff000; @@ -962,7 +962,7 @@ /* This adds BUS_SPI */ const int ret_spi = ich_init_spi(cfg, spibar, pch_generation); - if (ret_spi != ERROR_FATAL) { + if (ret_spi != ERROR_FLASHROM_FATAL) { if (ret_bc || ret_spi) ret = ERROR_NONFATAL; else @@ -1055,13 +1055,13 @@ /* Handle GCS (in RCRB) */ void *rcrb = physmap("BYT RCRB", rcba, 4); if (rcrb == ERROR_PTR) - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb); physunmap(rcrb, 4); /* Handle fwh_idsel parameter */ int ret_fwh = enable_flash_ich_fwh_decode(cfg, dev, ich_generation); - if (ret_fwh == ERROR_FATAL) + if (ret_fwh == ERROR_FLASHROM_FATAL) return ret_fwh; internal_buses_supported &= BUS_FWH; @@ -1071,7 +1071,7 @@ msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase); void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */ if (spibar == ERROR_PTR) - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; /* Enable Flash Writes. * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C). @@ -1079,7 +1079,7 @@ enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC); int ret_spi = ich_init_spi(cfg, spibar, ich_generation); - if (ret_spi == ERROR_FATAL) + if (ret_spi == ERROR_FLASHROM_FATAL) return ret_spi; if (((boot_buses & BUS_FWH) && ret_fwh) || ((boot_buses & BUS_SPI) && ret_spi)) @@ -1137,7 +1137,7 @@ struct pci_dev *south_north = pcidev_find(0x1106, 0xa353); if (south_north == NULL) { msg_perr("Could not find South-North Module Interface Control device!\n"); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } msg_pdbg("Strapped to "); @@ -1157,7 +1157,7 @@ spi0_mm_base = pci_read_long(dev, 0xbc) << 8; if (spi0_mm_base == 0x0) { msg_pdbg ("MMIO not enabled!\n"); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } break; case 0x8409: /* VX855/VX875 */ @@ -1165,18 +1165,18 @@ mmio_base = pci_read_long(dev, 0xbc) << 8; if (mmio_base == 0x0) { msg_pdbg ("MMIO not enabled!\n"); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN); if (mmio_base_physmapped == ERROR_PTR) - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; /* Offset 0 - Bit 0 holds SPI Bus0 Enable Bit. */ spi_cntl = mmio_readl(mmio_base_physmapped) + 0x00; if ((spi_cntl & 0x01) == 0) { msg_pdbg ("SPI Bus0 disabled!\n"); physunmap(mmio_base_physmapped, SPI_CNTL_LEN); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } /* Offset 1-3 has SPI Bus Memory Map Base Address: */ spi0_mm_base = spi_cntl & 0xFFFFFF00; @@ -1190,7 +1190,7 @@ break; default: msg_perr("%s: Unsupported chipset %x:%x!\n", __func__, dev->vendor_id, dev->device_id); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } return via_init_spi(spi0_mm_base); @@ -1578,7 +1578,7 @@ if (!smbusdev) { msg_perr("ERROR: SMBus device not found. Aborting.\n"); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } /* Enable some SMBus stuff. */ @@ -1713,7 +1713,7 @@ /* 1. Map MMCR */ mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize()); if (mmcr == ERROR_PTR) - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for * BOOTCS region (PARx[31:29] = 100b)e @@ -2216,7 +2216,7 @@ if (chipset_enables[i].status == BAD) { msg_perr("ERROR: This chipset is not supported yet.\n"); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } if (chipset_enables[i].status == NT) { msg_pinfo("This chipset is marked as untested. If " @@ -2242,7 +2242,7 @@ msg_pinfo("OK.\n"); else if (ret == ERROR_NONFATAL) msg_pinfo("PROBLEMS, continuing anyway\n"); - if (ret == ERROR_FATAL) { + if (ret == ERROR_FLASHROM_FATAL) { msg_perr("FATAL ERROR!\n"); return ret; } diff --git a/flashrom.c b/flashrom.c index 624c463..af57a95 100644 --- a/flashrom.c +++ b/flashrom.c @@ -155,7 +155,7 @@ cfg.params = strdup(param); if (!cfg.params) { msg_perr("Out of memory!\n"); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } } else { cfg.params = NULL; @@ -176,7 +176,7 @@ */ msg_perr("Unhandled programmer parameters: %s\n", cfg.params); msg_perr("Aborting.\n"); - ret = ERROR_FATAL; + ret = ERROR_FLASHROM_FATAL; } } free(cfg.params); diff --git a/ichspi.c b/ichspi.c index 6d3535c..f5d9352 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1859,11 +1859,11 @@ } else if (!strlen(arg)) { msg_perr("Missing argument for ich_spi_mode.\n"); free(arg); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } else { msg_perr("Unknown argument for ich_spi_mode: %s\n", arg); free(arg); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } free(arg); @@ -2157,20 +2157,20 @@ if (!desc_valid) { msg_perr("Hardware sequencing was requested " "but the flash descriptor is not valid. Aborting.\n"); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } int tmpi = getFCBA_component_density(ich_gen, &desc, 0); if (tmpi < 0) { msg_perr("Could not determine density of flash component %d.\n", 0); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } g_hwseq_data.size_comp0 = tmpi; tmpi = getFCBA_component_density(ich_gen, &desc, 1); if (tmpi < 0) { msg_perr("Could not determine density of flash component %d.\n", 1); - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; } g_hwseq_data.size_comp1 = tmpi; @@ -2217,7 +2217,7 @@ ich_spibar = rphysmap("VIA SPI MMIO registers", mmio_base, 0x70); if (ich_spibar == ERROR_PTR) - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; /* Do we really need no write enable? Like the LPC one at D17F0 0x40 */ /* Not sure if it speaks all these bus protocols. */ diff --git a/include/flash.h b/include/flash.h index 633601d..7f59274 100644 --- a/include/flash.h +++ b/include/flash.h @@ -440,7 +440,7 @@ #define ERROR_NONFATAL 0x100 /* Something happened that shouldn't happen, we'll abort. */ -#define ERROR_FATAL -0xee +#define ERROR_FLASHROM_FATAL -0xee #define ERROR_FLASHROM_BUG -200 /* We reached one of the hardcoded limits of flashrom. This can be fixed by * increasing the limit of a compile-time allocation or by switching to dynamic diff --git a/internal.c b/internal.c index 8c834e2..4f68456 100644 --- a/internal.c +++ b/internal.c @@ -289,7 +289,7 @@ if (ret == -2) { msg_perr("WARNING: No chipset found. Flash detection " "will most likely fail.\n"); - } else if (ret == ERROR_FATAL) { + } else if (ret == ERROR_FLASHROM_FATAL) { goto internal_init_exit; } diff --git a/sb600spi.c b/sb600spi.c index 6020145..68a5690 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -656,7 +656,7 @@ /* Physical memory has to be mapped at page (4k) boundaries. */ sb600_spibar = rphysmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); if (sb600_spibar == ERROR_PTR) - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; /* The low bits of the SPI base address are used as offset into * the mapped page. @@ -798,10 +798,10 @@ } if (handle_speed(cfg, dev, amd_gen, sb600_spibar) != 0) - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; if (handle_imc(cfg, dev, amd_gen) != 0) - return ERROR_FATAL; + return ERROR_FLASHROM_FATAL; struct sb600spi_data *data = calloc(1, sizeof(*data)); if (!data) { diff --git a/tests/dummyflasher.c b/tests/dummyflasher.c index 1148217..c41f9df 100644 --- a/tests/dummyflasher.c +++ b/tests/dummyflasher.c @@ -88,7 +88,7 @@ * is successful, due to invalid param at the end of param string. */ run_init_error_path(state, &dummy_io, &programmer_dummy, - "bus=spi,emulate=W25Q128FV,invalid=value", ERROR_FATAL); + "bus=spi,emulate=W25Q128FV,invalid=value", ERROR_FLASHROM_FATAL); } void dummy_init_success_unhandled_param_test_success(void **state) @@ -107,7 +107,7 @@ * Unhandled param `voltage` is not used for dummyflasher. */ run_init_error_path(state, &dummy_io, &programmer_dummy, - "bus=spi,emulate=W25Q128FV,voltage=3.5V", ERROR_FATAL); + "bus=spi,emulate=W25Q128FV,voltage=3.5V", ERROR_FLASHROM_FATAL); } void dummy_null_prog_param_test_success(void **state) -- To view, visit https://review.coreboot.org/c/flashrom/+/68776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I51ee789f9a1443bfff1e3c85c9b40b5023db6062 Gerrit-Change-Number: 68776 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in flashrom[master]: bitbang_spi.c: Fix unchecked heap allocation
by Edward O'Callaghan (Code Review) 25 Oct '22

25 Oct '22

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/68775 ) Change subject: bitbang_spi.c: Fix unchecked heap allocation ...................................................................... bitbang_spi.c: Fix unchecked heap allocation Change-Id: Ib64b1fe67fa1874875453ab9e1700e468c579e7c Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M bitbang_spi.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/75/68775/1 diff --git a/bitbang_spi.c b/bitbang_spi.c index 10c1087..5e4b566 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -165,6 +165,9 @@ } struct bitbang_spi_master_data *data = calloc(1, sizeof(*data)); + if (!data) + return ERROR_FATAL; + data->master = master; if (spi_data) data->spi_data = spi_data; -- To view, visit https://review.coreboot.org/c/flashrom/+/68775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib64b1fe67fa1874875453ab9e1700e468c579e7c Gerrit-Change-Number: 68775 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in flashrom[master]: ichspi.c: heap allocate hwseq_data to remove global
by Felix Singer (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Edward O'Callaghan, Angel Pons, Anastasia Klimchuk. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/68774 ) Change subject: ichspi.c: heap allocate hwseq_data to remove global ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/68774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib362c5ab2d3e8afee2c3c7d3135cc4414d6bd6c3 Gerrit-Change-Number: 68774 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 24 Oct 2022 23:35:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in flashrom[master]: ichspi.c: derive hsfc_fcycle from ctx in ich_start_hwseq_xfer()
by Felix Singer (Code Review) 25 Oct '22

25 Oct '22

Attention is currently required from: Edward O'Callaghan, Angel Pons, Anastasia Klimchuk. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/68773 ) Change subject: ichspi.c: derive hsfc_fcycle from ctx in ich_start_hwseq_xfer() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/68773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib0ccf4b32fd1e2be2ecc3a4a4c6e397c8e901a0a Gerrit-Change-Number: 68773 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 24 Oct 2022 23:31:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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