January 2022 - flashrom-gerrit

Change in flashrom[master]: ichspi: Extract handling programmer param into a function
by Angel Pons (Code Review) 17 Jan '22

17 Jan '22

Attention is currently required from: Edward O'Callaghan, Anastasia Klimchuk, Nikolai Artemiev. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58736 ) Change subject: ichspi: Extract handling programmer param into a function ...................................................................... Patch Set 7: Code-Review+2 (1 comment) Patchset: PS7: > I deleted "TEST ME ON ICH7" from commit message, because I realised this patch doesn't need to be? I […] Sounds good -- To view, visit https://review.coreboot.org/c/flashrom/+/58736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I20e2379a6fd58c9346f0a2d6daf2b8decf1f6976 Gerrit-Change-Number: 58736 Gerrit-PatchSet: 7 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Mon, 17 Jan 2022 16:58:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: spi25_statusreg.c: add SR3 read/write support
by Sergii Dmytruk (Code Review) 17 Jan '22

17 Jan '22

Attention is currently required from: Nico Huber, Anastasia Klimchuk, Nikolai Artemiev. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/60230 ) Change subject: spi25_statusreg.c: add SR3 read/write support ...................................................................... Patch Set 4: (1 comment) File flash.h: https://review.coreboot.org/c/flashrom/+/60230/comment/6b088dd4_818f7e8e PS2, Line 148: FEATURE_SR3 > Single flag or no flag at all? What information does it carry that wouldn't be […] It just communicates availability of SR3 since not all chips have it. I mostly followed code that adds SR2 though and can drop this flag if you think it's not actually necessary to guard against accidental use of opcodes that might not be supported. -- To view, visit https://review.coreboot.org/c/flashrom/+/60230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id987c544c02da2b956e6ad2c525265cac8f15be1 Gerrit-Change-Number: 60230 Gerrit-PatchSet: 4 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Mon, 17 Jan 2022 15:24:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: comment

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Change in flashrom[master]: Makefile: replace RAW_ACCESS with RAW_MEM_ACCESS X86_MSR X86_PORT_IO
by Thomas Heijligen (Code Review) 17 Jan '22

17 Jan '22

Attention is currently required from: Nico Huber, Angel Pons. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/60325 ) Change subject: Makefile: replace RAW_ACCESS with RAW_MEM_ACCESS X86_MSR X86_PORT_IO ...................................................................... Patch Set 5: (4 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/60325/comment/64226dc9_f325d5e2 PS4, Line 10: realy > *really* Done https://review.coreboot.org/c/flashrom/+/60325/comment/9027351b_9ea779df PS4, Line 11: has handels > *handles* Done File Makefile: https://review.coreboot.org/c/flashrom/+/60325/comment/618c94d7_ffff11ef PS4, Line 835: -D'NEED_RAW_ACCESS=1' > If this vanishes, we should update `meson.build` as well. Done https://review.coreboot.org/c/flashrom/+/60325/comment/7869789b_e754ab5e PS4, Line 397: hwaccess.o > Is there anything left in it that isn't only needed in case of RAW_MEM_ACCESS? Done, see previous commit (new in chain) -- To view, visit https://review.coreboot.org/c/flashrom/+/60325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5bdafaa3c5023ad6c4a695493eeddf11bc148085 Gerrit-Change-Number: 60325 Gerrit-PatchSet: 5 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 17 Jan 2022 14:34:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in flashrom[master]: hwaccess: move mmio functions into hwaccess_physmap
by Thomas Heijligen (Code Review) 17 Jan '22

17 Jan '22

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/61160 ) Change subject: hwaccess: move mmio functions into hwaccess_physmap ...................................................................... hwaccess: move mmio functions into hwaccess_physmap The mmio_le/be_read/writex functions are used for raw memory access. Bundle them with the physmap functions. Change-Id: I313062b078e89630c703038866ac93c651f0f49a Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M Makefile M atapromise.c M board_enable.c M chipset_enable.c M dmi.c M drkaiser.c M flashrom.c M gfxnvidia.c D hwaccess.c M hwaccess.h M hwaccess_physmap.c M hwaccess_physmap.h M ich_descriptors.c M ichspi.c M internal.c M it8212.c M it87spi.c M libflashrom.c M mcp6x_spi.c M meson.build M nicintel.c M nicintel_eeprom.c M nicintel_spi.c M ogp_spi.c M satamv.c M satasii.c M sb600spi.c M wbsio_spi.c 28 files changed, 249 insertions(+), 293 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/60/61160/1 diff --git a/Makefile b/Makefile index b8287a9..6e2e33f 100644 --- a/Makefile +++ b/Makefile @@ -833,7 +833,7 @@ ifneq ($(NEED_RAW_ACCESS), ) # Raw memory, MSR or PCI port I/O access. FEATURE_CFLAGS += -D'NEED_RAW_ACCESS=1' -PROGRAMMER_OBJS += hwaccess.o hwaccess_physmap.o +PROGRAMMER_OBJS += hwaccess_physmap.o ifeq ($(ARCH), x86) FEATURE_CFLAGS += -D'__FLASHROM_HAVE_OUTB__=1' diff --git a/atapromise.c b/atapromise.c index fb3adcb..d781190 100644 --- a/atapromise.c +++ b/atapromise.c @@ -18,7 +18,6 @@ #include <stdlib.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_x86_io.h" #include "hwaccess_physmap.h" #include "platform/pci.h" diff --git a/board_enable.c b/board_enable.c index 445e354..c23e257 100644 --- a/board_enable.c +++ b/board_enable.c @@ -25,7 +25,6 @@ #include <stdlib.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_x86_io.h" #include "hwaccess_x86_msr.h" #include "platform/pci.h" diff --git a/chipset_enable.c b/chipset_enable.c index 02a93a8..d72300e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -33,7 +33,6 @@ #include <errno.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_x86_io.h" #include "hwaccess_x86_msr.h" #include "hwaccess_physmap.h" diff --git a/dmi.c b/dmi.c index df918f9..16d350d 100644 --- a/dmi.c +++ b/dmi.c @@ -31,7 +31,6 @@ #include <stdlib.h> #include "flash.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "programmer.h" diff --git a/drkaiser.c b/drkaiser.c index 3738930..0849109 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -17,7 +17,6 @@ #include <stdlib.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "platform/pci.h" diff --git a/flashrom.c b/flashrom.c index 73ebab5..bd34676 100644 --- a/flashrom.c +++ b/flashrom.c @@ -37,7 +37,6 @@ #include "flash.h" #include "flashchips.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "chipdrivers.h" diff --git a/gfxnvidia.c b/gfxnvidia.c index 535467e..e5c07dd 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -18,7 +18,6 @@ #include <string.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "platform/pci.h" diff --git a/hwaccess.c b/hwaccess.c deleted file mode 100644 index 4e8a274..0000000 --- a/hwaccess.c +++ /dev/null @@ -1,237 +0,0 @@ -/* - * This file is part of the flashrom project. - * - * Copyright (C) 2009,2010 Carl-Daniel Hailfinger - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <stdlib.h> -#include <errno.h> -#include <sys/types.h> -#if !defined (__DJGPP__) && !defined(__LIBPAYLOAD__) -/* No file access needed/possible to get hardware access permissions. */ -#include <unistd.h> -#include <fcntl.h> -#endif -#include "flash.h" -#include "hwaccess.h" - -/* Prevent reordering and/or merging of reads/writes to hardware. - * Such reordering and/or merging would break device accesses which depend on the exact access order. - */ -static inline void sync_primitive(void) -{ -/* This is not needed for... - * - x86: uses uncached accesses which have a strongly ordered memory model. - * - MIPS: uses uncached accesses in mode 2 on /dev/mem which has also a strongly ordered memory model. - * - ARM: uses a strongly ordered memory model for device memories. - * - * See also https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Docume… - */ -// cf. http://lxr.free-electrons.com/source/arch/powerpc/include/asm/barrier.h -#if defined(__powerpc) || defined(__powerpc__) || defined(__powerpc64__) || defined(__POWERPC__) || \ - defined(__ppc__) || defined(__ppc64__) || defined(_M_PPC) || defined(_ARCH_PPC) || \ - defined(_ARCH_PPC64) || defined(__ppc) - asm("eieio" : : : "memory"); -#elif (__sparc__) || defined (__sparc) -#if defined(__sparc_v9__) || defined(__sparcv9) - /* Sparc V9 CPUs support three different memory orderings that range from x86-like TSO to PowerPC-like - * RMO. The modes can be switched at runtime thus to make sure we maintain the right order of access we - * use the strongest hardware memory barriers that exist on Sparc V9. */ - asm volatile ("membar #Sync" ::: "memory"); -#elif defined(__sparc_v8__) || defined(__sparcv8) - /* On SPARC V8 there is no RMO just PSO and that does not apply to I/O accesses... but if V8 code is run - * on V9 CPUs it might apply... or not... we issue a write barrier anyway. That's the most suitable - * operation in the V8 instruction set anyway. If you know better then please tell us. */ - asm volatile ("stbar"); -#else - #error Unknown and/or unsupported SPARC instruction set version detected. -#endif -#endif -} - -void mmio_writeb(uint8_t val, void *addr) -{ - *(volatile uint8_t *) addr = val; - sync_primitive(); -} - -void mmio_writew(uint16_t val, void *addr) -{ - *(volatile uint16_t *) addr = val; - sync_primitive(); -} - -void mmio_writel(uint32_t val, void *addr) -{ - *(volatile uint32_t *) addr = val; - sync_primitive(); -} - -uint8_t mmio_readb(const void *addr) -{ - return *(volatile const uint8_t *) addr; -} - -uint16_t mmio_readw(const void *addr) -{ - return *(volatile const uint16_t *) addr; -} - -uint32_t mmio_readl(const void *addr) -{ - return *(volatile const uint32_t *) addr; -} - -void mmio_readn(const void *addr, uint8_t *buf, size_t len) -{ - memcpy(buf, addr, len); - return; -} - -void mmio_le_writeb(uint8_t val, void *addr) -{ - mmio_writeb(cpu_to_le8(val), addr); -} - -void mmio_le_writew(uint16_t val, void *addr) -{ - mmio_writew(cpu_to_le16(val), addr); -} - -void mmio_le_writel(uint32_t val, void *addr) -{ - mmio_writel(cpu_to_le32(val), addr); -} - -uint8_t mmio_le_readb(const void *addr) -{ - return le_to_cpu8(mmio_readb(addr)); -} - -uint16_t mmio_le_readw(const void *addr) -{ - return le_to_cpu16(mmio_readw(addr)); -} - -uint32_t mmio_le_readl(const void *addr) -{ - return le_to_cpu32(mmio_readl(addr)); -} - -enum mmio_write_type { - mmio_write_type_b, - mmio_write_type_w, - mmio_write_type_l, -}; - -struct undo_mmio_write_data { - void *addr; - int reg; - enum mmio_write_type type; - union { - uint8_t bdata; - uint16_t wdata; - uint32_t ldata; - }; -}; - -static int undo_mmio_write(void *p) -{ - struct undo_mmio_write_data *data = p; - msg_pdbg("Restoring MMIO space at %p\n", data->addr); - switch (data->type) { - case mmio_write_type_b: - mmio_writeb(data->bdata, data->addr); - break; - case mmio_write_type_w: - mmio_writew(data->wdata, data->addr); - break; - case mmio_write_type_l: - mmio_writel(data->ldata, data->addr); - break; - } - /* p was allocated in register_undo_mmio_write. */ - free(p); - return 0; -} - -#define register_undo_mmio_write(a, c) \ -{ \ - struct undo_mmio_write_data *undo_mmio_write_data; \ - undo_mmio_write_data = malloc(sizeof(*undo_mmio_write_data)); \ - if (!undo_mmio_write_data) { \ - msg_gerr("Out of memory!\n"); \ - exit(1); \ - } \ - undo_mmio_write_data->addr = a; \ - undo_mmio_write_data->type = mmio_write_type_##c; \ - undo_mmio_write_data->c##data = mmio_read##c(a); \ - register_shutdown(undo_mmio_write, undo_mmio_write_data); \ -} - -#define register_undo_mmio_writeb(a) register_undo_mmio_write(a, b) -#define register_undo_mmio_writew(a) register_undo_mmio_write(a, w) -#define register_undo_mmio_writel(a) register_undo_mmio_write(a, l) - -void rmmio_writeb(uint8_t val, void *addr) -{ - register_undo_mmio_writeb(addr); - mmio_writeb(val, addr); -} - -void rmmio_writew(uint16_t val, void *addr) -{ - register_undo_mmio_writew(addr); - mmio_writew(val, addr); -} - -void rmmio_writel(uint32_t val, void *addr) -{ - register_undo_mmio_writel(addr); - mmio_writel(val, addr); -} - -void rmmio_le_writeb(uint8_t val, void *addr) -{ - register_undo_mmio_writeb(addr); - mmio_le_writeb(val, addr); -} - -void rmmio_le_writew(uint16_t val, void *addr) -{ - register_undo_mmio_writew(addr); - mmio_le_writew(val, addr); -} - -void rmmio_le_writel(uint32_t val, void *addr) -{ - register_undo_mmio_writel(addr); - mmio_le_writel(val, addr); -} - -void rmmio_valb(void *addr) -{ - register_undo_mmio_writeb(addr); -} - -void rmmio_valw(void *addr) -{ - register_undo_mmio_writew(addr); -} - -void rmmio_vall(void *addr) -{ - register_undo_mmio_writel(addr); -} diff --git a/hwaccess.h b/hwaccess.h index d80e0e3..98ca08e 100644 --- a/hwaccess.h +++ b/hwaccess.h @@ -20,38 +20,6 @@ #ifndef __HWACCESS_H__ #define __HWACCESS_H__ 1 -void mmio_writeb(uint8_t val, void *addr); -void mmio_writew(uint16_t val, void *addr); -void mmio_writel(uint32_t val, void *addr); -uint8_t mmio_readb(const void *addr); -uint16_t mmio_readw(const void *addr); -uint32_t mmio_readl(const void *addr); -void mmio_readn(const void *addr, uint8_t *buf, size_t len); -void mmio_le_writeb(uint8_t val, void *addr); -void mmio_le_writew(uint16_t val, void *addr); -void mmio_le_writel(uint32_t val, void *addr); -uint8_t mmio_le_readb(const void *addr); -uint16_t mmio_le_readw(const void *addr); -uint32_t mmio_le_readl(const void *addr); -#define pci_mmio_writeb mmio_le_writeb -#define pci_mmio_writew mmio_le_writew -#define pci_mmio_writel mmio_le_writel -#define pci_mmio_readb mmio_le_readb -#define pci_mmio_readw mmio_le_readw -#define pci_mmio_readl mmio_le_readl -void rmmio_writeb(uint8_t val, void *addr); -void rmmio_writew(uint16_t val, void *addr); -void rmmio_writel(uint32_t val, void *addr); -void rmmio_le_writeb(uint8_t val, void *addr); -void rmmio_le_writew(uint16_t val, void *addr); -void rmmio_le_writel(uint32_t val, void *addr); -#define pci_rmmio_writeb rmmio_le_writeb -#define pci_rmmio_writew rmmio_le_writew -#define pci_rmmio_writel rmmio_le_writel -void rmmio_valb(void *addr); -void rmmio_valw(void *addr); -void rmmio_vall(void *addr); - #define ___constant_swab8(x) ((uint8_t) ( \ (((uint8_t)(x) & (uint8_t)0xffU)))) diff --git a/hwaccess_physmap.c b/hwaccess_physmap.c index dcc6ed7..b1b9c64 100644 --- a/hwaccess_physmap.c +++ b/hwaccess_physmap.c @@ -18,16 +18,20 @@ #include <unistd.h> #include <stdbool.h> +#include <stdint.h> #include <stdio.h> #include <stdlib.h> #include <string.h> #include <errno.h> #include "flash.h" +#include "hwaccess.h" #include "hwaccess_physmap.h" #if !defined(__DJGPP__) && !defined(__LIBPAYLOAD__) /* No file access needed/possible to get mmap access permissions or access MSR. */ +#include <unistd.h> #include <sys/stat.h> +#include <sys/types.h> #include <fcntl.h> #endif @@ -361,3 +365,212 @@ { return physmap_common(descr, phys_addr, len, PHYSM_RO, PHYSM_NOCLEANUP, PHYSM_EXACT); } + +/* Prevent reordering and/or merging of reads/writes to hardware. + * Such reordering and/or merging would break device accesses which depend on the exact access order. + */ +static inline void sync_primitive(void) +{ +/* This is not needed for... + * - x86: uses uncached accesses which have a strongly ordered memory model. + * - MIPS: uses uncached accesses in mode 2 on /dev/mem which has also a strongly ordered memory model. + * - ARM: uses a strongly ordered memory model for device memories. + * + * See also https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Docume… + */ +// cf. http://lxr.free-electrons.com/source/arch/powerpc/include/asm/barrier.h +#if defined(__powerpc) || defined(__powerpc__) || defined(__powerpc64__) || defined(__POWERPC__) || \ + defined(__ppc__) || defined(__ppc64__) || defined(_M_PPC) || defined(_ARCH_PPC) || \ + defined(_ARCH_PPC64) || defined(__ppc) + asm("eieio" : : : "memory"); +#elif (__sparc__) || defined (__sparc) +#if defined(__sparc_v9__) || defined(__sparcv9) + /* Sparc V9 CPUs support three different memory orderings that range from x86-like TSO to PowerPC-like + * RMO. The modes can be switched at runtime thus to make sure we maintain the right order of access we + * use the strongest hardware memory barriers that exist on Sparc V9. */ + asm volatile ("membar #Sync" ::: "memory"); +#elif defined(__sparc_v8__) || defined(__sparcv8) + /* On SPARC V8 there is no RMO just PSO and that does not apply to I/O accesses... but if V8 code is run + * on V9 CPUs it might apply... or not... we issue a write barrier anyway. That's the most suitable + * operation in the V8 instruction set anyway. If you know better then please tell us. */ + asm volatile ("stbar"); +#else + #error Unknown and/or unsupported SPARC instruction set version detected. +#endif +#endif +} + +void mmio_writeb(uint8_t val, void *addr) +{ + *(volatile uint8_t *) addr = val; + sync_primitive(); +} + +void mmio_writew(uint16_t val, void *addr) +{ + *(volatile uint16_t *) addr = val; + sync_primitive(); +} + +void mmio_writel(uint32_t val, void *addr) +{ + *(volatile uint32_t *) addr = val; + sync_primitive(); +} + +uint8_t mmio_readb(const void *addr) +{ + return *(volatile const uint8_t *) addr; +} + +uint16_t mmio_readw(const void *addr) +{ + return *(volatile const uint16_t *) addr; +} + +uint32_t mmio_readl(const void *addr) +{ + return *(volatile const uint32_t *) addr; +} + +void mmio_readn(const void *addr, uint8_t *buf, size_t len) +{ + memcpy(buf, addr, len); + return; +} + +void mmio_le_writeb(uint8_t val, void *addr) +{ + mmio_writeb(cpu_to_le8(val), addr); +} + +void mmio_le_writew(uint16_t val, void *addr) +{ + mmio_writew(cpu_to_le16(val), addr); +} + +void mmio_le_writel(uint32_t val, void *addr) +{ + mmio_writel(cpu_to_le32(val), addr); +} + +uint8_t mmio_le_readb(const void *addr) +{ + return le_to_cpu8(mmio_readb(addr)); +} + +uint16_t mmio_le_readw(const void *addr) +{ + return le_to_cpu16(mmio_readw(addr)); +} + +uint32_t mmio_le_readl(const void *addr) +{ + return le_to_cpu32(mmio_readl(addr)); +} + +enum mmio_write_type { + mmio_write_type_b, + mmio_write_type_w, + mmio_write_type_l, +}; + +struct undo_mmio_write_data { + void *addr; + int reg; + enum mmio_write_type type; + union { + uint8_t bdata; + uint16_t wdata; + uint32_t ldata; + }; +}; + +static int undo_mmio_write(void *p) +{ + struct undo_mmio_write_data *data = p; + msg_pdbg("Restoring MMIO space at %p\n", data->addr); + switch (data->type) { + case mmio_write_type_b: + mmio_writeb(data->bdata, data->addr); + break; + case mmio_write_type_w: + mmio_writew(data->wdata, data->addr); + break; + case mmio_write_type_l: + mmio_writel(data->ldata, data->addr); + break; + } + /* p was allocated in register_undo_mmio_write. */ + free(p); + return 0; +} + +#define register_undo_mmio_write(a, c) \ +{ \ + struct undo_mmio_write_data *undo_mmio_write_data; \ + undo_mmio_write_data = malloc(sizeof(*undo_mmio_write_data)); \ + if (!undo_mmio_write_data) { \ + msg_gerr("Out of memory!\n"); \ + exit(1); \ + } \ + undo_mmio_write_data->addr = a; \ + undo_mmio_write_data->type = mmio_write_type_##c; \ + undo_mmio_write_data->c##data = mmio_read##c(a); \ + register_shutdown(undo_mmio_write, undo_mmio_write_data); \ +} + +#define register_undo_mmio_writeb(a) register_undo_mmio_write(a, b) +#define register_undo_mmio_writew(a) register_undo_mmio_write(a, w) +#define register_undo_mmio_writel(a) register_undo_mmio_write(a, l) + +void rmmio_writeb(uint8_t val, void *addr) +{ + register_undo_mmio_writeb(addr); + mmio_writeb(val, addr); +} + +void rmmio_writew(uint16_t val, void *addr) +{ + register_undo_mmio_writew(addr); + mmio_writew(val, addr); +} + +void rmmio_writel(uint32_t val, void *addr) +{ + register_undo_mmio_writel(addr); + mmio_writel(val, addr); +} + +void rmmio_le_writeb(uint8_t val, void *addr) +{ + register_undo_mmio_writeb(addr); + mmio_le_writeb(val, addr); +} + +void rmmio_le_writew(uint16_t val, void *addr) +{ + register_undo_mmio_writew(addr); + mmio_le_writew(val, addr); +} + +void rmmio_le_writel(uint32_t val, void *addr) +{ + register_undo_mmio_writel(addr); + mmio_le_writel(val, addr); +} + +void rmmio_valb(void *addr) +{ + register_undo_mmio_writeb(addr); +} + +void rmmio_valw(void *addr) +{ + register_undo_mmio_writew(addr); +} + +void rmmio_vall(void *addr) +{ + register_undo_mmio_writel(addr); +} diff --git a/hwaccess_physmap.h b/hwaccess_physmap.h index eb3ddb8..a0a7e74 100644 --- a/hwaccess_physmap.h +++ b/hwaccess_physmap.h @@ -24,4 +24,36 @@ void physunmap(void *virt_addr, size_t len); void physunmap_unaligned(void *virt_addr, size_t len); +void mmio_writeb(uint8_t val, void *addr); +void mmio_writew(uint16_t val, void *addr); +void mmio_writel(uint32_t val, void *addr); +uint8_t mmio_readb(const void *addr); +uint16_t mmio_readw(const void *addr); +uint32_t mmio_readl(const void *addr); +void mmio_readn(const void *addr, uint8_t *buf, size_t len); +void mmio_le_writeb(uint8_t val, void *addr); +void mmio_le_writew(uint16_t val, void *addr); +void mmio_le_writel(uint32_t val, void *addr); +uint8_t mmio_le_readb(const void *addr); +uint16_t mmio_le_readw(const void *addr); +uint32_t mmio_le_readl(const void *addr); +#define pci_mmio_writeb mmio_le_writeb +#define pci_mmio_writew mmio_le_writew +#define pci_mmio_writel mmio_le_writel +#define pci_mmio_readb mmio_le_readb +#define pci_mmio_readw mmio_le_readw +#define pci_mmio_readl mmio_le_readl +void rmmio_writeb(uint8_t val, void *addr); +void rmmio_writew(uint16_t val, void *addr); +void rmmio_writel(uint32_t val, void *addr); +void rmmio_le_writeb(uint8_t val, void *addr); +void rmmio_le_writew(uint16_t val, void *addr); +void rmmio_le_writel(uint32_t val, void *addr); +#define pci_rmmio_writeb rmmio_le_writeb +#define pci_rmmio_writew rmmio_le_writew +#define pci_rmmio_writel rmmio_le_writel +void rmmio_valb(void *addr); +void rmmio_valw(void *addr); +void rmmio_vall(void *addr); + #endif /* __HWACCESS_PHYSMAP_H__ */ \ No newline at end of file diff --git a/ich_descriptors.c b/ich_descriptors.c index 56a3c67..2bff341 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -15,8 +15,8 @@ * GNU General Public License for more details. */ +#include "hwaccess_physmap.h" #include "ich_descriptors.h" -#include "hwaccess.h" #ifdef ICH_DESCRIPTORS_FROM_DUMP_ONLY #include <stdio.h> diff --git a/ichspi.c b/ichspi.c index 0bb6360..47b23eb 100644 --- a/ichspi.c +++ b/ichspi.c @@ -23,7 +23,6 @@ #include <stdlib.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "spi.h" #include "ich_descriptors.h" diff --git a/internal.c b/internal.c index f2f1fb1..bb606ca 100644 --- a/internal.c +++ b/internal.c @@ -19,7 +19,6 @@ #include <stdlib.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_x86_io.h" #include "hwaccess_physmap.h" #include "platform/pci.h" diff --git a/it8212.c b/it8212.c index ca82d9c..e57397a 100644 --- a/it8212.c +++ b/it8212.c @@ -17,7 +17,6 @@ #include <stdlib.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "platform/pci.h" diff --git a/it87spi.c b/it87spi.c index 0944915..728ec70 100644 --- a/it87spi.c +++ b/it87spi.c @@ -25,7 +25,7 @@ #include "flash.h" #include "chipdrivers.h" #include "programmer.h" -#include "hwaccess.h" +#include "hwaccess_physmap.h" #include "hwaccess_x86_io.h" #include "spi.h" diff --git a/libflashrom.c b/libflashrom.c index 1ecf650..fb70934 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -29,7 +29,6 @@ #include "fmap.h" #include "programmer.h" #include "layout.h" -#include "hwaccess.h" #include "ich_descriptors.h" #include "libflashrom.h" diff --git a/mcp6x_spi.c b/mcp6x_spi.c index 2097cf4..81ef1b5 100644 --- a/mcp6x_spi.c +++ b/mcp6x_spi.c @@ -23,7 +23,6 @@ #include <ctype.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "platform/pci.h" diff --git a/meson.build b/meson.build index b2e2d72..403a33e 100644 --- a/meson.build +++ b/meson.build @@ -346,7 +346,6 @@ # raw memory, MSR or PCI port I/O access if need_raw_access - srcs += 'hwaccess.c' srcs += 'hwaccess_x86_io.c' srcs += 'hwaccess_x86_msr.c' srcs += 'hwaccess_physmap.c' diff --git a/nicintel.c b/nicintel.c index c8a8789..fdc4eba 100644 --- a/nicintel.c +++ b/nicintel.c @@ -18,7 +18,6 @@ #include <stdlib.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "platform/pci.h" diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index ea0e768..af5fa21 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -34,7 +34,6 @@ #include "flash.h" #include "spi.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "platform/pci.h" diff --git a/nicintel_spi.c b/nicintel_spi.c index 004af66..1f1dcff 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -34,7 +34,6 @@ #include <unistd.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "platform/pci.h" diff --git a/ogp_spi.c b/ogp_spi.c index 830cfe7..bc0d739 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -18,7 +18,6 @@ #include <string.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "platform/pci.h" diff --git a/satamv.c b/satamv.c index e7c4305..445b2c8 100644 --- a/satamv.c +++ b/satamv.c @@ -19,7 +19,6 @@ #include <stdlib.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_x86_io.h" #include "hwaccess_physmap.h" #include "platform/pci.h" diff --git a/satasii.c b/satasii.c index a27fc29..3ee5556 100644 --- a/satasii.c +++ b/satasii.c @@ -17,7 +17,6 @@ /* Datasheets can be found on http://www.siliconimage.com. Great thanks! */ #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "platform/pci.h" diff --git a/sb600spi.c b/sb600spi.c index 32a7420..eb54028 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -22,7 +22,6 @@ #include <stdlib.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "spi.h" #include "platform/pci.h" diff --git a/wbsio_spi.c b/wbsio_spi.c index 805abf7..2794491 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -19,7 +19,7 @@ #include "flash.h" #include "chipdrivers.h" #include "programmer.h" -#include "hwaccess.h" +#include "hwaccess_physmap.h" #include "hwaccess_x86_io.h" #include "spi.h" -- To view, visit https://review.coreboot.org/c/flashrom/+/61160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I313062b078e89630c703038866ac93c651f0f49a Gerrit-Change-Number: 61160 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in flashrom[master]: Makefile: replace RAW_ACCESS with RAW_MEM_ACCESS X86_MSR X86_PORT_IO
by Thomas Heijligen (Code Review) 17 Jan '22

17 Jan '22

Attention is currently required from: Thomas Heijligen, Angel Pons. Hello build bot (Jenkins), Nico Huber, Paul Menzel, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/60325 to look at the new patch set (#5). Change subject: Makefile: replace RAW_ACCESS with RAW_MEM_ACCESS X86_MSR X86_PORT_IO ...................................................................... Makefile: replace RAW_ACCESS with RAW_MEM_ACCESS X86_MSR X86_PORT_IO Let programmer only depend on the kind of hardware access method they really need. Libpci no longer depends on all hardware access types since each programmer has handles this dependency. Change-Id: I5bdafaa3c5023ad6c4a695493eeddf11bc148085 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M Makefile M meson.build 2 files changed, 21 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/25/60325/5 -- To view, visit https://review.coreboot.org/c/flashrom/+/60325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5bdafaa3c5023ad6c4a695493eeddf11bc148085 Gerrit-Change-Number: 60325 Gerrit-PatchSet: 5 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: spi25_statusreg.c: add SR3 read/write support
by Nico Huber (Code Review) 17 Jan '22

17 Jan '22

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Sergii Dmytruk. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/60230 ) Change subject: spi25_statusreg.c: add SR3 read/write support ...................................................................... Patch Set 4: (1 comment) File flash.h: https://review.coreboot.org/c/flashrom/+/60230/comment/317ea1dc_994cfdde PS2, Line 148: FEATURE_SR3 > SR2 can be written in two different ways, but read in one. […] Single flag or no flag at all? What information does it carry that wouldn't be visible from `.reg_bits`, for instance? -- To view, visit https://review.coreboot.org/c/flashrom/+/60230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id987c544c02da2b956e6ad2c525265cac8f15be1 Gerrit-Change-Number: 60230 Gerrit-PatchSet: 4 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Mon, 17 Jan 2022 12:46:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: comment

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Change in flashrom[master]: libflashrom,writeprotect: add functions for reading/writing WP settings
by Nikolai Artemiev (Code Review) 17 Jan '22

17 Jan '22

Attention is currently required from: Nico Huber, Edward O'Callaghan, Anastasia Klimchuk, Sergii Dmytruk. Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58479 ) Change subject: libflashrom,writeprotect: add functions for reading/writing WP settings ...................................................................... Patch Set 28: (1 comment) File writeprotect.c: https://review.coreboot.org/c/flashrom/+/58479/comment/050bedae_e716820c PS27, Line 161: to write : * to the chip > drop Done -- To view, visit https://review.coreboot.org/c/flashrom/+/58479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad Gerrit-Change-Number: 58479 Gerrit-PatchSet: 28 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Mon, 17 Jan 2022 08:46:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in flashrom[master]: writeprotect.h: add structure to represent chip wp configuration bits
by Nikolai Artemiev (Code Review) 17 Jan '22

17 Jan '22

Attention is currently required from: Nico Huber, Angel Pons, Sergii Dmytruk. Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58478 ) Change subject: writeprotect.h: add structure to represent chip wp configuration bits ...................................................................... Patch Set 27: (1 comment) File flash.h: https://review.coreboot.org/c/flashrom/+/58478/comment/6ecbb399_f71cdaca PS22, Line 201: Complete > Your intentions don't change that the comment is misleading. If you […] Thanks, I think that's a much better description of the structure. -- To view, visit https://review.coreboot.org/c/flashrom/+/58478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809 Gerrit-Change-Number: 58478 Gerrit-PatchSet: 27 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Mon, 17 Jan 2022 08:46:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: comment

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Change in flashrom[master]: flashchips: add writeprotect bit layout map to chips
by Nikolai Artemiev (Code Review) 17 Jan '22

17 Jan '22

Attention is currently required from: Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk. Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58477 ) Change subject: flashchips: add writeprotect bit layout map to chips ...................................................................... Patch Set 26: (2 comments) File flash.h: https://review.coreboot.org/c/flashrom/+/58477/comment/6027590f_77efed75 PS25, Line 287: struct reg_bit_info cmp; > Please add a comment about the acronyms. (Thought I mentioned that before […] Done File flash.h: https://review.coreboot.org/c/flashrom/+/58477/comment/ae79894c_5eae8307 PS21, Line 192: 0 > Still, why the 0? Done -- To view, visit https://review.coreboot.org/c/flashrom/+/58477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id08d77e6d4ca5109c0d698271146d026dbc21284 Gerrit-Change-Number: 58477 Gerrit-PatchSet: 26 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Mon, 17 Jan 2022 08:46:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: comment

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Change in flashrom[master]: spi25_statusreg,flashchips: add SR2 read/write support
by Nikolai Artemiev (Code Review) 17 Jan '22

17 Jan '22

Attention is currently required from: Nico Huber, Angel Pons, Sergii Dmytruk. Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58570 ) Change subject: spi25_statusreg,flashchips: add SR2 read/write support ...................................................................... Patch Set 23: (3 comments) File flash.h: https://review.coreboot.org/c/flashrom/+/58570/comment/df799c75_44d020ab PS22, Line 145: #define FEATURE_RDSR2 (1 << 21) > Isn't this implied by the above and function pointers that make use of it? […] Done https://review.coreboot.org/c/flashrom/+/58570/comment/42480b1e_f6181556 PS22, Line 147: > Only one empty line please. Done File flashchips.c: https://review.coreboot.org/c/flashrom/+/58570/comment/1d81735c_f68fcef7 PS18, Line 6711: FEATURE_WRSR_EXT > Interesting, looks like the datasheet is inconsistent. It first states: […] I tested it by writing to the QE bit in SR2 (since the SRP1 isn't writable unless you get special chips with powercycle / permanent protection modes enabled) and both commands worked. My understanding of section 7.5 is roughly that CS# going high after 8 bits will just write SR1, and CS# going high after 16 bits will write SR1+SR2. The section you quote implies otherwise but I'd assume it was written for a different chip and just not updated for this one. -- To view, visit https://review.coreboot.org/c/flashrom/+/58570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db Gerrit-Change-Number: 58570 Gerrit-PatchSet: 23 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Mon, 17 Jan 2022 08:46:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: comment

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flashrom-gerrit January 2022