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Change subject: tests: Upgrade linux_spi test to run probe lifecycle
......................................................................
Patch Set 4:
(2 comments)
This change is ready for review.
File tests/lifecycle.c:
https://review.coreboot.org/c/flashrom/+/59742/comment/9ec1c5db_a45d242e
PS2, Line 336: W25Q128.V
> Thank you so much for finding the problem! I missed the elephant in the room, forgot about caching I […]
I fixed my epic fail :) I only have a question about spidev include (I added another comment).
File tests/lifecycle.c:
https://review.coreboot.org/c/flashrom/+/59742/comment/d61d5041_72f0f817
PS4, Line 18: #include <linux/spi/spidev.h>
This include seems inevitable... is it ok? Do I need to guard it with anything? (like CONFIG_LINUX_SPI for example)
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Change subject: tests: test write protection
......................................................................
Patch Set 26:
(1 comment)
Patchset:
PS26:
Sergii, there is a change happening at the moment: converting everything to call libflashrom API, and everything includes tests. Your tests are calling do_erase, so you need to update them as well. Good news: it will be really easy, and here is an example CB:61137
No rush, you can do at convenient time. Your chain will go chronologically after write-protect chain anyway.
Thank you!
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Hello build bot (Jenkins), Nico Huber, Angel Pons,
I'd like you to reexamine a change. Please visit
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Change subject: [RFC][OTP] spi25_statusreg: support reading/writing security register
......................................................................
[RFC][OTP] spi25_statusreg: support reading/writing security register
Not to be confused with "secure registers" of OTP.
Security register is a dedicated status register for security-related
bits. You don't write its value directly, issuing corresponding write
command with no data just sets OTP bit to 1 automatically.
No WREN is necessary, but at least some datasheets indicate BUSY state
after write command.
Unlike cases where OTP bit is part of SR and can only be written while
in OTP mode, security register can only be written outside of the mode.
Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae
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---
M flash.h
M spi.h
M spi25_statusreg.c
3 files changed, 74 insertions(+), 28 deletions(-)
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Change subject: [RFC][OTP] tests: add tests for OTP regions
......................................................................
[RFC][OTP] tests: add tests for OTP regions
There are two sets of tests targeting two new dummyflasher chips that provide
two kinds of OTP.
Change-Id: I4ff584395367dfd52db89332d8e45d7e865276e1
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Change subject: tests: test write protection
......................................................................
tests: test write protection
Tests both WP implementation and its emulation in dummy programmer.
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Change subject: flashchips: enable write-protection for W25Q{64,128}.V
......................................................................
flashchips: enable write-protection for W25Q{64,128}.V
Configuration for W25Q64 was tested on hardware (W25Q64FV).
Emulation of W25Q128 in dummyflasher will be extended to support WP.
Haven't tested this one on hardware, but it's the same configuration as
for W25Q64 except that it has WPS.
W25Q64.V chip was split into W25Q64BV/W25Q64CV/W25Q64FV (no SR3 and WPS)
and W25Q64JV (SR3 and WPS).
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Change subject: spi25_statusreg.c: add SR3 read/write support
......................................................................
spi25_statusreg.c: add SR3 read/write support
Adds support for reading and writing the third status register, which
needs to be enabled per chip.
Extended WRSR doesn't cover SR3, so only one feature flag is added.
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Change subject: tests: Add run_probe_lifecycle and add dummyflasher probe test
......................................................................
Patch Set 3:
(1 comment)
File tests/lifecycle.c:
https://review.coreboot.org/c/flashrom/+/59741/comment/427f4eba_8b10511f
PS3, Line 72: /* Each probe lifecycle should run independently, without cache. */
: clear_spi_id_cache();
Fix for the situation when subsequent tests were using cache and skipping the actual send command.
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Change subject: [WIP] tests: Upgrade linux_spi test to run probe lifecycle
......................................................................
[WIP] tests: Upgrade linux_spi test to run probe lifecycle
WORK IN PROGRESS
BUG=b:181803212
TEST=ninja test
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