January 2022 - flashrom-gerrit

Change in flashrom[master]: meson: sync programmer dependencies from Makefile
by Peter Marheine (Code Review) 21 Jan '22

21 Jan '22

Attention is currently required from: Thomas Heijligen, Edward O'Callaghan. Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61287 ) Change subject: meson: sync programmer dependencies from Makefile ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/flashrom/+/61287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iae93111fd48865f3fe8dd0eb637349b9a0c4affc Gerrit-Change-Number: 61287 Gerrit-PatchSet: 3 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Fri, 21 Jan 2022 05:15:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in flashrom[master]: meson: build hwaccess only on x86
by Peter Marheine (Code Review) 21 Jan '22

21 Jan '22

Attention is currently required from: Nico Huber, Thomas Heijligen. Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61198 ) Change subject: meson: build hwaccess only on x86 ...................................................................... Patch Set 3: Code-Review-1 (1 comment) File meson.build: https://review.coreboot.org/c/flashrom/+/61198/comment/9d272e08_5dd780cd PS3, Line 357: error('RAW access is not available on non-x86 platforms. Disable the programmer which needs it. Use `meson build -Dpciutils=false -Dconfig_rayer_spi=false`') > Well, the comment about ARM is not wrong. But I have to admit it's misleading […] I hadn't realized that the Meson configuration had diverged so far from the Makefile; I've remedied that in https://review.coreboot.org/c/flashrom/+/61287 by copying the overall structure used in the Makefile. Since the x86 hwaccess headers are included in some non-x86 builds as part of the internal programmer, they do still need changes in order to build for non-x86 systems (even with the Makefile, though I was unable to actually cross-compile with the Makefile for seemingly pkg-config related reasons). I've fixed that in https://review.coreboot.org/c/flashrom/+/61194. Chromium uses Meson for all builds of flashrom, so removing the support would be unhelpful for us. I am not familiar with any conversation that came with its initial introduction, but I assume there was sufficient agreement that it's worth having. -- To view, visit https://review.coreboot.org/c/flashrom/+/61198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iafabe8b4b2a95697773a739501dfc62d880d3f6d Gerrit-Change-Number: 61198 Gerrit-PatchSet: 3 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Fri, 21 Jan 2022 05:15:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Thomas Heijligen <src(a)posteo.de> Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in flashrom[master]: hwaccess: fix build on non-x86 targets
by Peter Marheine (Code Review) 21 Jan '22

21 Jan '22

Attention is currently required from: Paul Menzel, Thomas Heijligen, Edward O'Callaghan. Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61194 ) Change subject: hwaccess: fix build on non-x86 targets ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/61194/comment/bd9cc178_9acdb780 PS1, Line 22: Change-Id: I20f122679c30340b2c73afd7419e79644ddc3c4e > Missing Signed-off-by line? Done Patchset: PS1: > The hwaccess_x86 files should only get compiled on x86 platforms. So as the code which requires it. […] The hwaccess_x86 headers are included in components of the internal programmer that are also built on non-x86: while there are issues with the Meson configuration (fixed in the following CL), the Makefile build is also broken. I've now opted to put the x86 guards in the headers rather than in the files that include them because otherwise the guards would need to be duplicated across three other files. -- To view, visit https://review.coreboot.org/c/flashrom/+/61194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I20f122679c30340b2c73afd7419e79644ddc3c4e Gerrit-Change-Number: 61194 Gerrit-PatchSet: 3 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Fri, 21 Jan 2022 05:15:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: comment

1 0

Change in flashrom[master]: hwaccess: fix build on non-x86 targets
by Peter Marheine (Code Review) 21 Jan '22

21 Jan '22

Attention is currently required from: Edward O'Callaghan, Peter Marheine. Hello build bot (Jenkins), Thomas Heijligen, Edward O'Callaghan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/61194 to look at the new patch set (#3). Change subject: hwaccess: fix build on non-x86 targets ...................................................................... hwaccess: fix build on non-x86 targets The changes to hwaccess in commit 49d758698a0dd166679c48b1a2785e50e9b0cc83 cause build failure on non-x86 systems because the hwaccess_x86_* headers are included in some files that are built for all platforms (particularly those in the internal programmer) and those headers in turn include <sys/io.h> which only exists on x86. This change makes the hwaccess_x86 headers a nop on non-x86 platforms, and adds a define (set in the header as appropriate) allowing callers to detect the presence of rget_io_perms(): that function is used by the internal programmer, which is also supported on non-x86 systems. The comment on the stub implementation of rget_io_perms() is also modified to remove references to non-x86 platforms, since that file is only built on x86 now. BUG=None TEST=meson build succeeds for both x86 and ARM targets Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> Change-Id: I20f122679c30340b2c73afd7419e79644ddc3c4e --- M hwaccess_x86_io.c M hwaccess_x86_io.h M hwaccess_x86_msr.h M internal.c 4 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/61194/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/61194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I20f122679c30340b2c73afd7419e79644ddc3c4e Gerrit-Change-Number: 61194 Gerrit-PatchSet: 3 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in flashrom[master]: flashrom: Convert do_read() into a libflashrom user
by Anastasia Klimchuk (Code Review) 21 Jan '22

21 Jan '22

Attention is currently required from: Nico Huber, Edward O'Callaghan. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/60430 ) Change subject: flashrom: Convert do_read() into a libflashrom user ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/60430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id2addadb891c482ee3f69da806062d7a88776675 Gerrit-Change-Number: 60430 Gerrit-PatchSet: 4 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Fri, 21 Jan 2022 04:53:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in flashrom[master]: flashrom.c: extract operation only uses layout files
by Edward O'Callaghan (Code Review) 21 Jan '22

21 Jan '22

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/59921 ) Change subject: flashrom.c: extract operation only uses layout files ...................................................................... flashrom.c: extract operation only uses layout files This change fixes a bug on handling the extract operation. The extract operation reads out the layout regions to filenames corresponding to the respective layout region names. read_flash_to_file() does this work via write_buf_to_include_args(). This change makes the call to write_buf_to_file() optional as it is still required for -r (read operation) but not for -x (extract operation). BUG=b:209512852 TEST=flashrom -x Fixes: commit ce983bccaab450d358854494f15c2d8a1846d56b Change-Id: Ibc9a4e2966385863345f06662521d6d0e4685121 Signed-off-by: Daniel Campello <campello(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59921 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M flashrom.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved diff --git a/flashrom.c b/flashrom.c index bd34676..dd443b9 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1098,7 +1098,8 @@ goto out_free; } - ret = write_buf_to_file(buf, size, filename); + if (filename) + ret = write_buf_to_file(buf, size, filename); out_free: free(buf); msg_cinfo("%s.\n", ret ? "FAILED" : "done"); 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/flashrom/+/59921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ibc9a4e2966385863345f06662521d6d0e4685121 Gerrit-Change-Number: 59921 Gerrit-PatchSet: 7 Gerrit-Owner: Daniel Campello <campello(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: merged

1 0

Change in flashrom[master]: hwaccess: fix build on non-x86 targets
by Peter Marheine (Code Review) 21 Jan '22

21 Jan '22

Attention is currently required from: Edward O'Callaghan, Peter Marheine. Hello build bot (Jenkins), Thomas Heijligen, Edward O'Callaghan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/61194 to look at the new patch set (#2). Change subject: hwaccess: fix build on non-x86 targets ...................................................................... hwaccess: fix build on non-x86 targets The changes to hwaccess in commit 49d758698a0dd166679c48b1a2785e50e9b0cc83 cause build failure on non-x86 systems because the hwaccess_x86_* headers are included in some files that are built for all platforms (particularly those in the internal programmer) and those headers in turn include <sys/io.h> which only exists on x86. This change makes the hwaccess_x86 headers a nop on non-x86 platforms, and adds a define (set in the header as appropriate) allowing callers to detect the presence of rget_io_perms(): that function is used by the internal programmer, which is also supported on non-x86 systems. BUG=None TEST=meson build succeeds for both x86 and ARM targets Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> Change-Id: I20f122679c30340b2c73afd7419e79644ddc3c4e --- M hwaccess_x86_io.c M hwaccess_x86_io.h M hwaccess_x86_msr.h M internal.c 4 files changed, 15 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/61194/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/61194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I20f122679c30340b2c73afd7419e79644ddc3c4e Gerrit-Change-Number: 61194 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in flashrom[master]: Add mediatek_i2c_spi interface.
by Neill Corlett (Code Review) 21 Jan '22

21 Jan '22

Neill Corlett has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/61288 ) Change subject: Add mediatek_i2c_spi interface. ...................................................................... Add mediatek_i2c_spi interface. Add a spi_master interface supporting MediaTek MST9U ISP mode. Autodetect the bus type via I2C_FUNC_I2C, and use the appropriate read/write commands, in case the MST9U is attached to smbus. TEST=Successfully programmed SPI on test hardware. Change-Id: I24adb14e7b4f7160e1c3ff941774064d5a81e820 Signed-off-by: Neill Corlett <corlett(a)google.com> --- M Makefile A mediatek_i2c_spi.c M meson.build M meson_options.txt M programmer.h M programmer_table.c 6 files changed, 529 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/61288/1 diff --git a/Makefile b/Makefile index d4de2ff..086cd45 100644 --- a/Makefile +++ b/Makefile @@ -482,6 +482,9 @@ # Disables LSPCON support until the i2c helper supports multiple systems. CONFIG_LSPCON_I2C_SPI ?= no +# Disables MediaTek support until the i2c helper supports multiple systems. +CONFIG_MEDIATEK_I2C_SPI ?= no + # Disables REALTEK_MST support until the i2c helper supports multiple systems. CONFIG_REALTEK_MST_I2C_SPI ?= no @@ -698,6 +701,11 @@ PROGRAMMER_OBJS += lspcon_i2c_spi.o endif +ifeq ($(CONFIG_MEDIATEK_I2C_SPI), yes) +FEATURE_FLAGS += -D'CONFIG_MEDIATEK_I2C_SPI=1' +PROGRAMMER_OBJS += mediatek_i2c_spi.o +endif + ifeq ($(CONFIG_REALTEK_MST_I2C_SPI), yes) FEATURE_FLAGS += -D'CONFIG_REALTEK_MST_I2C_SPI=1' PROGRAMMER_OBJS += realtek_mst_i2c_spi.o diff --git a/mediatek_i2c_spi.c b/mediatek_i2c_spi.c new file mode 100644 index 0000000..41c6d69 --- /dev/null +++ b/mediatek_i2c_spi.c @@ -0,0 +1,510 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2021 The Chromium OS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/i2c-dev.h> +#include <linux/i2c.h> +#include <stdlib.h> +#include <string.h> +#include <sys/ioctl.h> +#include <unistd.h> + +#include "flash.h" +#include "i2c_helper.h" +#include "programmer.h" +#include "spi.h" + +#define ISP_PORT 0x92 >> 1 +#define DEBUG_PORT 0xb2 >> 1 + +#define MTK_CMD_WRITE 0x10 +#define MTK_CMD_READ 0x11 +#define MTK_CMD_END 0x12 + + +struct mediatek_data { + int fd; + unsigned long funcs; +}; + +// Returns null pointer on error. +static const struct mediatek_data* get_data_from_context( + const struct flashctx *flash) +{ + if (!flash || !flash->mst || !flash->mst->spi.data) { + msg_pdbg("Unable to extract data from flash context\n"); + return NULL; + } + return (const struct mediatek_data *)flash->mst->spi.data; +} + +// Returns bytes read, negative value on error. +static int read_raw(const struct mediatek_data* port, uint16_t addr, + uint8_t* buf, size_t len) +{ + int ret; + + if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { + msg_pdbg("Invalid length for read command: %zu\n", len); + return SPI_INVALID_LENGTH; + } + + ret = ioctl(port->fd, I2C_SLAVE, addr); + if (ret) { + msg_pdbg("Failed to set slave address: 0x%02x\n", addr); + return ret; + } + + if (port->funcs & I2C_FUNC_I2C) { + // Use raw I2C read. + uint8_t command = MTK_CMD_READ; + if (write(port->fd, &command, 1) != 1) { + return SPI_GENERIC_ERROR; + } + if (read(port->fd, buf, len) != (int)len) { + return SPI_GENERIC_ERROR; + } + return len; + } + + union i2c_smbus_data data = { + .block[0] = len, + }; + struct i2c_smbus_ioctl_data args = { + .read_write = I2C_SMBUS_READ, + .command = MTK_CMD_READ, + .size = I2C_SMBUS_I2C_BLOCK_DATA, + .data = &data, + }; + ret = ioctl(port->fd, I2C_SMBUS, &args); + if (ret) { + msg_pdbg("Failed to read SMBus I2C block data\n"); + return ret; + } + memcpy(buf, args.data->block + 1, args.data->block[0]); + return args.data->block[0]; +} + +// Returns non-zero value on error. +static int write_command(const struct mediatek_data* port, uint16_t addr, + uint8_t command, const uint8_t* buf, size_t len) +{ + int ret; + + if (len > I2C_SMBUS_BLOCK_MAX) { + msg_pdbg("Invalid length for write command: %zu\n", len); + return SPI_INVALID_LENGTH; + } + + ret = ioctl(port->fd, I2C_SLAVE, addr); + if (ret) { + msg_pdbg("Failed to set slave address: 0x%02x\n", addr); + return ret; + } + + if (port->funcs & I2C_FUNC_I2C) { + // Use raw I2C write. + uint8_t raw_buffer[I2C_SMBUS_BLOCK_MAX + 1]; + raw_buffer[0] = command; + if (len > 0) { + memcpy(raw_buffer + 1, buf, len); + } + if (write(port->fd, raw_buffer, len + 1) != (int)(len + 1)) { + return SPI_GENERIC_ERROR; + } + return 0; + } + + union i2c_smbus_data data = {0}; + struct i2c_smbus_ioctl_data args = { + .read_write = I2C_SMBUS_WRITE, + .command = command, + .data = &data, + }; + + // Special case single byte commands, as empty I2C block data commands + // failed on this component in practice. + if (len == 0) { + args.size = I2C_SMBUS_BYTE; + ret = ioctl(port->fd, I2C_SMBUS, &args); + if (ret) { + msg_pdbg("Failed to write SMBus byte: 0x%02x\n", command); + } + return ret; + } + + args.size = I2C_SMBUS_I2C_BLOCK_DATA; + data.block[0] = len; + if (buf && len) { + memcpy(data.block + 1, buf, len); + } + ret = ioctl(port->fd, I2C_SMBUS, &args); + if (ret) { + msg_pdbg("Failed to write SMBus I2C block data: 0x%02x\n", command); + } + return ret; +} + +// Returns non-zero value on error. +static int write_raw(const struct mediatek_data* port, uint16_t addr, + const uint8_t* buf, size_t len) +{ + if (len < 1) { + msg_pdbg("Invalid write length: %zu\n", len); + return SPI_INVALID_LENGTH; + } + return write_command(port, addr, buf[0], buf + 1, len - 1); +} + +// Read from a GPIO register via debug port. Returns non-zero value on error. +static int mediatek_read_gpio(const struct mediatek_data* port, + uint16_t gpio_addr, uint8_t* value) +{ + int ret; + + uint8_t data[2]; + data[0] = gpio_addr >> 8; + data[1] = gpio_addr & 0xff; + + ret = write_command(port, DEBUG_PORT, MTK_CMD_WRITE, data, 2); + if (ret) { + msg_pdbg("Failed to issue read GPIO command at address 0x%04x\n", gpio_addr); + return ret; + } + + size_t len = 1; + ret = read_raw(port, DEBUG_PORT, value, len); + if (ret < 0) { + msg_pdbg("Failed to read GPIO register at address 0x%04x\n", gpio_addr); + return ret; + } + + if (ret != 1) { + msg_pdbg("GPIO read returned improper length: %d\n", ret); + return SPI_INVALID_LENGTH; + } + + return 0; +} + +// Write to a GPIO register via the debug port. Returns non-zero value on error. +static int mediatek_write_gpio(const struct mediatek_data* port, + uint16_t gpio_addr, uint8_t value) +{ + uint8_t data[3]; + data[0] = gpio_addr >> 8; + data[1] = gpio_addr & 0xff; + data[2] = value; + + return write_command(port, DEBUG_PORT, MTK_CMD_WRITE, data, 3); +} + +// Write a single bit value to a GPIO register via the debug port. Returns +// non-zero value on error. +static int mediatek_set_gpio_bit(const struct mediatek_data* port, + uint16_t gpio_addr, int bit, int value) +{ + int ret; + uint8_t data; + + ret = mediatek_read_gpio(port, gpio_addr, &data); + if (ret) { + msg_pdbg("Failed to read GPIO 0x%04x\n", gpio_addr); + return ret; + } + + if (value) { + data |= (1 << bit); + } else { + data &= ~(1 << bit); + } + + ret = mediatek_write_gpio(port, gpio_addr, data); + if (ret) { + msg_pdbg("Failed to set GPIO 0x%04x to 0x%02x\n", gpio_addr, data); + return ret; + } + return ret; +} + +// Poke the GPIO line that goes to SPI WP# using the MST9U GPIO register +// addresses. Returns non-zero value on error. +static int mediatek_set_write_protect(const struct mediatek_data* port, + int protected) +{ + int ret; + + ret = mediatek_set_gpio_bit(port, 0x426, 7, (protected == 0)); + if (ret) { + msg_perr("Failed to set GPIO out value: %d\n", protected == 0); + return ret; + } + + ret = mediatek_set_gpio_bit(port, 0x428, 7, (protected != 0)); + if (ret) { + msg_perr("Failed to set GPIO enable value: %d\n", protected != 0); + return ret; + } + + return 0; +} + +// Enter serial debug mode using "Option 1" for MST9U and select I2C channel 0 +// to configure write protect GPIOs. Returns non-zero value on error. +static int mediatek_enter_serial_debug_mode(const struct mediatek_data* port) { + int ret; + + unsigned char enter_serial_debug[] = { 'S', 'E', 'R', 'D', 'B' }; + ret = write_raw(port, DEBUG_PORT, enter_serial_debug, + sizeof(enter_serial_debug)); + if (ret) { + msg_perr("Failed to send enter serial debug mode command\n"); + return ret; + } + + unsigned char enter_single_step_1[] = { 0xc0, 0xc1, 0x53 }; + ret = write_command(port, DEBUG_PORT, MTK_CMD_WRITE, + enter_single_step_1, sizeof(enter_single_step_1)); + if (ret) { + msg_perr("Failed to enter serial single step mode (part 1)\n"); + return ret; + } + + unsigned char enter_single_step_2[] = { 0x1f, 0xc1, 0x53 }; + ret = write_command(port, DEBUG_PORT, MTK_CMD_WRITE, enter_single_step_2, + sizeof(enter_single_step_2)); + if (ret) { + msg_perr("Failed to enter serial single step mode (part 2)\n"); + return ret; + } + + // Send each I2C channel 0 configuration byte individually. + unsigned char i2c_channel_0_config[] = + { 0x80, 0x82, 0x84, 0x51, 0x7F, 0x37, 0x61 }; + for (size_t i = 0; i < sizeof(i2c_channel_0_config); ++i) { + ret = write_command( + port, DEBUG_PORT, i2c_channel_0_config[i], NULL, 0); + if (ret) { + msg_perr("Failed to configure i2c channel 0: 0x%02x\n", + i2c_channel_0_config[i]); + return ret; + } + } + + unsigned char enter_single_step_3[] = { 0x00, 0x00, 0x00 }; + ret = write_command(port, DEBUG_PORT, MTK_CMD_WRITE, enter_single_step_3, + sizeof(enter_single_step_3)); + if (ret) { + msg_perr("Failed to enter serial single step mode (part 3)\n"); + return ret; + } + + ret = write_command(port, DEBUG_PORT, 0x35, NULL, 0); + if (ret) { + msg_perr("Failed to send serial debug command (part 1)\n"); + return ret; + } + + ret = write_command(port, DEBUG_PORT, 0x71, NULL, 0); + if (ret) { + msg_perr("Failed to send serial debug command (part 2)\n"); + return ret; + } + + return 0; +} + +// Returns non-zero value on error. +static int mediatek_enter_isp(const struct mediatek_data* port) { + int ret; + + ret = mediatek_enter_serial_debug_mode(port); + if (ret) { + msg_perr("Failed to enter serial debug mode\n"); + return ret; + } + + // MediaTek documentation says to do this twice just in case. + unsigned char enter_isp[] = { 'M', 'S', 'T', 'A', 'R' }; + ret = write_raw(port, ISP_PORT, enter_isp, sizeof(enter_isp)); + if (ret) { + msg_gwarn("Failed to enter ISP mode, trying again\n"); + } + ret = write_raw(port, ISP_PORT, enter_isp, sizeof(enter_isp)); + if (ret) { + msg_gwarn("Might already be in ISP mode, ignoring\n"); + } + + ret = mediatek_set_write_protect(port, 0); + if (ret) { + msg_perr("Failed to disable write protection\n"); + return ret; + } + + return 0; +} + +// Returns non-zero value on error. +static int mediatek_exit_isp(const struct mediatek_data* port) { + int ret; + + ret = mediatek_set_write_protect(port, 1); + if (ret) { + msg_perr("Failed to re-enable write protect\n"); + return ret; + } + + unsigned char exit_single_step[] = { 0xc0, 0xc1, 0xff }; + ret = write_command(port, DEBUG_PORT, MTK_CMD_WRITE, exit_single_step, + sizeof(exit_single_step)); + if (ret) { + msg_perr("Failed to exit single step mode\n"); + return ret; + } + + ret = write_command(port, DEBUG_PORT, 0x34, NULL, 0); + if (ret) { + msg_perr("Failed to exit serial debug mode (1), ignoring\n"); + } + + ret = write_command(port, DEBUG_PORT, 0x45, NULL, 0); + if (ret) { + msg_perr("Failed to exit serial debug mode (2), ignoring\n"); + } + + ret = write_command(port, ISP_PORT, 0x24, NULL, 0); + if (ret) { + msg_perr("Failed to exit ISP mode command, ignoring\n"); + } + + return 0; +} + +static int mediatek_send_command(const struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + const struct mediatek_data* port = get_data_from_context(flash); + if (!port) { + msg_perr("Failed to extract chip data for ISP command\n"); + return SPI_GENERIC_ERROR; + } + + int ret; + + if (writecnt) { + ret = write_command(port, ISP_PORT, MTK_CMD_WRITE, + writearr, writecnt); + if (ret) { + msg_perr("Failed to issue ISP write command\n"); + return ret; + } + } + + if (readcnt) { + size_t len = readcnt; + ret = read_raw(port, ISP_PORT, readarr, len); + if (ret < 0) { + msg_perr("Failed to read ISP command result\n"); + return ret; + } + + if (ret != (int)readcnt) { + msg_perr("Read length mismatched: expected %u got %d\n", readcnt, ret); + return SPI_INVALID_LENGTH; + } + } + + // End the current command. + ret = write_command(port, ISP_PORT, MTK_CMD_END, NULL, 0); + if (ret) { + msg_perr("Failed to end ISP command\n"); + return ret; + } + + return 0; +} + +static const struct spi_master spi_master_i2c_mediatek = { + .max_data_read = I2C_SMBUS_BLOCK_MAX, + // Leave room for 1-byte command and up to a 4-byte address. + .max_data_write = I2C_SMBUS_BLOCK_MAX - 5, + .command = mediatek_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, +}; + +static int mediatek_shutdown(void *data) +{ + int ret = 0; + struct mediatek_data* port = (struct mediatek_data*)data; + + ret |= mediatek_exit_isp(port); + i2c_close(port->fd); + free(data); + + return ret; +} + +static int mediatek_init(void) +{ + int ret; + int fd = i2c_open_from_programmer_params(ISP_PORT, 0); + if (fd < 0) { + msg_perr("Failed to open i2c\n"); + return fd; + } + + struct mediatek_data* port = calloc(1, sizeof(*port)); + if (!port) { + msg_perr("Unable to allocate space for SPI master data\n"); + i2c_close(fd); + return SPI_GENERIC_ERROR; + } + port->fd = fd; + + ret = ioctl(fd, I2C_FUNCS, &(port->funcs)); + if (ret) { + msg_perr("Failed to fetch I2C bus functionality\n"); + free(port); + i2c_close(fd); + return ret; + } + + ret = mediatek_enter_isp(port); + if (ret) { + msg_perr("Failed to enter ISP mode\n"); + free(port); + i2c_close(fd); + return ret; + } + + ret |= register_shutdown(mediatek_shutdown, port); + ret |= register_spi_master(&spi_master_i2c_mediatek, port); + + return ret; +} + +const struct programmer_entry programmer_mediatek_i2c_spi = { + .name = "mediatek_i2c_spi", + .type = OTHER, + .devs.note = "Device files /dev/i2c-*\n", + .init = mediatek_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, +}; diff --git a/meson.build b/meson.build index 4c33bf5..492e5a7 100644 --- a/meson.build +++ b/meson.build @@ -96,6 +96,7 @@ config_usbblaster_spi = get_option('config_usbblaster_spi') config_stlinkv3_spi = get_option('config_stlinkv3_spi') config_lspcon_i2c_spi = get_option('config_lspcon_i2c_spi') +config_mediatek_i2c_spi = get_option('config_mediatek_i2c_spi') config_realtek_mst_i2c_spi = get_option('config_realtek_mst_i2c_spi') config_print_wiki= get_option('print_wiki') config_default_programmer_name = get_option('default_programmer_name') @@ -329,6 +330,10 @@ srcs += 'lspcon_i2c_spi.c' cargs += '-DCONFIG_LSPCON_I2C_SPI=1' endif +if config_mediatek_i2c_spi + srcs += 'mediatek_i2c_spi.c' + cargs += '-DCONFIG_MEDIATEK_I2C_SPI=1' +endif if config_realtek_mst_i2c_spi srcs += 'realtek_mst_i2c_spi.c' cargs += '-DCONFIG_REALTEK_MST_I2C_SPI=1' diff --git a/meson_options.txt b/meson_options.txt index 588ed5b..8022c74 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -40,4 +40,5 @@ option('config_usbblaster_spi', type : 'boolean', value : true, description : 'Altera USB-Blaster dongles') option('config_stlinkv3_spi', type : 'boolean', value : true, description : 'STMicroelectronics STLINK-V3') option('config_lspcon_i2c_spi', type : 'boolean', value : false, description : 'Parade lspcon USB-C to HDMI protocol translator') +option('config_mediatek_i2c_spi', type : 'boolean', value : false, description : 'MediaTek LCD controller') option('config_realtek_mst_i2c_spi', type : 'boolean', value : true, description : 'Realtek MultiStream Transport MST') diff --git a/programmer.h b/programmer.h index 4dd4cad..647d822 100644 --- a/programmer.h +++ b/programmer.h @@ -76,6 +76,7 @@ extern const struct programmer_entry programmer_linux_mtd; extern const struct programmer_entry programmer_linux_spi; extern const struct programmer_entry programmer_lspcon_i2c_spi; +extern const struct programmer_entry programmer_mediatek_i2c_spi; extern const struct programmer_entry programmer_mstarddc_spi; extern const struct programmer_entry programmer_ni845x_spi; extern const struct programmer_entry programmer_nic3com; diff --git a/programmer_table.c b/programmer_table.c index e406f67..2a06c30 100644 --- a/programmer_table.c +++ b/programmer_table.c @@ -128,6 +128,10 @@ &programmer_lspcon_i2c_spi, #endif +#if CONFIG_MEDIATEK_I2C_SPI == 1 + &programmer_mediatek_i2c_spi, +#endif + #if CONFIG_REALTEK_MST_I2C_SPI == 1 &programmer_realtek_mst_i2c_spi, #endif -- To view, visit https://review.coreboot.org/c/flashrom/+/61288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I24adb14e7b4f7160e1c3ff941774064d5a81e820 Gerrit-Change-Number: 61288 Gerrit-PatchSet: 1 Gerrit-Owner: Neill Corlett <corlett(a)google.com> Gerrit-MessageType: newchange

1 0

Change in flashrom[master]: cli_classic.c: Convert do_erase() to libflashrom call
by Nico Huber (Code Review) 21 Jan '22

21 Jan '22

Attention is currently required from: Edward O'Callaghan, Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/60068 ) Change subject: cli_classic.c: Convert do_erase() to libflashrom call ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/60068/comment/60fd215e_fd85dcd3 PS4, Line 12: closer to cli_classic as a pure libflashrom user. > I'm ok with that option too! That FIXME seems like a forever fix me is that actually actionable? I thought about that as well. I'd probably just use a lower message level in case of erase, e.g. warn or info. I'd also be ok with dropping the call. There should be another failure message already, IIRC. -- To view, visit https://review.coreboot.org/c/flashrom/+/60068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8566164e7dbad69cf478b24208014f10fb99e4d0 Gerrit-Change-Number: 60068 Gerrit-PatchSet: 5 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Daniel Campello <campello(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 21 Jan 2022 00:56:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in flashrom[master]: cli_classic.c: Convert do_erase() to libflashrom call
by Edward O'Callaghan (Code Review) 21 Jan '22

21 Jan '22

Attention is currently required from: Nico Huber, Angel Pons. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/60068 ) Change subject: cli_classic.c: Convert do_erase() to libflashrom call ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/60068/comment/64c9319e_42a73b0d PS4, Line 12: closer to cli_classic as a pure libflashrom user. > It does, but kind of by moving CLI code into libflashrom. do_erase() […] I'm ok with that option too! That FIXME seems like a forever fix me is that actually actionable? -- To view, visit https://review.coreboot.org/c/flashrom/+/60068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8566164e7dbad69cf478b24208014f10fb99e4d0 Gerrit-Change-Number: 60068 Gerrit-PatchSet: 5 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Daniel Campello <campello(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 21 Jan 2022 00:47:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

2025

2024

2023

2022

2021

2020

2019

2018

2017

flashrom-gerrit January 2022