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Change subject: Makeile: reenable internal programmer for mipsel
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/61300/comment/92c8255b_322c13e5
PS3, Line 7: Makeile
Make_f_ile
https://review.coreboot.org/c/flashrom/+/61300/comment/25ab0ddc_fe2d21a9
PS3, Line 10: for
Remove this
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Change subject: Makeile: reenable internal programmer for mipsel
......................................................................
Patch Set 3:
(2 comments)
File Makefile:
https://review.coreboot.org/c/flashrom/+/61300/comment/547cfbd6_e5babc55
PS3, Line 104: CONFIG_INTERNAL_MIPSLE \
> Is this actually true?
I haven't looked it up yet
https://review.coreboot.org/c/flashrom/+/61300/comment/64c8059b_ca168f11
PS3, Line 332: # Disable the internal programmer on unsupported architectures (everything but x86 and mipsel)
> Sounds like it compiled with the meson.build by coincidence all the time? […]
The internal programmer should fail at runtime at internal.c:266 processor_flash_enable() which return 1 on non x86 or specific mips and let the init function return also 1, which indicates an error.
The whole point of having CONFIG_INTERNAL_<arch> and not only CONFIG_INTERNAL and CONFIG_INTERNAL_X86 is to be able to have multiple implementations of the internal programmer. The CONFIG_INTERNAL is only an alias for the user.
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Change subject: hwaccess: fix build on non-x86 targets
......................................................................
Patch Set 5: Code-Review-1
(2 comments)
Patchset:
PS1:
> 61276 in particular looks like a nice cleanup of these headers. […]
It doesn't change a thing about the problem at hand, though, that code compiled
for non-x86 includes an x86 file.
Patchset:
PS5:
This is a step backwards, having an `if x86` in an x86 file can't be good.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61300 )
Change subject: Makeile: reenable internal programmer for mipsel
......................................................................
Patch Set 3:
(2 comments)
File Makefile:
https://review.coreboot.org/c/flashrom/+/61300/comment/a5ba1dbd_d97cadbd
PS3, Line 104: CONFIG_INTERNAL_MIPSLE \
Is this actually true?
https://review.coreboot.org/c/flashrom/+/61300/comment/d284d3d3_5073a47c
PS3, Line 332: # Disable the internal programmer on unsupported architectures (everything but x86 and mipsel)
> I think this is overly strict, because the internal programmer will delegate to MTD if enabled, whic […]
Sounds like it compiled with the meson.build by coincidence all the time?
Looking at the code, it seems possible, but there's a shitload of dead,
code not making any sense.
I guess we could have a CONFIG_INTERNAL (with raw mem and libpci (spurious?) dependencies) and CONFIG_INTERNAL_X86 like suggested by this patch. Thomas,
WDYT? For the dependencies, we'd have to disable CONFIG_INTERNAL if
CONFIG_INTERNAL_X86 = no.
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Change subject: hwaccess: fix build on non-x86 targets
......................................................................
Patch Set 5:
(3 comments)
Patchset:
PS1:
> I've started working on an overhaul of the hwaccess code in CB:61275 and CB:61276. […]
61276 in particular looks like a nice cleanup of these headers. Fixing the build regression seems like the important aspect of this change, and calling it a temporary solution until the headers are cleaned up more comprehensively sounds fine to me.
File hwaccess_x86_io.h:
https://review.coreboot.org/c/flashrom/+/61194/comment/3796a02d_fc2baee8
PS4, Line 41: #define HAVE_RGET_IO_PERMS 1
> not needed
Done
File internal.c:
https://review.coreboot.org/c/flashrom/+/61194/comment/4343a592_6843769f
PS4, Line 245: if (rget_io_perms()) {
> You can move this under the x86 guard at line 275. […]
Done
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Hello build bot (Jenkins), Thomas Heijligen, Edward O'Callaghan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/61194
to look at the new patch set (#5).
Change subject: hwaccess: fix build on non-x86 targets
......................................................................
hwaccess: fix build on non-x86 targets
The changes to hwaccess in commit 49d758698a0dd166679c48b1a2785e50e9b0cc83
cause build failure on non-x86 systems because the hwaccess_x86_*
headers are included in some files that are built for all platforms
(particularly those in the internal programmer) and those headers in
turn include <sys/io.h> which only exists on x86.
This change makes the hwaccess_x86 headers a nop on non-x86 platforms so
the internal programmer can be built without errors.
The comment on the stub implementation of rget_io_perms() is also
modified to remove references to non-x86 platforms, since that file is
only built on x86 now.
BUG=None
TEST=meson build succeeds for both x86 and ARM targets
Signed-off-by: Peter Marheine <pmarheine(a)chromium.org>
Change-Id: I20f122679c30340b2c73afd7419e79644ddc3c4e
---
M hwaccess_x86_io.c
M hwaccess_x86_io.h
M hwaccess_x86_msr.h
M internal.c
4 files changed, 14 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/61194/5
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Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61300 )
Change subject: Makeile: reenable internal programmer for mipsel
......................................................................
Patch Set 3:
(1 comment)
File Makefile:
https://review.coreboot.org/c/flashrom/+/61300/comment/df6055da_360b8bcb
PS3, Line 332: # Disable the internal programmer on unsupported architectures (everything but x86 and mipsel)
I think this is overly strict, because the internal programmer will delegate to MTD if enabled, which is supported on more than just x86 and mipsel. For Chromium we use that delegation on ARM, for instance.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/60711 )
Change subject: Add Elkhart Lake support
......................................................................
Patch Set 2: Code-Review+2
(5 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/60711/comment/ddf2ee0b_f024667c
PS2, Line 15: TEST=Read and flash complete flash on Siemens MC EHL1
Some tests with --ifd and writing only specific regions would be nice
to have. This can also happen with an external programmer.
File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/60711/comment/26618e8d_2db36d6d
PS1, Line 709: boot_straps = boot_straps_pch500;
> In EDS there is just SPI defined (bbs=0), whereas bbs=1 is marked as reserved. […]
Hmmm, I was looking at revision 1.3 which says UFS. But I wouldn't mind
to leave it as `reserved`, it feels unlikely to find it in the wild and
we would return BUS_NONE, anyway.
https://review.coreboot.org/c/flashrom/+/60711/comment/46df6eb8_892a62a9
PS1, Line 995: dev
> I guess this would be something for a follow-up patch, right?
Yep, at your convenience. Just something that could be done better for
newer platforms in general. AIUI, at least Tiger Lake could be treated
the same. Don't know actually since when it's not hidden anymore.
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/60711/comment/3ac0ee97_2d88b46f
PS1, Line 1033: return CHIPSET_500_SERIES_TIGER_POINT;
> Yes, I was starring at this code back than for a while. […]
Please also test if it detects the right platform. Should be easy
with ich_descriptors_tool (in util/) run on one of your EHL images ;)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/60711/comment/8d4e0af0_ef3f6085
PS1, Line 2027: ich_gen == CHIPSET_ELKHART_LAKE)) {
> If moved below, something like this? […]
Sounds good.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59742 )
Change subject: tests: Upgrade linux_spi test to run probe lifecycle
......................................................................
Patch Set 4:
(3 comments)
File tests/lifecycle.c:
https://review.coreboot.org/c/flashrom/+/59742/comment/97d87212_96adb405
PS4, Line 18: #include <linux/spi/spidev.h>
> This include seems inevitable... […]
IIRC, we asked this before. It depends on whether we want the tests
to compile everywhere or just on Linux. I think it's fine as is
for now.
If we'd guard the include, we'd also have to guard the function
below that depends on it etc. If we'd want that, it would be better
to put the code into a separate .c file, e.g. one specific to
linux_spi tests (which wouldn't need guards inside, just the build
system should only compile it when needed).
https://review.coreboot.org/c/flashrom/+/59742/comment/f9b3c865_d7e27165
PS4, Line 321: 0x40406b00
Isn't this covered by the include, something like `SPI_IOC_MESSAGE(2)`?
https://review.coreboot.org/c/flashrom/+/59742/comment/564fd459_31a2b6c4
PS4, Line 327: readcnt == 3
Checking the actual command would be more accurate and not much harder,
I guess, e.g. if (msg[0].len == 1 && msg[0].tx_buf[0] == JEDEC_RDID &&
readcnt == 3)
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Change subject: SFDP: drop static table length check to make newer SFDP revisions work
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/60055/comment/eca0edc4_33f2e601
PS1, Line 28: ***RFC*** We could maintain a list of revisions/lengths but is it really
: worth it?
:
> > and that the major version is 1.
>
> That's already checked.
Ack. I missed that the actual action is inside an else-if condition.
> But.....
> According to JESD216 there is a conflict between JESD216 and Intel legacy. It reads like Intel used 1.x, x=[1-4] \o/ I couldn't find *anything* about that, though.......
Well, the code seems to assume legacy Intel has a length of 16. It also seems
unlikely that any newer legacy-Intel version would show up with a higher length.
So we'd just have to maintain the current quirk: always allow length 16 for
major version 1. We allow that already, so it won't get worse.
Checking the minimum length would avoid undefined behavior (accessing bytes
we didn't read). IMO, that's all we have to do. We can either use the minimum
we need (36, currently) or the minimum mandated by the spec. So either
} else if (len != 4 * 4 && len < 9 * 4) {
or trying to be more accurate
} else if (len != 4 * 4 && len < mandated_length[minor_idx]) {
with `minor_idx = MIN(ARRAY_SIZE(mandated_length) - 1, hdrs[i].v_minor);`.
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