Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/55295 )
Change subject: tests: Do not run a test if its driver is not built
......................................................................
tests: Do not run a test if its driver is not built
For all tests that exist as of today, drivers are built by default,
however config options can be disabled and in that case test should
not be run.
Technically, this is done by skipping the test.
BUG=b:181803212
TEST=1) Tested by adding into tests/meson.build
-DCONFIG_xxx=0
4 times (for every driver with test), and then running ninja test
Result: corresponding test is skipped, all other tests are passed
2) Running ninja test with default config settings (everything is
enabled, no overriding in test meson).
Result: all tests are passed.
3) Replacing one of config options in the patch with CONFIG_JLINK_SPI
which is disabled by default.
Result: corresponding test is skipped.
Change-Id: Ic1c48e41f658045a608f46636071f478ba646f77
Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55295
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
---
M tests/init_shutdown.c
1 file changed, 16 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
Angel Pons: Looks good to me, approved
Edward O'Callaghan: Looks good to me, approved
diff --git a/tests/init_shutdown.c b/tests/init_shutdown.c
index 80440bd..48448f8 100644
--- a/tests/init_shutdown.c
+++ b/tests/init_shutdown.c
@@ -34,7 +34,11 @@
void dummy_init_and_shutdown_test_success(void **state)
{
+#if CONFIG_DUMMY == 1
run_lifecycle(state, &programmer_dummy, "bus=parallel+lpc+fwh+spi");
+#else
+ skip();
+#endif
}
struct mec1308_io_state {
@@ -62,6 +66,7 @@
void mec1308_init_and_shutdown_test_success(void **state)
{
+#if CONFIG_MEC1308 == 1
struct mec1308_io_state mec1308_io_state = { 0 };
const struct io_mock mec1308_io = {
.state = &mec1308_io_state,
@@ -75,6 +80,9 @@
run_lifecycle(state, &programmer_mec1308, "");
io_mock_register(NULL);
+#else
+ skip();
+#endif
}
struct ene_lpc_io_state {
@@ -118,6 +126,7 @@
void ene_lpc_init_and_shutdown_test_success(void **state)
{
+#if CONFIG_ENE_LPC == 1
/*
* Current implementation tests for chip ENE_KB932.
* Another chip which is not tested here is ENE_KB94X.
@@ -134,6 +143,9 @@
run_lifecycle(state, &programmer_ene_lpc, "");
io_mock_register(NULL);
+#else
+ skip();
+#endif
}
void linux_spi_init_and_shutdown_test_success(void **state)
@@ -144,5 +156,9 @@
* and the fallback to getpagesize(). This test does the latter (fallback to
* getpagesize).
*/
+#if CONFIG_LINUX_SPI == 1
run_lifecycle(state, &programmer_linux_spi, "dev=/dev/null");
+#else
+ skip();
+#endif
}
--
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Gerrit-Change-Id: Ic1c48e41f658045a608f46636071f478ba646f77
Gerrit-Change-Number: 55295
Gerrit-PatchSet: 6
Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55715 )
Change subject: ite_ec: Implement support for flashing ITE ECs found on TUXEDO laptops
......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS4:
> > Forcing to run the programmer code on an unknown board would be new […]
All other EC drivers were added lately without proper review. That they skip
sanity checks (and documentation too), is the foremost reason why I'm currently
holding a release back. The situation of the superio probing is bad indeed, but
not as bad as starting with EC RAM writes. The comment in probe_superio() proves
the point. IMHO, we should only probe for expected chips, `board_enable` provides
the infrastructure for it.
Patches (also to clean up the superio situation) are welcome of course.
--
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55714 )
Change subject: acpi_ec: Implement basic ACPI embedded controller API
......................................................................
Patch Set 4:
(1 comment)
File acpi_ec.c:
https://review.coreboot.org/c/flashrom/+/55714/comment/851fde2a_a4647fe6
PS4, Line 23: ontrol_port
cmd_port
--
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Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/55695 )
Change subject: ft2232_spi: Revise comments about output pin states
......................................................................
ft2232_spi: Revise comments about output pin states
The meaning of the variables is easy to misunderstand as some
states are merely implicit: All output pins that are not set
in the `cs_bits` mask will be constantly driven low. This may
be sheer coincidence as all programmers that need additional
pins driven use active-low signals to enable buffers.
While other pins stay low, *all* pins set in the `cs_bits`
mask are supposed to be toggled during SPI transactions.
Also drop some irritating dead code and try to explain things
in a comment.
Change-Id: I2b84ede01759c80f69d5ad17e43783d09ecd1107
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55695
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M ft2232_spi.c
1 file changed, 21 insertions(+), 9 deletions(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, approved
diff --git a/ft2232_spi.c b/ft2232_spi.c
index eb98933..0d0c32c 100644
--- a/ft2232_spi.c
+++ b/ft2232_spi.c
@@ -86,15 +86,27 @@
#define BITMODE_BITBANG_NORMAL 1
#define BITMODE_BITBANG_SPI 2
-/* The variables cs_bits and pindir store the values for the "set data bits low byte" MPSSE command that
- * sets the initial state and the direction of the I/O pins. The pin offsets are as follows:
- * SCK is bit 0.
- * DO is bit 1.
- * DI is bit 2.
- * CS is bit 3.
+/*
+ * The variables `cs_bits` and `pindir` store the values for the
+ * "set data bits low byte" MPSSE command that sets the initial
+ * state and the direction of the I/O pins. `cs_bits` pins default
+ * to high and will be toggled during SPI transactions. All other
+ * output pins will be kept low all the time. On exit, all pins
+ * will be reconfigured as inputs.
*
- * The default values (set below in ft2232_spi_init) are used for most devices:
- * value: 0x08 CS=high, DI=low, DO=low, SK=low
+ * The pin offsets are as follows:
+ * TCK/SK is bit 0.
+ * TDI/DO is bit 1.
+ * TDO/DI is bit 2.
+ * TMS/CS is bit 3.
+ * GPIOL0 is bit 4.
+ * GPIOL1 is bit 5.
+ * GPIOL2 is bit 6.
+ * GPIOL3 is bit 7.
+ *
+ * The default values (set below in ft2232_spi_init) are used for
+ * most devices:
+ * value: 0x08 CS=high, DI=low, DO=low, SK=low
* dir: 0x0b CS=output, DI=input, DO=output, SK=output
*/
struct ft2232_data {
@@ -219,7 +231,7 @@
msg_pspew("Assert CS#\n");
buf[i++] = SET_BITS_LOW;
- buf[i++] = 0 & ~spi_data->cs_bits; /* assertive */
+ buf[i++] = 0; /* assert CS# pins, all other output pins stay low */
buf[i++] = spi_data->pindir;
/* WREN, OP(PROGRAM, ERASE), ADDR, DATA */
--
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55715 )
Change subject: ite_ec: Implement support for flashing ITE ECs found on TUXEDO laptops
......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS4:
> Forcing to run the programmer code on an unknown board would be new
to flashrom. I don't see why we would suddenly need that.
I haven't checked all flash drivers in flashrom but I don't remember any DMI checks or anything like that in other ec or superio drivers. Why do we need it now?
--
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Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/55694 )
Change subject: Revert "ft2232_spi: Enhance csgpiol parameter for FT2232"
......................................................................
Revert "ft2232_spi: Enhance csgpiol parameter for FT2232"
This reverts commit ba6575de82f091b97ea0f2efcf2f79ef3739d64f.
Technically, the only thing that is wrong here is the lack of docu-
mentation (manpage update). However, as this change was succeeded by
a regressing fixup patch, it seems likely that the meaning of the
`csgpiol` parameter was just misunderstood and these changes were
not what the author intended.
Change-Id: I460237b9d275b1cd1d8a069f852d17dea393b14e
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55694
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M ft2232_spi.c
1 file changed, 14 insertions(+), 26 deletions(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, approved
diff --git a/ft2232_spi.c b/ft2232_spi.c
index 44975db..eb98933 100644
--- a/ft2232_spi.c
+++ b/ft2232_spi.c
@@ -88,17 +88,10 @@
/* The variables cs_bits and pindir store the values for the "set data bits low byte" MPSSE command that
* sets the initial state and the direction of the I/O pins. The pin offsets are as follows:
- * TCK/SK is bit 0.
- * TDI/DO is bit 1.
- * TDO/DI is bit 2.
- * TMS/CS is bit 3.
- * GPIOL0 is bit 4.
- * GPIOL1 is bit 5.
- * GPIOL2 is bit 6.
- * GPIOL3 is bit 7.
- *
- * The pin signal direction bit offsets follow the same order; 0 means that
- * pin at the matching bit index is an input, 1 means pin is an output.
+ * SCK is bit 0.
+ * DO is bit 1.
+ * DI is bit 2.
+ * CS is bit 3.
*
* The default values (set below in ft2232_spi_init) are used for most devices:
* value: 0x08 CS=high, DI=low, DO=low, SK=low
@@ -459,24 +452,19 @@
}
free(arg);
- /* Allows setting multiple GPIOL states, for example: csgpiol=012 */
arg = extract_programmer_param("csgpiol");
if (arg) {
- unsigned int ngpios = strlen(arg);
- for (unsigned int i = 0; i <= ngpios; i++) {
- int temp = arg[i] - '0';
- if (ngpios == 0 || (ngpios != i && (temp < 0 || temp > 3))) {
- msg_perr("Error: Invalid GPIOLs specified: \"%s\".\n"
- "Valid values are numbers between 0 and 3. "
- "Multiple GPIOLs can be specified.\n", arg);
- free(arg);
- return -2;
- } else {
- unsigned int pin = temp + 4;
- cs_bits |= 1 << pin;
- pindir |= 1 << pin;
- }
+ char *endptr;
+ unsigned int temp = strtoul(arg, &endptr, 10);
+ if (*endptr || endptr == arg || temp > 3) {
+ msg_perr("Error: Invalid GPIOL specified: \"%s\".\n"
+ "Valid values are between 0 and 3.\n", arg);
+ free(arg);
+ return -2;
}
+ unsigned int pin = temp + 4;
+ cs_bits |= 1 << pin;
+ pindir |= 1 << pin;
}
free(arg);
--
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