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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/33521 )
Change subject: layout: Use linked list for `struct romentry`
......................................................................
Patch Set 8:
(2 comments)
File layout.c:
https://review.coreboot.org/c/flashrom/+/33521/comment/0111516e_643ae007
PS8, Line 388: *layout = malloc(sizeof(**layout));
> Given that you memset() the allocated space afterwards, use calloc() instead?
I like to see it explicitly if something is cleared explicitly. I can try
something else, though. Maybe you'll like it better.
https://review.coreboot.org/c/flashrom/+/33521/comment/00d12983_54967aad
PS8, Line 458: if (layout == global_layout)
: return;
:
: while (layout && layout->head) {
: struct romentry *const entry = layout->head;
: layout->head = entry->next;
: free(entry->file);
: free(entry->name);
: free(entry);
: }
: free(layout);
> Given that `layout` is not modified in the while loop, how about evaluating it once? […]
Ack. Might make it less odd to read.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55647 )
Change subject: ich_descriptors: Revise detection for chipsets w/ ICCRIBA
......................................................................
Patch Set 4:
(1 comment)
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/55647/comment/ea3e311a_6d5aeb11
PS3, Line 946: } else if (upper->MDTBA == 0x00) {
> It seems much more invasive, do you want to do it? Anything to do here?
Ping
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Attention is currently required from: Xiang W, Angel Pons.
Hello Xiang W, Angel Pons,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/flashrom/+/55862
to review the following change.
Change subject: [NOTFORMERGE] Add thoughts about bitbang CPOL/CPHA patches
......................................................................
[NOTFORMERGE] Add thoughts about bitbang CPOL/CPHA patches
Change-Id: I6a4b64c686497a7df99ea50273ed90105d669858
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M Documentation/bitbang_spi_analysis.md
1 file changed, 95 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/55862/1
diff --git a/Documentation/bitbang_spi_analysis.md b/Documentation/bitbang_spi_analysis.md
index 293abe5..02196af 100644
--- a/Documentation/bitbang_spi_analysis.md
+++ b/Documentation/bitbang_spi_analysis.md
@@ -148,3 +148,98 @@
This would have to be tested. It even seems possible that raising
`.half_period` above 0 together with this optimization might
increase the speed and reliability.
+
+What happens with CB:49255 (bitbang-spi.c: support clock polarity and phase)
+----------------------------------------------------------------------------
+
+Let's assume the default `cpol = 0`, `cpha = 0`.
+
+ __ h h h h h h h h
+ CS# |_____________________________________
+ ____ ____ ____ ____
+ SCK ______| |___| |___| |___| |_
+
+ MOSI XXXXXXX111111111222222222222222222222222
+
+ MISO XXXXXXXXXXXXXXXXXXXXXX333333333444444444
+ ^ ^
+
+MOSI is off by `.half_period`. It should be sampled right after the
+rising edge of `SCK` where it's unstable. Still, how does it look
+like with `.half_period = 0`?
+
+ __
+ CS# |_____________
+ _ _ _ _
+ SCK ___| || || || |_
+
+ MOSI XXXX111222222222
+
+ MISO XXXXXXXXXX333444
+ ^ ^
+
+Roughly the same, although MISO looks a little tighter. Note that
+the `SCK` pattern is the same now for writing and reading. This is
+because programming `MOSI` happens at the wrong time.
+
+Fixup to CB:49255 (bitbang_spi.c: fix spi sequence in time and rename)
+----------------------------------------------------------------------
+
+ __ h h h h h h h h
+ CS# |_____________________________________
+ ___ ___ ____ ____
+ SCK _______| |____| |___| |___| |_
+
+ MOSI XXXXXX1111111112222222222222222222222222
+
+ MISO XXXXXXXXXXXXXXXXXXXXXX333333333444444444
+ ^ ^
+
+This gives a little more margin to the botched `MOSI` setting. But,
+if looked at with a high `.half_period`, it would still look the
+same. However, with `.half_period = 0`
+
+ __
+ CS# |_____________
+ _ _
+ SCK ____||_||| || |_
+
+ MOSI XXX1112222222222
+
+ MISO XXXXXXXXXX333444
+ ^ ^
+
+things look better. The rising edge of `SCK` aligns again with
+`MOSI`. So the fixup fixes the regression for programmers with
+`.half_period = 0`. Not necessarily for other values.
+
+Let's have a final look at this version for programmers that
+pack the `SCK` setting with programming `MOSI` and sampling
+`MISO`.
+
+ __ h h h h h h h h
+ CS# |_________________________________
+ ___ ___ ___ ___
+ SCK ______| |___| |___| |___| |_
+
+ MOSI XXXXXX111111112222222222222222222222
+
+ MISO XXXXXXXXXXXXXXXXXXXX3333333344444444
+ ^ ^
+
+As things are packed, it's the same as without the fixup. And
+without `.half_period`:
+
+ __
+ CS# |_________
+
+ SCK ___||||||||_
+
+ MOSI XXX112222222
+
+ MISO XXXXXXXX3344
+ ^ ^
+
+`MOSI` is still less likely to be stable at the rising edge of
+`SCK`. For sampling `MISO` it's the same as for current `master`
+(after commit 455a6fc8).
--
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Hello Angel Pons,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/flashrom/+/55860
to review the following change.
Change subject: [DRAFT] Document bitbang SPI thoughts
......................................................................
[DRAFT] Document bitbang SPI thoughts
Change-Id: I2437ad736b6677ad6eefa17a7b2d65d6f489f890
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
A Documentation/bitbang_spi_analysis.md
1 file changed, 150 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/60/55860/1
diff --git a/Documentation/bitbang_spi_analysis.md b/Documentation/bitbang_spi_analysis.md
new file mode 100644
index 0000000..765aeb7
--- /dev/null
+++ b/Documentation/bitbang_spi_analysis.md
@@ -0,0 +1,150 @@
+Analysis of changes to flashrom's `bitbang_spi` driver
+======================================================
+
+* `.half_period` is considered 3 chars long, marked by an `h`.
+
+* Delays incurred by programming or reading a hardware value
+ are 1 char long. So are transmission delays including the
+ time the other endpoint needs to react.
+
+* Assumed is `mode 0`, i.e. `CPOL = 0` and `CPHA = 0`. Changes
+ should happen after a falling edge of `SCK` or `CS#` and
+ sampling after a rising edge of `SCK`.
+
+* `^` denotes a sampling at our end.
+
+Before commit b623f403 (bitbang_spi: Add functions to optimize xfers)
+---------------------------------------------------------------------
+
+ __ h h h h h h h h
+ CS# |_________________________________________
+ ____ ____ ____ ____
+ SCK _______| |____| |____| |____| |_
+
+ MOSI ___11111111112222222222333333333344444444445
+
+ MISO XXXX1111111111222222222233333333334444444444
+ ^ ^ ^ ^
+
+This looks quite balanced actually. Now, what happens if we set
+`.half_period = 0`?
+
+ __
+ CS# |_________________
+ _ _ _ _
+ SCK ____| |_| |_| |_| |_
+
+ MOSI ___11112222333344445
+
+ MISO XXXX1111222233334444
+ ^ ^ ^ ^
+
+Looks ok'ish. Only notice that we sample a little early. It might
+be better to sample after the falling edge of `SCK`, however that
+would make the code incompatible to `.half_period != 0` :-/
+
+With commit b623f403 (bitbang_spi: Add functions to optimize xfers)
+-------------------------------------------------------------------
+
+We explicitly set `SCK = 0` before setting `MOSI` now, which adds
+a tiny delay at the start:
+
+ __ h h h h h h h h
+ CS# |__________________________________________
+ ____ ____ ____ ____
+ SCK ________| |____| |____| |____| |_
+
+ MOSI ____11111111112222222222333333333344444444445
+
+ MISO XXXX11111111111222222222233333333334444444444
+ ^ ^ ^ ^
+
+Nothing to spectacular with `.half_period = 0` either:
+
+ __
+ CS# |__________________
+ _ _ _ _
+ SCK _____| |_| |_| |_| |_
+
+ MOSI ____11112222333344445
+
+ MISO XXXX11111222233334444
+ ^ ^ ^ ^
+
+With commit 455a6fc8 (bitbang_spi: Add half-duplex optimizations)
+-----------------------------------------------------------------
+
+We assume half-duplex from now on. This removes a sampling delay
+per bit on our end during the first, writing phase, and a program-
+ming delay per bit during the second, read phase.
+
+We still program `MOSI = 0` at the start of every byte *read*,
+though. Don't know why. It incurs a programming delay per byte.
+We'll mark this with `o` for odd. We'll also assume bytes are
+only 2 bits long, to not make the diagrams explode.
+
+ __ h h h h h h h h
+ CS# |_______________________________________
+ ___ ___ ____ ____
+ SCK ________| |____| |____| |___| |_
+
+ MOSI ____111111111222222222____________________
+
+ MISO XXXXXXXXXXXXXXXXXXXXXXX3333333333444444444
+ ^ ^
+
+Note that during the write phase, the clock-high periods are
+shorter now, and during the read phase, the clock-lock periods
+are shorter. Now, once again, let's remove the `.half_period`
+delays (vim makes this awesomely easy btw. ^^).
+
+ __
+ CS# |_______________
+ _ _
+ SCK _____||_||_| || ||
+
+ MOSI ____111222________
+
+ MISO XXXXXXXXXXX3333444
+ ^ ^
+
+This looks pretty tense. But remember: everyone is supposed
+to sample after a rising edge of `SCK`. Which is right in the
+center of our `MOSI` output. With `MISO`, however, things
+look bad. This is assuming programming, sampling and a trans-
+mission round-trip all take the same time. *If* the round-trip
+is not longer, we should still be safe.
+
+Making use of 455a6fc8's optimizations
+--------------------------------------
+
+Now what happens if we pack setting `SCK = 0` with setting
+`MOSI` and setting `SCK = 1` with sampling `MISO`?
+
+ __ h h h h h h h h
+ CS# |___________________________________
+ ___ ___ ___ ___
+ SCK ________| |___| |___| |___| |_
+
+ MOSI ____1111111122222222__________________
+
+ MISO XXXXXXXXXXXXXXXXXXXXXX3333333344444444
+ ^ ^
+
+A nice picture once more, but what happens if we ditch
+`.half_period`?
+
+ __
+ CS# |___________
+
+ SCK _____||||||||_
+
+ MOSI ____1122______
+
+ MISO XXXXXXXXXX3344
+ ^ ^
+
+We'd definitely sample very early. Could it work? I don't know.
+This would have to be tested. It even seems possible that raising
+`.half_period` above 0 together with this optimization might
+increase the speed and reliability.
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Change subject: rayer_spi.c: Implement `set_sck_set_mosi`
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Need to think some more about this as I just realized that this driver […]
Hmmm, good point.
CB:49267 and CB:55720 are for nicintel_spi, which sets `.half_delay = 1`. And both were tested by Idwer and me.
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Change subject: rayer_spi.c: Implement `set_sck_set_mosi`
......................................................................
Patch Set 3: -Code-Review
(1 comment)
Patchset:
PS3:
Need to think some more about this as I just realized that this driver
(among others) sets `.half_delay = 0`. This will make things more
susceptible wrt. timing changes.
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Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55715 )
Change subject: ite_ec: Implement support for flashing ITE ECs found on TUXEDO laptops
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS4:
> Oh wow, I wasn't aware of board_enable :O Thanks for that hint. […]
Yeah, I started some work on the Super I/O is preceding patch: 55849
However it is still much to do. The code for Super I/Os is too scattered.
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