zapb has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48379 )
Change subject: jlink_spi: Reduce transfer size
......................................................................
jlink_spi: Reduce transfer size
The maximum transfer size is too large for some devices and
results in an USB timeout.
Change-Id: If2c00b1524ec56740bdfe290096c3546cf375d73
Signed-off-by: Marc Schink <dev(a)zapb.de>
---
M jlink_spi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/48379/1
diff --git a/jlink_spi.c b/jlink_spi.c
index 36611bf..3a73c01 100644
--- a/jlink_spi.c
+++ b/jlink_spi.c
@@ -34,7 +34,7 @@
* Maximum number of bytes that can be transferred at once via the JTAG
* interface, see jaylink_jtag_io().
*/
-#define JTAG_MAX_TRANSFER_SIZE (UINT16_MAX / 8)
+#define JTAG_MAX_TRANSFER_SIZE (32768 / 8)
/*
* Default base frequency in Hz. Used when the base frequency can not be
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Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48879 )
Change subject: sb600spi.c: add rev 0x51 to the leading comment block
......................................................................
sb600spi.c: add rev 0x51 to the leading comment block
Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>
Change-Id: Ic74cff04f2d1fd92ad92aa37f71e5852f02d86a6
---
M sb600spi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/48879/1
diff --git a/sb600spi.c b/sb600spi.c
index ef9da4b..b9560e2 100644
--- a/sb600spi.c
+++ b/sb600spi.c
@@ -127,7 +127,7 @@
* found on both Stoney Ridge and Zen platforms.
*
* The revisions I have found by searching various lspci
- * outputs are as follows: 0x4b, 0x59 & 0x61.
+ * outputs are as follows: 0x4b, 0x51, 0x59 & 0x61.
*/
} else if (rev == 0x4b || rev == 0x51 || rev == 0x59 || rev == 0x61) {
msg_pdbg("Promontory (rev 0x%02x) detected.\n", rev);
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/49489 )
Change subject: flashchips: Mark Macronix MX25L1635D as tested
......................................................................
Patch Set 2: Code-Review+2
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/50263 )
Change subject: flashchips: add definition of the XT25F02E SPI NOR flash
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/50263/comment/820d81f7_8ef98ea1
PS1, Line 19242: TEST_UNTESTED
> It has been tested with https://review.coreboot. […]
If it works properly, then I'd mark it as tested.
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Neil Armstrong has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/50264 )
Change subject: VIA VL805 SPI Flash Bus support
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
> I emailed the log - did it come through? It says it's too big to attach in a reply
yes I received it, thanks
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jmorrison(a)bogomips.com has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/50264 )
Change subject: VIA VL805 SPI Flash Bus support
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
> Great ! Could you share the log ?
I emailed the log - did it come through? It says it's too big to attach in a reply
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Change subject: VIA VL805 SPI Flash Bus support
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
> Working! […]
Great ! Could you share the log ?
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Name of user not set #1003338 has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/50264 )
Change subject: VIA VL805 SPI Flash Bus support
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
Patchset:
PS6:
Working!
flashrom unknown on Linux 4.15.0-130-generic (x86_64)
flashrom was built with libpci 3.5.2, GCC 7.5.0, little endian
Command line (7 args): ./flashrom -VV --programmer vl805 -r test.img -o test.log
Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
Initializing vl805 programmer
Found "VIA VL805" (1106:3483, BDF 01:00.0).
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Change subject: realtek_mst_i2c_spi.c: Move gpio 88 toggle outside write function
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/49785/comment/076eabd5_4e1ff7cc
PS2, Line 9: Gpio 88 toggle is used as write protection disable/enable now
: and we need that to happen at the initialization of programmer.
> Since Shiyu is unavailable and this seems to fix a bug where 'Block protection could not be disabled […]
Alright. Since flashrom patches can be submitted even when there are unresolved comments, let's keep this comment as unresolved until we get a reply from Shiyu.
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