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Change subject: bitbang_spi.c: fix bitbang_spi_send_command to make the delay symmetric
......................................................................
Patch Set 24:
(1 comment)
Patchset:
PS24:
Have anything update?
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Change subject: bitbang-spi.c: support clock polarity and phase
......................................................................
Patch Set 26:
(1 comment)
Patchset:
PS26:
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Change subject: sysfsgpio.c implement spi interface via linux sysfs
......................................................................
Patch Set 17:
(1 comment)
Patchset:
PS17:
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Douglas Anderson has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/50206 )
Change subject: linux_mtd: Switch fopen() to open() for MTD devices
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
How should we proceed here? I don't have a great environment for testing pure upstream flashrom but I'm fairly confident that this will "just work". Should we land it?
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Change subject: flashchips: add definition of the XT25F02E SPI NOR flash
......................................................................
Patch Set 4: Code-Review+2
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Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/50263
to look at the new patch set (#4).
Change subject: flashchips: add definition of the XT25F02E SPI NOR flash
......................................................................
flashchips: add definition of the XT25F02E SPI NOR flash
This adds definition of the XT25F02E 2MBit SPI NOR Flash
from XTX Technology Limited.
This also adds the XTX Technology Limited vendor ID.
Tested (Probe, Erase, Write, Read) with a VL805 USB3.0 bridge.
Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com>
Change-Id: I295633c448c05520e4a6aa09c08bd7c9f2346d54
---
M flashchips.c
M flashchips.h
2 files changed, 38 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/63/50263/4
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Neil Armstrong has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/50263 )
Change subject: flashchips: add definition of the XT25F02E SPI NOR flash
......................................................................
Patch Set 2:
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/50263/comment/2431a1e6_b6541e8f
PS1, Line 19242: TEST_UNTESTED
> If it works properly, then I'd mark it as tested.
Done
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zapb has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48379 )
Change subject: jlink_spi: Reduce transfer size
......................................................................
jlink_spi: Reduce transfer size
The maximum transfer size is too large for some devices and
results in an USB timeout.
Change-Id: If2c00b1524ec56740bdfe290096c3546cf375d73
Signed-off-by: Marc Schink <dev(a)zapb.de>
---
M jlink_spi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/48379/1
diff --git a/jlink_spi.c b/jlink_spi.c
index 36611bf..3a73c01 100644
--- a/jlink_spi.c
+++ b/jlink_spi.c
@@ -34,7 +34,7 @@
* Maximum number of bytes that can be transferred at once via the JTAG
* interface, see jaylink_jtag_io().
*/
-#define JTAG_MAX_TRANSFER_SIZE (UINT16_MAX / 8)
+#define JTAG_MAX_TRANSFER_SIZE (32768 / 8)
/*
* Default base frequency in Hz. Used when the base frequency can not be
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Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48879 )
Change subject: sb600spi.c: add rev 0x51 to the leading comment block
......................................................................
sb600spi.c: add rev 0x51 to the leading comment block
Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>
Change-Id: Ic74cff04f2d1fd92ad92aa37f71e5852f02d86a6
---
M sb600spi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/48879/1
diff --git a/sb600spi.c b/sb600spi.c
index ef9da4b..b9560e2 100644
--- a/sb600spi.c
+++ b/sb600spi.c
@@ -127,7 +127,7 @@
* found on both Stoney Ridge and Zen platforms.
*
* The revisions I have found by searching various lspci
- * outputs are as follows: 0x4b, 0x59 & 0x61.
+ * outputs are as follows: 0x4b, 0x51, 0x59 & 0x61.
*/
} else if (rev == 0x4b || rev == 0x51 || rev == 0x59 || rev == 0x61) {
msg_pdbg("Promontory (rev 0x%02x) detected.\n", rev);
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