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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
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Change subject: libflashrom,writeprotect: add flashrom_wp_{read,write}_chip_config()
......................................................................
libflashrom,writeprotect: add flashrom_wp_{read,write}_chip_config()
The read/write functions map between register values and `struct
wp_chip_state` using the chip's register bit map.
All currently supported chips can be handled with a single pair of
read/write functions, though an option for chips to override them might
be necessary in the future.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
BRANCH=none
Change-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M libflashrom.h
M writeprotect.c
2 files changed, 168 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/58479/20
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Attention is currently required from: Nico Huber, Angel Pons, Nikolai Artemiev, Sergii Dmytruk.
Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58478
to look at the new patch set (#20).
Change subject: flash: add structure to represent chip wp configuration
......................................................................
flash: add structure to represent chip wp configuration
Add `struct flashrom_wp_chip_config` for representing values of all WP
bits in a chip's status register(s).
It allows most WP code to store and manipulate a chip's configuration
without knowing the exact layout of bits in the chip's status registers.
Supporting other chips may require additional fields to be added to the
structure.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
BRANCH=none
Change-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flash.h
1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/58478/20
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58477
to look at the new patch set (#19).
Change subject: flashchips: add writeprotect bit layout map to chips
......................................................................
flashchips: add writeprotect bit layout map to chips
This patch adds a register bit map `struct reg_bit_info`, with fields
for storing the register, bit index, and writability of each bit that
affects the chip's write protection. This allows writeprotect code to be
independent of the register layout of any specific chip. The new fields
have been filled out for example chips.
The representation is centered around describing how bits can be
accessed and modified, rather than the layout of registers. This is
generally easier to work with in code that needs to access specific bits
and typically requires specifying the locations of fewer bits overall.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
BRANCH=none
Change-Id: Id08d77e6d4ca5109c0d698271146d026dbc21284
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flash.h
M flashchips.c
2 files changed, 71 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/58477/19
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59741 )
Change subject: tests: Add run_probe_lifecycle and use it in dummyflasher test
......................................................................
Patch Set 1:
(1 comment)
File tests/lifecycle.c:
https://review.coreboot.org/c/flashrom/+/59741/comment/e4e8dd53_4c312fe3
PS1, Line 53: printf("Testing flashrom_flash_probe for programmer=%s, chip=%s ... \n", prog->name, chip_name);
: assert_int_equal(0, flashrom_flash_probe(&flashctx, flashprog, chip_name));
: printf("... flashrom_flash_probe for programmer=%s successful\n", prog->name);
technically this block is the real meaning of the test and the rest is mostly almost exact the same as run_basic_lifecycle() and so perhaps could we just consume a function pointer into a internal run_lifecycle() function that does the following pattern:
run_lifecylcle():
init()
fx()
deinit()
.
This way all the lifecycle test variants call this with their particular fx() intermediate details such as the above probe block.
This avoids duplication and makes the foundations of this test infrastructure far more extensible for other contributions.
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Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59075 )
Change subject: [RFC][WPTST] tests: test write protection
......................................................................
Patch Set 11:
(3 comments)
File tests/chip_wp.c:
https://review.coreboot.org/c/flashrom/+/59075/comment/ae7c96f8_921ab392
PS11, Line 143: 0x00fff000
> Where does this magic number come from?
It's size of the chip (16 MiB) minus 4 KiB. Made code compute it instead.
https://review.coreboot.org/c/flashrom/+/59075/comment/995f3d67_4a872d7a
PS11, Line 326: assert_int_equal(0x004000, range.start);
: assert_int_equal(0xffc000, range.len);
> Maybe I don't understand this properly, but aren't the values flipped?
In the comment above:
* Multiplaying that by base unit gives 16 KiB protected region at the
* bottom, which is then complemented.
So the values are correct. This is the protected range and it starts at 16 KiB and goes until the end of the chip 16 MiB. I've added that "bottom" means start of the chip.
https://review.coreboot.org/c/flashrom/+/59075/comment/4adbb025_385c9584
PS11, Line 391: 0x1000
> Sorry I have just realised, for this test to work as expected range. […]
Done
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