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Hello build bot (Jenkins), Nico Huber, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/59709
to look at the new patch set (#4).
Change subject: [RFC][OTP] spi25_statusreg: support reading/writing security register
......................................................................
[RFC][OTP] spi25_statusreg: support reading/writing security register
Not to be confused with "secure registers" of OTP.
Security register is a dedicated status register for security-related
bits. You don't write its value directly, issuing corresponding write
command with no data just sets OTP bit to 1 automatically.
No WREN is necessary, but at least some datasheets indicate BUSY state
after write command.
Unlike cases where OTP bit is part of SR and can only be written while
in OTP mode, security register can only be written outside of the mode.
Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M flash.h
M spi.h
M spi25_statusreg.c
3 files changed, 58 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/59709/4
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Gerrit-Change-Number: 59709
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Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58479 )
Change subject: libflashrom,writeprotect: add flashrom_wp_{read,write}_chip_config()
......................................................................
Patch Set 20:
(3 comments)
File writeprotect.c:
https://review.coreboot.org/c/flashrom/+/58479/comment/d455cae1_2e3e3d13
PS16, Line 113: }
> Loop body is one line so braces around loop body are not needed. And same for the loop right below. […]
Done
File writeprotect.c:
https://review.coreboot.org/c/flashrom/+/58479/comment/807a1ee5_3cb38bc2
PS18, Line 159: int
> unsigned ?
It's counting down, `i` needs to get to -1 for the exit condition to evaluate to true.
https://review.coreboot.org/c/flashrom/+/58479/comment/595c0839_f707ef94
PS18, Line 171: int
> ditto
ditto.
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Attention is currently required from: Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk.
Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59529 )
Change subject: spi25_statusreg: delete read_status_register()
......................................................................
Patch Set 10:
(2 comments)
File spi25.c:
https://review.coreboot.org/c/flashrom/+/59529/comment/e6c85789_bf3f0aa1
PS9, Line 312: return 0;
> Conditional body should be on new line.
Done
File spi25_statusreg.c:
https://review.coreboot.org/c/flashrom/+/59529/comment/10687112_39ac10e4
PS9, Line 217: return 1;
> Sorry I know there are so many lines like this in the file, can we propagate error code in all of th […]
Done
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Attention is currently required from: Nico Huber, Angel Pons, Nikolai Artemiev, Sergii Dmytruk.
Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58477
to look at the new patch set (#19).
Change subject: flashchips: add writeprotect bit layout map to chips
......................................................................
flashchips: add writeprotect bit layout map to chips
This patch adds a register bit map `struct reg_bit_info`, with fields
for storing the register, bit index, and writability of each bit that
affects the chip's write protection. This allows writeprotect code to be
independent of the register layout of any specific chip. The new fields
have been filled out for example chips.
The representation is centered around describing how bits can be
accessed and modified, rather than the layout of registers. This is
generally easier to work with in code that needs to access specific bits
and typically requires specifying the locations of fewer bits overall.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
BRANCH=none
Change-Id: Id08d77e6d4ca5109c0d698271146d026dbc21284
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flash.h
M flashchips.c
2 files changed, 71 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/58477/19
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Attention is currently required from: Nico Huber, Angel Pons, Nikolai Artemiev, Sergii Dmytruk.
Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58478
to look at the new patch set (#20).
Change subject: flash: add structure to represent chip wp configuration
......................................................................
flash: add structure to represent chip wp configuration
Add `struct flashrom_wp_chip_config` for representing values of all WP
bits in a chip's status register(s).
It allows most WP code to store and manipulate a chip's configuration
without knowing the exact layout of bits in the chip's status registers.
Supporting other chips may require additional fields to be added to the
structure.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
BRANCH=none
Change-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flash.h
1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/58478/20
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Attention is currently required from: Nico Huber, Angel Pons, Nikolai Artemiev, Sergii Dmytruk.
Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58479
to look at the new patch set (#20).
Change subject: libflashrom,writeprotect: add flashrom_wp_{read,write}_chip_config()
......................................................................
libflashrom,writeprotect: add flashrom_wp_{read,write}_chip_config()
The read/write functions map between register values and `struct
wp_chip_state` using the chip's register bit map.
All currently supported chips can be handled with a single pair of
read/write functions, though an option for chips to override them might
be necessary in the future.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
BRANCH=none
Change-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M libflashrom.h
M writeprotect.c
2 files changed, 168 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/58479/20
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