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Change subject: flashchips: enable write-protection for W25Q{64,128}.V
......................................................................
Patch Set 15:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/59071/comment/8270980f_85d83b48
PS15, Line 9: W25Q64
Which version specifically?
Patchset:
PS15:
So, there are two wrinkles with these Winbond chips:
1. Newer versions with an additional, 3rd status register
and WPS feature re-use the older RDID numbers.
2. To support write-protection on these newer chips, the
code needs to be extended with WPS support first (for a
start it would be enough to ensure the WPS bit is 0, we
could extend the API for individual block protection later).
So far the only solution I see for 1. is to split the entries
in `flashchip.c`. So for W25Q64.V this would become two
entries, one for W25Q64BV/W25Q64CV/W25Q64FV w/o WPS
support and one for W25Q64JV w/ WPS support (or w/o
write-protect support for now).
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Change subject: writeprotect: print chip range truth table for debugging
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
File writeprotect.c:
https://review.coreboot.org/c/flashrom/+/59909/comment/c284f6ab_87dc43c3
PS5, Line 283: dbg
IMO, `dbg2` or even `spew` would fit better here. I guess this can
fill multiple pages of a terminal?
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Change subject: ite_ec: Implement support for flashing ITE ECs found on TUXEDO laptops
......................................................................
Patch Set 25:
(1 comment)
File ite_ecfw.c:
https://review.coreboot.org/c/flashrom/+/55715/comment/5243ac21_e5e0d967
PS25, Line 335: sens
sense
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Change subject: ite_ec: Implement support for flashing ITE ECs found on TUXEDO laptops
......................................................................
Patch Set 25:
(1 comment)
File ite_ecfw.c:
https://review.coreboot.org/c/flashrom/+/55715/comment/54538c11_7ec726de
PS25, Line 337: The datasheet says
: * this bit should always be 1 (internal clock source).
the IT5570E datasheet says that but this code is meant to work with other ITE ECs, too, where this is not true
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Change subject: ite_ec: Implement support for flashing ITE ECs found on TUXEDO laptops
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Patch Set 25:
(1 comment)
File ite_ecfw.c:
https://review.coreboot.org/c/flashrom/+/55715/comment/a20e2844_b24f69b4
PS20, Line 332: if (blocks_1_2) {
: itestring->flags.clock_source = CLOCK_SOURCE_INTERNAL;
:
> Added the comment
I still don't see how clock source and block count are related. Force the internal clock doesn't make any sense when there is a external crystal
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Change subject: libflashrom,writeprotect: add flashrom_wp_{read,write}_chip_config()
......................................................................
Patch Set 22:
(1 comment)
Patchset:
PS22:
> I first thought the API is missing a function to create a new `config` […]
Thinking further about this, there are more reasons to tie
flash context and wp config together. The current internal
representation is actually only valid for a specific chip
model (it's storing the exact bits found on the chip; same
bit values could have a different meaning for another chip).
Completely different idea: we could pass an abstract (decoded)
config around instead of the current bit representation. Just
like one would deserialize data from a byte stream and use
a better, program-specific representation and only serialize
it again for writing.
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Change subject: libflashrom,writeprotect: add flashrom_wp_{read,write}_chip_config()
......................................................................
Patch Set 22:
(1 comment)
Patchset:
PS22:
I first thought the API is missing a function to create a new `config`
(currently you always have to start by reading the existing one). However,
it seems this is intentional and I learned later that some code relies on
this (I haven't fully understood why yet / couldn't find a chip that mixes
OTP bits in). This brings us to another problem: Given this limitation,
the config "objects" are actually tied to the flash context they were
created with. For instance, you can't just clone a config from one chip
to another by writing a config object of the former to the latter. I hope
I got this right?
Neither does the documentation mention this limitation nor is the API
user forced to do the right thing in any way. I could think of a simple
way to achieve the latter. Instead of exposing the `flashrom_wp_chip_config`
we could use a `flashrom_wp_context` that links to the flash context (and
remove the flash context argument from all but the read function). But I'm
not convinced of this idea yet...
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Change subject: spi25_statusreg: inline spi_write_register_flag()
......................................................................
Patch Set 13:
(1 comment)
Patchset:
PS13:
What is gained by this? Commit message doesn't state a reason.
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Change subject: libflashrom,writeprotect: add flashrom_wp_{config,range,mode}_to_str()
......................................................................
Patch Set 25:
(2 comments)
File libflashrom.h:
https://review.coreboot.org/c/flashrom/+/58484/comment/238e3f85_cf90f5ac
PS25, Line 138: arbitrary
It definitely has a minimum. It's hard to get right without leaking
information about the implementation. It also raises questions, what
if a newer version of the library supports more config bits? we'd
have to start versioning the API... at least we should pass the size
of the destination string as another argument.
IMO, much better to allocate the string inside libflashrom.
File writeprotect.c:
https://review.coreboot.org/c/flashrom/+/58484/comment/e6faa3c1_e075bf88
PS25, Line 466: }
This leaks internal information, it looks much like debugging code TBH.
IIRC, I've seen some discussion about debug output later in the queue.
IMO, it seems right to log things in internal code. A CLI is always
limited in what it can present, and that's ok as it should present things
to a humble user. Information that is only useful for developers would
land in the log, is that a bad idea?
Not sure about the other two functions below. On one hand they seem
convenient, on the other they don't do anything the CLI code coudn't do.
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Change subject: libflashrom,writeprotect: add flashrom_wp_{get,set}_mode()
......................................................................
Patch Set 25:
(7 comments)
File libflashrom.h:
https://review.coreboot.org/c/flashrom/+/58483/comment/a1f22da1_22bcc989
PS25, Line 148: const
In a forward declaration, `const` as a qualifier of a parameter (i.e.
not a qualifier for something a parameter points to) is meaningless.
Arguments are always passed by value and it doesn't matter to the
caller if the callee will change its own copy.
File writeprotect.c:
https://review.coreboot.org/c/flashrom/+/58483/comment/07996cb6_a828b109
PS25, Line 374:
Spurious line break?
https://review.coreboot.org/c/flashrom/+/58483/comment/913a7999_7dbb0a33
PS25, Line 406: const
This is correct usage of `const`. It tells the compiler and the reader
that the intention is not to change the value.
https://review.coreboot.org/c/flashrom/+/58483/comment/e9c794e6_2c3ffd39
PS25, Line 410: return 1;
Wouldn't it be a success if `mode == WP_MODE_DISABLE`?
https://review.coreboot.org/c/flashrom/+/58483/comment/5b83f455_3256f89f
PS25, Line 412: f(
Missing space. Could be a `switch/case` though.
https://review.coreboot.org/c/flashrom/+/58483/comment/f08b91a4_0beccf53
PS25, Line 420: f(
Missing space.
https://review.coreboot.org/c/flashrom/+/58483/comment/7ae43c15_9a5c026a
PS25, Line 437: }
I wonder if it's a good idea to have SRP bits in an array. The intention
is unclear. Is `srp_bit_count` only used to decide if SRP1 is exists? or
does it prepare for more than 2 SRP bits? It seems the code would overall
be more clear if we had separate bit definitions named by what we expect
them to do. For instance, we expect SRP0 to always control the hardware
write protection, so why not call it `hwwp` or something like that?
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