December 2021 - flashrom-gerrit

Change in flashrom[master]: dummyflasher: make RO status of SPI_SR_WEL explicit
by Sergii Dmytruk (Code Review) 19 Dec '21

19 Dec '21

Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/60224 ) Change subject: dummyflasher: make RO status of SPI_SR_WEL explicit ...................................................................... dummyflasher: make RO status of SPI_SR_WEL explicit It was read-only before this commit because it's reset at the bottom of emulate_spi_chip_response() for any command that's not WREN or EWSR. However, the code looked like it could be set by WRSR. This also adds a test which passes with and without this commit, but is probably still useful for the peace of mind. Change-Id: I5dce77e22a1f9cd29f40ec0881d2b1238a985e97 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M dummyflasher.c A tests/dummyflasher.c M tests/meson.build M tests/tests.c M tests/tests.h 5 files changed, 103 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/24/60224/1 diff --git a/dummyflasher.c b/dummyflasher.c index 2311576..5f393f9 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -317,7 +317,7 @@ break; } /* FIXME: add some reasonable simulation of the busy flag */ - data->emu_status = writearr[1] & ~SPI_SR_WIP; + data->emu_status = writearr[1] & ~(SPI_SR_WEL | SPI_SR_WIP); msg_pdbg2("WRSR wrote 0x%02x.\n", data->emu_status); break; case JEDEC_READ: diff --git a/tests/dummyflasher.c b/tests/dummyflasher.c new file mode 100644 index 0000000..e7e9694 --- /dev/null +++ b/tests/dummyflasher.c @@ -0,0 +1,93 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2021 3mdeb Embedded Systems Consulting + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <include/test.h> +#include <stdlib.h> +#include <string.h> + +#include "chipdrivers.h" +#include "flash.h" +#include "programmer.h" +#include "spi.h" + +static void setup_chip(struct flashrom_flashctx *flashctx, struct flashchip *chip, const char *programmer_param) +{ + flashctx->chip = chip; + + assert_int_equal(0, programmer_init(&programmer_dummy, programmer_param)); + + /* Assignment below normally happens while probing, but this test is not probing. */ + flashctx->mst = &registered_masters[0]; +} + +static void teardown(void) +{ + assert_int_equal(0, programmer_shutdown()); +} + +/* Setup the struct for W25Q128.V, all values come from flashchips.c */ +static const struct flashchip chip_W25Q128_V = { + .vendor = "aklm&dummyflasher", + .total_size = 16 * 1024, + .tested = TEST_OK_PREW, + .read = spi_chip_read, + .write = spi_chip_write_256, + .unlock = spi_disable_blockprotect, + .page_size = 256, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, +}; + +void wel_is_ro_in_dummyflasher_test_success(void **state) +{ + (void) state; /* unused */ + + struct flashrom_flashctx flashctx = { 0 }; + struct flashchip mock_chip = chip_W25Q128_V; + /* + * Dummyflasher is capable to emulate W25Q128.V, so we ask it to do this. + * Nothing to mock, dummy is taking care of this already. + */ + char *param_dup = strdup("bus=spi,emulate=W25Q128FV"); + + setup_chip(&flashctx, &mock_chip, param_dup); + + const uint8_t status = spi_read_status_register(&flashctx) & SPI_SR_WEL; + assert_int_equal(0, status & SPI_SR_WEL); + + assert_int_equal(0, spi_write_status_register(&flashctx, status | SPI_SR_WEL)); + assert_int_equal(0, spi_read_status_register(&flashctx) & SPI_SR_WEL); + + teardown(); + + free(param_dup); +} diff --git a/tests/meson.build b/tests/meson.build index 5bb6ac9..b2ff313 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -23,6 +23,7 @@ 'init_shutdown.c', 'layout.c', 'chip.c', + 'dummyflasher.c', ] mocks = [ diff --git a/tests/tests.c b/tests/tests.c index a4a312e..164a770 100644 --- a/tests/tests.c +++ b/tests/tests.c @@ -379,5 +379,10 @@ }; ret |= cmocka_run_group_tests_name("chip.c tests", chip_tests, NULL, NULL); + const struct CMUnitTest dummyflasher_tests[] = { + cmocka_unit_test(wel_is_ro_in_dummyflasher_test_success), + }; + ret |= cmocka_run_group_tests_name("dummyflasher.c tests", dummyflasher_tests, NULL, NULL); + return ret; } diff --git a/tests/tests.h b/tests/tests.h index 16974af..a5f5380 100644 --- a/tests/tests.h +++ b/tests/tests.h @@ -65,4 +65,7 @@ void write_chip_test_success(void **state); void write_chip_with_dummyflasher_test_success(void **state); +/* dummyflasher.c */ +void wel_is_ro_in_dummyflasher_test_success(void **state); + #endif /* TESTS_H */ -- To view, visit https://review.coreboot.org/c/flashrom/+/60224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5dce77e22a1f9cd29f40ec0881d2b1238a985e97 Gerrit-Change-Number: 60224 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: dummyflasher: add SR2 emulation harness
by Nico Huber (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Angel Pons, Nikolai Artemiev, Sergii Dmytruk. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59072 ) Change subject: dummyflasher: add SR2 emulation harness ...................................................................... Patch Set 18: (2 comments) File dummyflasher.c: https://review.coreboot.org/c/flashrom/+/59072/comment/8f272bc0_278d9f64 PS16, Line 339: data->emu_status[0] &= ro_bits; > WIP was RO before, old code is: […] And what does that tell us about the state of WIP after that line? AFAICT, it was always cleared here. Does it matter? I guess no, but I had to investigate (check all accesses to `emu_status` basically). It's just so much nicer to investigate such things for dedicated commits :) I guess changing this single line, no matter how minor it seems, makes about 50% of the review of this change (and it's not a small change). https://review.coreboot.org/c/flashrom/+/59072/comment/433daacc_c06c9d76 PS16, Line 347: other chips might differ > At least datasheet for W25Q128FV claims otherwise in its note on previous generations: […] So we actually know already that chips with different behavior exist. That's already more information than the comment provides :) If that is the reason for the comment, please rephrase. Anyway, what I meant is that there can always be chips that act differently. That's the case for WRSR, but also for WRSR2, and also, less likely, for read/write/erase commands. -- To view, visit https://review.coreboot.org/c/flashrom/+/59072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59 Gerrit-Change-Number: 59072 Gerrit-PatchSet: 18 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Sun, 19 Dec 2021 12:27:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: comment

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Change in flashrom[master]: dummyflasher: emulate SR2 for W25Q128FV
by Nico Huber (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Angel Pons, Sergii Dmytruk. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59073 ) Change subject: dummyflasher: emulate SR2 for W25Q128FV ...................................................................... Patch Set 18: (1 comment) File dummyflasher.c: https://review.coreboot.org/c/flashrom/+/59073/comment/f14a8972_b6a9a31c PS16, Line 180: } > We can't generalize this. […] Yes, needs custom code ofc. It's just a question where that code is placed. I was thinking about the chip selection, because the code is already chip specific. But you are right, we'd need more chip-specific code anyway. Either here or whenever the bit mask would get updated. -- To view, visit https://review.coreboot.org/c/flashrom/+/59073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I79f9b4a0b604663d3288ad70dcbe3ea4075dede5 Gerrit-Change-Number: 59073 Gerrit-PatchSet: 18 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Sun, 19 Dec 2021 12:04:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: comment

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Change in flashrom[master]: ichspi: Extract handling programmer param into a function
by Felix Singer (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Nikolai Artemiev. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58736 ) Change subject: ichspi: Extract handling programmer param into a function ...................................................................... Patch Set 1: (1 comment) File ichspi.c: https://review.coreboot.org/c/flashrom/+/58736/comment/83f77320_52f4f2b7 PS1, Line 1761: if (arg && !strcmp(arg, "hwseq")) { > If you have any idea how to achieve that in C, please in a separate commit. Oh, forgot that this is not possible in C. I have another idea, but that requires way more refactoring. Sorry for blocking. Done. -- To view, visit https://review.coreboot.org/c/flashrom/+/58736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I20e2379a6fd58c9346f0a2d6daf2b8decf1f6976 Gerrit-Change-Number: 58736 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Sat, 18 Dec 2021 22:43:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in flashrom[master]: flashchips: enable write-protection for W25Q{64,128}.V
by Sergii Dmytruk (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Nico Huber, Angel Pons, Anastasia Klimchuk. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59071 ) Change subject: flashchips: enable write-protection for W25Q{64,128}.V ...................................................................... Patch Set 15: (2 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/59071/comment/9c3577b1_2c8e9c5b PS15, Line 9: W25Q64 > Which version specifically? W25Q64FV Patchset: PS15: > So, there are two wrinkles with these Winbond chips: […] OK, I'll add: * SR3 support * WPS bit definition and setting it to 0 * separate chip definition * SR3 emulation (probably in SR2 patches) -- To view, visit https://review.coreboot.org/c/flashrom/+/59071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iccb69a8d3a0dd2192e2c938caddaf07b1889ed35 Gerrit-Change-Number: 59071 Gerrit-PatchSet: 15 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Sat, 18 Dec 2021 22:19:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in flashrom[master]: [RFC][OTP] tests: test OTP with security register
by Sergii Dmytruk (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Nico Huber, Angel Pons, Sergii Dmytruk. Hello build bot (Jenkins), Nico Huber, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/59713 to look at the new patch set (#10). Change subject: [RFC][OTP] tests: test OTP with security register ...................................................................... [RFC][OTP] tests: test OTP with security register Change-Id: Ib0e4d948a200d0cf1e670d67623f7087005d5d39 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M tests/chip_otp.c M tests/tests.c M tests/tests.h 3 files changed, 95 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/13/59713/10 -- To view, visit https://review.coreboot.org/c/flashrom/+/59713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib0e4d948a200d0cf1e670d67623f7087005d5d39 Gerrit-Change-Number: 59713 Gerrit-PatchSet: 10 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: [RFC][OTP] flashchips,otp: support MX25L6436E "family"
by Sergii Dmytruk (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Nico Huber, Angel Pons, Sergii Dmytruk. Hello build bot (Jenkins), Nico Huber, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/59712 to look at the new patch set (#10). Change subject: [RFC][OTP] flashchips,otp: support MX25L6436E "family" ...................................................................... [RFC][OTP] flashchips,otp: support MX25L6436E "family" Also includes MX25L6445E, MX25L6465E, MX25L6473E and MX25L6473F. It's emulated by dummy flasher and will be used in tests. Change-Id: I7e9dbef8632d8a1ef9322286b5fb1c0b47e8007e Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M flashchips.c M otp.h M otp_layouts.c 3 files changed, 23 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/12/59712/10 -- To view, visit https://review.coreboot.org/c/flashrom/+/59712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7e9dbef8632d8a1ef9322286b5fb1c0b47e8007e Gerrit-Change-Number: 59712 Gerrit-PatchSet: 10 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: [RFC][OTP] otp: support 2-bit locks
by Sergii Dmytruk (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Nico Huber, Angel Pons, Sergii Dmytruk. Hello build bot (Jenkins), Nico Huber, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/59711 to look at the new patch set (#10). Change subject: [RFC][OTP] otp: support 2-bit locks ...................................................................... [RFC][OTP] otp: support 2-bit locks Change-Id: I0593724901a0e354f1016405577f60ac82d4b14c Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M otp.c M otp.h 2 files changed, 24 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/11/59711/10 -- To view, visit https://review.coreboot.org/c/flashrom/+/59711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0593724901a0e354f1016405577f60ac82d4b14c Gerrit-Change-Number: 59711 Gerrit-PatchSet: 10 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: [RFC][OTP] dummyflasher: implement SCUR and OTP for MX25L6436
by Sergii Dmytruk (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Nico Huber, Angel Pons, Sergii Dmytruk. Hello build bot (Jenkins), Nico Huber, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/59710 to look at the new patch set (#10). Change subject: [RFC][OTP] dummyflasher: implement SCUR and OTP for MX25L6436 ...................................................................... [RFC][OTP] dummyflasher: implement SCUR and OTP for MX25L6436 The chip has OTP mode, but state of OTP is stored in a security register. Additions: * spi_scur parameter for dummyflasher to configure initial state of security register * commands for entering/leaving OTP mode (ENSO, EXSO) * commands for reading/writing secure register (RDSCUR, WRSCUR) Change-Id: I13716d597d305351ec27d532e9020615c397693a Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M dummyflasher.c M flashrom.8.tmpl M spi.h 3 files changed, 84 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/10/59710/10 -- To view, visit https://review.coreboot.org/c/flashrom/+/59710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I13716d597d305351ec27d532e9020615c397693a Gerrit-Change-Number: 59710 Gerrit-PatchSet: 10 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: [RFC][OTP] spi25_statusreg: support reading/writing security register
by Sergii Dmytruk (Code Review) 18 Dec '21

18 Dec '21

Attention is currently required from: Nico Huber, Angel Pons, Sergii Dmytruk. Hello build bot (Jenkins), Nico Huber, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/59709 to look at the new patch set (#10). Change subject: [RFC][OTP] spi25_statusreg: support reading/writing security register ...................................................................... [RFC][OTP] spi25_statusreg: support reading/writing security register Not to be confused with "secure registers" of OTP. Security register is a dedicated status register for security-related bits. You don't write its value directly, issuing corresponding write command with no data just sets OTP bit to 1 automatically. No WREN is necessary, but at least some datasheets indicate BUSY state after write command. Unlike cases where OTP bit is part of SR and can only be written while in OTP mode, security register can only be written outside of the mode. Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M flash.h M spi.h M spi25_statusreg.c 3 files changed, 58 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/59709/10 -- To view, visit https://review.coreboot.org/c/flashrom/+/59709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae Gerrit-Change-Number: 59709 Gerrit-PatchSet: 10 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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flashrom-gerrit December 2021