December 2021 - flashrom-gerrit

Change in flashrom[master]: ichspi: Extract initialisation of swseq and hwseq into a function
by Anastasia Klimchuk (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Angel Pons, Anastasia Klimchuk, Nikolai Artemiev. Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Nikolai Artemiev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/58737 to look at the new patch set (#2). Change subject: ichspi: Extract initialisation of swseq and hwseq into a function ...................................................................... ichspi: Extract initialisation of swseq and hwseq into a function Initialisation of swseq_data and hwseq_data gets its own function, which is called from init_ich_default. This makes init_ich_default more readable. This patch also gives a name to (previously anonymous) struct swseq_data. Its sibling struct hwseq_data already has a name. Structs need names to be able to declare function parameters. TEST ME ON HW BUG=b:204488958 Change-Id: I7d62b1b380e497b82dcae1284d752204cc541bd3 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M ichspi.c 1 file changed, 57 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/37/58737/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/58737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7d62b1b380e497b82dcae1284d752204cc541bd3 Gerrit-Change-Number: 58737 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: ichspi: Extract handling programmer param into a function
by Anastasia Klimchuk (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Nikolai Artemiev. Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Nikolai Artemiev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/58736 to look at the new patch set (#2). Change subject: ichspi: Extract handling programmer param into a function ...................................................................... ichspi: Extract handling programmer param into a function Extract processing of ich_spi_mode into a separate function which is called from init_ich_default. This makes init_ich_default more readable and avoids one local variable. TEST ME ON HW BUG=b:204488958 Change-Id: I20e2379a6fd58c9346f0a2d6daf2b8decf1f6976 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M ichspi.c 1 file changed, 37 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/36/58736/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/58736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I20e2379a6fd58c9346f0a2d6daf2b8decf1f6976 Gerrit-Change-Number: 58736 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: ichspi: Split very long init function into two
by Anastasia Klimchuk (Code Review) 21 Dec '21

21 Dec '21

Attention is currently required from: Felix Singer, Nico Huber, Edward O'Callaghan, Anastasia Klimchuk, Nikolai Artemiev. Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Nikolai Artemiev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/58735 to look at the new patch set (#2). Change subject: ichspi: Split very long init function into two ...................................................................... ichspi: Split very long init function into two ich_init_spi is very long, but logically it can be split. Init function detects the chipset and then the rest of operations depends on the chipset. Init function is more readable now, it consists of only a switch. Initialisation of hwseq and swseq that used to happen in the beginning of init function now moved to init_ich_default, because hwseq and swseq are only used for chipsets served by init_ich_default. TEST ME ON DEVICE BUG=b:204488958 Change-Id: I6789bc456a4878e6555831ae0b80ecbdbf62938b Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M ichspi.c 1 file changed, 269 insertions(+), 255 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/35/58735/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/58735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6789bc456a4878e6555831ae0b80ecbdbf62938b Gerrit-Change-Number: 58735 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: libflashrom,writeprotect: add flashrom_wp_{read,write}_chip_config()
by Angel Pons (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Nico Huber, Edward O'Callaghan, Anastasia Klimchuk, Nikolai Artemiev, Sergii Dmytruk. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58479 ) Change subject: libflashrom,writeprotect: add flashrom_wp_{read,write}_chip_config() ...................................................................... Patch Set 22: (1 comment) File libflashrom.h: https://review.coreboot.org/c/flashrom/+/58479/comment/0ecb6de2_a8712be1 PS11, Line 4: 2010 > Sounds about right. Generally it's the year of the _first_ publication of […] I'd use SPDX license headers as done for coreboot, this avoids having to deal with copyright years 😄 -- To view, visit https://review.coreboot.org/c/flashrom/+/58479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad Gerrit-Change-Number: 58479 Gerrit-PatchSet: 22 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Mon, 20 Dec 2021 11:48:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Nikolai Artemiev <nartemiev(a)google.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: libflashrom,writeprotect: add flashrom_wp_{read,write}_chip_config()
by Nico Huber (Code Review) 20 Dec '21

20 Dec '21

Attention is currently required from: Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Nikolai Artemiev, Sergii Dmytruk. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58479 ) Change subject: libflashrom,writeprotect: add flashrom_wp_{read,write}_chip_config() ...................................................................... Patch Set 22: (1 comment) File libflashrom.h: https://review.coreboot.org/c/flashrom/+/58479/comment/76502ee8_0a2e8666 PS11, Line 4: 2010 > I think the best option is probably to just keep the first copyright year, since we also have git fo […] Sounds about right. Generally it's the year of the _first_ publication of an original work, AFAIK. Anything based on this work would still keep the original date. -- To view, visit https://review.coreboot.org/c/flashrom/+/58479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad Gerrit-Change-Number: 58479 Gerrit-PatchSet: 22 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Mon, 20 Dec 2021 11:41:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nikolai Artemiev <nartemiev(a)google.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: flashchips: enable write-protection for W25Q{64,128}.V
by Sergii Dmytruk (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Nico Huber, Angel Pons, Anastasia Klimchuk. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59071 ) Change subject: flashchips: enable write-protection for W25Q{64,128}.V ...................................................................... Patch Set 17: (1 comment) Patchset: PS15: > OK, I'll add: […] See CB:60230 and CB:60231. -- To view, visit https://review.coreboot.org/c/flashrom/+/59071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iccb69a8d3a0dd2192e2c938caddaf07b1889ed35 Gerrit-Change-Number: 59071 Gerrit-PatchSet: 17 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Sun, 19 Dec 2021 21:59:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: comment

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Change in flashrom[master]: writeprotect: add WPS bit and set it to zero
by Sergii Dmytruk (Code Review) 19 Dec '21

19 Dec '21

Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/60231 ) Change subject: writeprotect: add WPS bit and set it to zero ...................................................................... writeprotect: add WPS bit and set it to zero Handle WPS by always setting it to zero until proper support for it is implemented. Change-Id: I2c26ec65d64a3b6fb1f1a73690bc771415db2744 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M flash.h M writeprotect.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/31/60231/1 diff --git a/flash.h b/flash.h index 16a31ed..a49e615 100644 --- a/flash.h +++ b/flash.h @@ -315,6 +315,7 @@ struct reg_bit_info tb; struct reg_bit_info sec; struct reg_bit_info cmp; + struct reg_bit_info wps; /* Write Protect Selection (per sector protection when set) */ } reg_bits; wp_range_decode_fn_t decode_range; diff --git a/writeprotect.c b/writeprotect.c index bcd0657..39c782f 100644 --- a/writeprotect.c +++ b/writeprotect.c @@ -79,6 +79,7 @@ ret |= read_reg_bit(flash, bits->tb, &cfg->tb, &cfg->tb_bit_present); ret |= read_reg_bit(flash, bits->sec, &cfg->sec, &cfg->sec_bit_present); ret |= read_reg_bit(flash, bits->cmp, &cfg->cmp, &cfg->cmp_bit_present); + /* Note: WPS bit isn't read here, because it's not part of any range. */ for(size_t i = 0; bits->bp[i].reg != INVALID_REG; i++) { ret |= read_reg_bit(flash, bits->bp[i], &cfg->bp[i], &tmp); @@ -130,6 +131,8 @@ set_reg_bit(reg_values, write_masks, bits->tb, cfg->tb); set_reg_bit(reg_values, write_masks, bits->sec, cfg->sec); set_reg_bit(reg_values, write_masks, bits->cmp, cfg->cmp); + /* Note: always setting WPS bit to zero until its fully supported. */ + set_reg_bit(reg_values, write_masks, bits->wps, 0); /* Write each register */ for (enum flash_reg reg = INVALID_REG; reg < MAX_REGISTERS; reg++) { @@ -262,6 +265,8 @@ if (can_write_bit(bits->cmp)) range_bits[bit_count++] = &cfg.cmp; + /* TODO: take WPS bit into account. */ + /* Enumerate all values the range bits can take and find the range * associated with each one. */ *count = (1 << bit_count); -- To view, visit https://review.coreboot.org/c/flashrom/+/60231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2c26ec65d64a3b6fb1f1a73690bc771415db2744 Gerrit-Change-Number: 60231 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: spi25_statusreg.c: add SR3 read/write support
by Sergii Dmytruk (Code Review) 19 Dec '21

19 Dec '21

Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/60230 ) Change subject: spi25_statusreg.c: add SR3 read/write support ...................................................................... spi25_statusreg.c: add SR3 read/write support Adds support for reading and writing the third status register, which needs to be enabled per chip. Extended WRSR doesn't cover SR3, so only one feature flag is added. Change-Id: Id987c544c02da2b956e6ad2c525265cac8f15be1 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M flash.h M spi.h M spi25_statusreg.c 3 files changed, 21 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/30/60230/1 diff --git a/flash.h b/flash.h index d9b8d3a..16a31ed 100644 --- a/flash.h +++ b/flash.h @@ -144,6 +144,8 @@ #define FEATURE_WRSR2 (1 << 20) #define FEATURE_RDSR2 (1 << 21) +/* Status register 3 can be read and written. */ +#define FEATURE_SR3 (1 << 22) #define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff) @@ -175,9 +177,10 @@ INVALID_REG = 0, STATUS1, STATUS2, + STATUS3, CONFIG1, }; -#define MAX_REGISTERS 4 +#define MAX_REGISTERS 5 struct reg_bit_info { /* Register containing the bit */ diff --git a/spi.h b/spi.h index 845b6c2..14f71aa 100644 --- a/spi.h +++ b/spi.h @@ -136,6 +136,11 @@ #define JEDEC_RDSR2_OUTSIZE 0x01 #define JEDEC_RDSR2_INSIZE 0x01 +/* Read Status Register 3 */ +#define JEDEC_RDSR3 0x15 +#define JEDEC_RDSR3_OUTSIZE 0x01 +#define JEDEC_RDSR3_INSIZE 0x01 + /* Status Register Bits */ #define SPI_SR_WIP (0x01 << 0) #define SPI_SR_WEL (0x01 << 1) @@ -158,6 +163,11 @@ #define JEDEC_WRSR2_OUTSIZE 0x02 #define JEDEC_WRSR2_INSIZE 0x00 +/* Write Status Register 3 */ +#define JEDEC_WRSR3 0x11 +#define JEDEC_WRSR3_OUTSIZE 0x02 +#define JEDEC_WRSR3_INSIZE 0x00 + /* Enter 4-byte Address Mode */ #define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7 diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 6f804b1..c4d7399 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -26,6 +26,7 @@ switch (reg) { case STATUS1: return "SR1"; case STATUS2: return "SR2"; + case STATUS3: return "SR3"; case CONFIG1: return "CR1"; default: return "Unknown register"; } @@ -63,6 +64,10 @@ write_cmd[2] = value; write_cmd_len = JEDEC_WRSR_EXT_OUTSIZE; } + } else if (reg == STATUS3 && (feature_bits & FEATURE_SR3)) { + write_cmd[0] = JEDEC_WRSR3; + write_cmd[1] = value; + write_cmd_len = JEDEC_WRSR3_OUTSIZE; } if (write_cmd_len == 0) { @@ -136,6 +141,8 @@ read_cmd = JEDEC_RDSR; } else if (reg == STATUS2 && (feature_bits & FEATURE_RDSR2)) { read_cmd = JEDEC_RDSR2; + } else if (reg == STATUS3 && (feature_bits & FEATURE_SR3)) { + read_cmd = JEDEC_RDSR3; } else { msg_cerr("Chip does not support reading register %s.\n", reg_name(reg)); return 1; -- To view, visit https://review.coreboot.org/c/flashrom/+/60230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id987c544c02da2b956e6ad2c525265cac8f15be1 Gerrit-Change-Number: 60230 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC][OTP] spi25_statusreg: support reading/writing security register
by Sergii Dmytruk (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Nico Huber, Angel Pons, Sergii Dmytruk. Hello build bot (Jenkins), Nico Huber, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/59709 to look at the new patch set (#13). Change subject: [RFC][OTP] spi25_statusreg: support reading/writing security register ...................................................................... [RFC][OTP] spi25_statusreg: support reading/writing security register Not to be confused with "secure registers" of OTP. Security register is a dedicated status register for security-related bits. You don't write its value directly, issuing corresponding write command with no data just sets OTP bit to 1 automatically. No WREN is necessary, but at least some datasheets indicate BUSY state after write command. Unlike cases where OTP bit is part of SR and can only be written while in OTP mode, security register can only be written outside of the mode. Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M flash.h M spi.h M spi25_statusreg.c 3 files changed, 59 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/59709/13 -- To view, visit https://review.coreboot.org/c/flashrom/+/59709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae Gerrit-Change-Number: 59709 Gerrit-PatchSet: 13 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: [RFC][OTP] flashchips: add support for OTP to several chip models
by Sergii Dmytruk (Code Review) 19 Dec '21

19 Dec '21

Attention is currently required from: Nico Huber, Angel Pons, Sergii Dmytruk. Hello build bot (Jenkins), Nico Huber, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/59405 to look at the new patch set (#17). Change subject: [RFC][OTP] flashchips: add support for OTP to several chip models ...................................................................... [RFC][OTP] flashchips: add support for OTP to several chip models List of the chips: * Eon EN25Q16 * Eon EN25Q32(A/B) * Eon EN25Q40 * Eon EN25Q64 * Eon EN25Q80(A) * Eon EN25QH128 * Eon EN25QH16 * Eon EN25QH32 * Eon EN25QH64 * GigaDevice GD25Q127C/GD25Q128C * GigaDevice GD25VQ21B * GigaDevice GD25VQ41B * Winbond W25Q40.V * Winbond W25Q128.V Change-Id: I98491ed00d1e5fa6682bcdc4d5e132ec76447f21 Signed-off-by: Hatim Kanchwala <hatim at hatimak.me> Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M Makefile M flashchips.c M meson.build M otp.h A otp_layouts.c 5 files changed, 230 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/05/59405/17 -- To view, visit https://review.coreboot.org/c/flashrom/+/59405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I98491ed00d1e5fa6682bcdc4d5e132ec76447f21 Gerrit-Change-Number: 59405 Gerrit-PatchSet: 17 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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flashrom-gerrit December 2021