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Change subject: chipset_enable.c: Mark Intel Z390 as DEP
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/58774/comment/c16e194e_48d8a69a
PS3, Line 12: melvyn2
> I'm not sure how I missed the bright red text there, sorry about that. […]
I might be able to sign off this patch.
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Melvyn has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58774 )
Change subject: chipset_enable.c: Mark Intel Z390 as DEP
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/58774/comment/c3b2de35_52bf299d
PS3, Line 12: melvyn2
> As per our Sign-off procedure [1], I'm afraid you have to use your real name here. […]
I'm not sure how I missed the bright red text there, sorry about that. That does mean I won't be able to contribute this however. In the hopes someone else can pick this up:
I release the included works into the public domain free from my own copyright to the furthest extent possible.
This probably doesn't fulfill the copyright creativity clause but might as well.
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Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58623 )
Change subject: Makefile: Use pkg-config to find libftdi1
......................................................................
Patch Set 2:
This change is ready for review.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58529 )
Change subject: sb600spi: Cleanup spispeed and spireamode warnings
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Angel, do you have the power to merge?
I do, I just need to be reminded about it 😜
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Change subject: sb600spi: Cleanup spispeed and spireamode warnings
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Angel, do you have the power to merge?
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Simon Buhrow has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58467 )
Change subject: flashchips.c: big erase blocksize first
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Patch Set 5:
(1 comment)
Patchset:
PS5:
> I didn't take a look at the code, but I imagine this tries to use a full chip erase command where po […]
The clou is the condition
```
if ((block_size == flashctx->chip->total_size * 1024) && per_blockfn == &erase_block){
```
So when the block size equals the flash size it uses the biggest possible erase block size (assuming the eraseblocks are always given in ascending order).
I have never worked with a layout that´s why I didn´t test it. However in case of a given layout the "normal" way should be taken.
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