November 2021 - flashrom-gerrit

Change in flashrom[master]: chipset_enable.c: Mark Intel Z390 as DEP
by Melvyn (Code Review) 05 Nov '21

05 Nov '21

Melvyn has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58774 ) Change subject: chipset_enable.c: Mark Intel Z390 as DEP ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/58774/comment/c3b2de35_52bf299d PS3, Line 12: melvyn2 > As per our Sign-off procedure [1], I'm afraid you have to use your real name here. […] I'm not sure how I missed the bright red text there, sorry about that. That does mean I won't be able to contribute this however. In the hopes someone else can pick this up: I release the included works into the public domain free from my own copyright to the furthest extent possible. This probably doesn't fulfill the copyright creativity clause but might as well. -- To view, visit https://review.coreboot.org/c/flashrom/+/58774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If14d45c144bb32a1d1046185d4476ea29e4d0912 Gerrit-Change-Number: 58774 Gerrit-PatchSet: 3 Gerrit-Owner: Melvyn <melvyn2(a)brcok.tk> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 05 Nov 2021 01:19:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in flashrom[master]: Makefile: Use pkg-config to find libftdi1
by Thomas Heijligen (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Nico Huber, Angel Pons. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58623 ) Change subject: Makefile: Use pkg-config to find libftdi1 ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/flashrom/+/58623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I41f5186d9f3e063c12c8c6eea888d0b0bf534259 Gerrit-Change-Number: 58623 Gerrit-PatchSet: 2 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Nov 2021 20:38:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: sb600spi: Cleanup spispeed and spireamode warnings
by Angel Pons (Code Review) 04 Nov '21

04 Nov '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/flashrom/+/58529 ) Change subject: sb600spi: Cleanup spispeed and spireamode warnings ...................................................................... sb600spi: Cleanup spispeed and spireamode warnings These warnings are printed at error level so they are displayed with every invocation of flashrom. This clutters the flashrom output in the usual case. Move warnings to debug level, add newline and clean up text. TEST=Deploy to guybrush, observe messages are only seen when --verbose is enabled BUG=None BRANCH=None Change-Id: Idf5e735b9e504c943bf93a428da64976d723eb2c Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58529 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M sb600spi.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/sb600spi.c b/sb600spi.c index 7fa01af..d5e228c 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -458,8 +458,8 @@ msg_pdbg("SPI read mode is %s (%i)\n", spireadmodes[read_mode], read_mode); if (spireadmode_idx < 0) { - msg_perr("Warning: spireadmode not set, " - "leaving spireadmode unchanged."); + msg_pdbg("spireadmode is not set, " + "leaving SPI read mode unchanged.\n"); } else if (set_mode(dev, spireadmode_idx, sb600_spibar) != 0) { return 1; @@ -501,7 +501,7 @@ } } if (spispeed_idx < 0) { - msg_perr("Warning: spispeed not set, leaving spispeed unchanged."); + msg_pdbg("spispeed is not set, leaving SPI speed unchanged.\n"); return 0; } return set_speed(dev, amd_gen, spispeed_idx, sb600_spibar); -- To view, visit https://review.coreboot.org/c/flashrom/+/58529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idf5e735b9e504c943bf93a428da64976d723eb2c Gerrit-Change-Number: 58529 Gerrit-PatchSet: 2 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in flashrom[master]: sb600spi: Cleanup spispeed and spireamode warnings
by Angel Pons (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Rob Barnes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58529 ) Change subject: sb600spi: Cleanup spispeed and spireamode warnings ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Angel, do you have the power to merge? I do, I just need to be reminded about it 😜 -- To view, visit https://review.coreboot.org/c/flashrom/+/58529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idf5e735b9e504c943bf93a428da64976d723eb2c Gerrit-Change-Number: 58529 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Thu, 04 Nov 2021 17:29:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: sb600spi: Cleanup spispeed and spireamode warnings
by Raul Rangel (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Rob Barnes. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58529 ) Change subject: sb600spi: Cleanup spispeed and spireamode warnings ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Angel, do you have the power to merge? -- To view, visit https://review.coreboot.org/c/flashrom/+/58529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idf5e735b9e504c943bf93a428da64976d723eb2c Gerrit-Change-Number: 58529 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Thu, 04 Nov 2021 16:52:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: flashchips.c: big erase blocksize first
by Simon Buhrow (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Nico Huber, Angel Pons. Simon Buhrow has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58467 ) Change subject: flashchips.c: big erase blocksize first ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > I didn't take a look at the code, but I imagine this tries to use a full chip erase command where po […] The clou is the condition ``` if ((block_size == flashctx->chip->total_size * 1024) && per_blockfn == &erase_block){ ``` So when the block size equals the flash size it uses the biggest possible erase block size (assuming the eraseblocks are always given in ascending order). I have never worked with a layout that´s why I didn´t test it. However in case of a given layout the "normal" way should be taken. -- To view, visit https://review.coreboot.org/c/flashrom/+/58467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I862ce0b5f8912565e43c340578d8126aa2e6aa3b Gerrit-Change-Number: 58467 Gerrit-PatchSet: 5 Gerrit-Owner: Simon Buhrow Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Nov 2021 09:46:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Simon Buhrow Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in flashrom[master]: Add MEC1308 EC programmer
by Victor Ding (Code Review) 04 Nov '21

04 Nov '21

Victor Ding has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44541 ) Change subject: Add MEC1308 EC programmer ...................................................................... Add MEC1308 EC programmer Initial support of Microchip MEC1308 Embedded Controller. Signed-off-by: Victor Ding <victording(a)google.com> Change-Id: I2d51b4bdc0b38b6e488e71b9e774eb6232a2069e --- M Makefile M flashrom.c A mec1308.c M meson.build M meson_options.txt M programmer.h 6 files changed, 569 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/41/44541/1 diff --git a/Makefile b/Makefile index 803529f..2acd656 100644 --- a/Makefile +++ b/Makefile @@ -175,6 +175,11 @@ else override CONFIG_FT2232_SPI = no endif +ifeq ($(CONFIG_MEC1308), yes) +UNSUPPORTED_FEATURES += CONFIG_MEC1308=yes +else +override CONFIG_MEC1308 = no +endif ifeq ($(CONFIG_USBBLASTER_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_USBBLASTER_SPI=yes else @@ -281,6 +286,11 @@ else override CONFIG_DRKAISER = no endif +ifeq ($(CONFIG_MEC1308), yes) +UNSUPPORTED_FEATURES += CONFIG_MEC1308=yes +else +override CONFIG_MEC1308 = no +endif ifeq ($(CONFIG_NICREALTEK), yes) UNSUPPORTED_FEATURES += CONFIG_NICREALTEK=yes else @@ -386,6 +396,11 @@ else override CONFIG_FT2232_SPI = no endif +ifeq ($(CONFIG_MEC1308), yes) +UNSUPPORTED_FEATURES += CONFIG_MEC1308=yes +else +override CONFIG_MEC1308 = no +endif ifeq ($(CONFIG_USBBLASTER_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_USBBLASTER_SPI=yes else @@ -674,6 +689,9 @@ # Always enable FT2232 SPI dongles for now. CONFIG_FT2232_SPI ?= yes +# Microchip MEC1308 Embedded Controller +CONFIG_MEC1308 ?= yes + # Always enable Altera USB-Blaster dongles for now. CONFIG_USBBLASTER_SPI ?= yes @@ -855,6 +873,11 @@ NEED_LIBPCI += CONFIG_INTERNAL endif +ifeq ($(CONFIG_MEC1308), yes) +FEATURE_CFLAGS += -D'CONFIG_MEC1308=1' +PROGRAMMER_OBJS += mec1308.o +endif + ifeq ($(CONFIG_SERPROG), yes) FEATURE_CFLAGS += -D'CONFIG_SERPROG=1' PROGRAMMER_OBJS += serprog.o diff --git a/flashrom.c b/flashrom.c index 4a30986..5a8e37a 100644 --- a/flashrom.c +++ b/flashrom.c @@ -84,6 +84,18 @@ }, #endif +#if CONFIG_MEC1308 == 1 + { + .name = "mec1308", + .type = OTHER, + .devs.note = "Microchip MEC1308 Embedded Controller.\n", + .init = mec1308_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_NIC3COM == 1 { .name = "nic3com", diff --git a/mec1308.c b/mec1308.c new file mode 100644 index 0000000..43bd2db --- /dev/null +++ b/mec1308.c @@ -0,0 +1,520 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * Neither the name of Google or the names of contributors or + * licensors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * This software is provided "AS IS," without a warranty of any kind. + * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, + * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. + * GOOGLE INC AND ITS LICENSORS SHALL NOT BE LIABLE + * FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING + * OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL + * GOOGLE OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, + * OR FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR + * PUNITIVE DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF + * LIABILITY, ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, + * EVEN IF GOOGLE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + */ + +#if defined(__i386__) || defined(__x86_64__) +#include <inttypes.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> + +#include "flash.h" +#include "hwaccess.h" +#include "chipdrivers.h" +#include "programmer.h" +#include "spi.h" + +#define MEC1308_SIO_PORT1 0x2e +#define MEC1308_SIO_PORT2 0x4e +#define MEC1308_SIO_ENTRY_KEY 0x55 +#define MEC1308_SIO_EXIT_KEY 0xaa + +#define MEC1308_SIOCFG_LDN 0x07 /* LDN Bank Selector */ +#define MEC1308_DEVICE_ID_REG 0x20 /* Device ID Register */ +#define MEC1308_DEVICE_ID_VAL 0x4d /* Device ID Value for MEC1308 */ +#define MEC1310_DEVICE_ID_VAL 0x04 /* Device ID Value for MEC1310 */ +#define MEC1308_DEVICE_REV 0x21 /* Device Revision ID Register */ + +#define MEC1308_MBX_CMD 0x82 /* mailbox command register offset */ +#define MEC1308_MBX_EXT_CMD 0x83 /* mailbox ext. command reg offset */ +#define MEC1308_MBX_DATA_START 0x84 /* first mailbox data register offset */ +#define MEC1308_MBX_DATA_END 0x91 /* last mailbox data register offset */ + +static unsigned int mbx_data; /* Mailbox register interface data address*/ + +/* + * These command codes depend on EC firmware. The ones listed below are input + * using the mailbox interface, though others may be input using the ACPI + * interface. Some commands also have an output value (ie pass/failure code) + * which EC writes to the mailbox command register after completion. + */ +#define MEC1308_CMD_SMI_ENABLE 0x84 +#define MEC1308_CMD_SMI_DISABLE 0x85 +#define MEC1308_CMD_ACPI_ENABLE 0x86 +#define MEC1308_CMD_ACPI_DISABLE 0x87 + +/* + * Passthru commands are also input using the mailbox interface. Passthru mode + * enter/start/end commands are special since they require a command word to + * be written to the data registers. Other passthru commands are performed + * after passthru mode has been started. + * + * Multiple passthru mode commands may be issued before ending passthru mode. + * You do not need to enter, start, and end passthru mode for each SPI + * command. However, other mailbox commands might not work when passthru mode + * is enabled. For example, you may read all SPI chip content while in passthru + * mode, but you should exit passthru mode before performing other EC commands + * such as reading fan speed. + */ +#define MEC1308_CMD_PASSTHRU 0x55 /* force EC to process word */ +#define MEC1308_CMD_PASSTHRU_SUCCESS 0xaa /* success code for passthru */ +#define MEC1308_CMD_PASSTHRU_FAIL 0xfe /* failure code for passthru */ +#define MEC1308_CMD_PASSTHRU_ENTER "PathThruMode" /* not a typo... */ +#define MEC1308_CMD_PASSTHRU_START "Start" +#define MEC1308_CMD_PASSTHRU_EXIT "End_Mode" +#define MEC1308_CMD_PASSTHRU_CS_EN 0xf0 /* chip-select enable */ +#define MEC1308_CMD_PASSTHRU_CS_DIS 0xf1 /* chip-select disable */ +#define MEC1308_CMD_PASSTHRU_SEND 0xf2 /* send byte from data0 */ +#define MEC1308_CMD_PASSTHRU_READ 0xf3 /* read byte, place in data0 */ + +typedef struct +{ + unsigned int in_sio_cfgmode; + unsigned int mbx_idx; /* Mailbox register interface index address */ + unsigned int mbx_data; /* Mailbox register interface data address*/ +} mec1308_data_t; + +static void mec1308_sio_enter(mec1308_data_t *ctx_data, uint16_t port) +{ + if (ctx_data->in_sio_cfgmode) + return; + + OUTB(MEC1308_SIO_ENTRY_KEY, port); + ctx_data->in_sio_cfgmode = 1; +} + +static void mec1308_sio_exit(mec1308_data_t *ctx_data, uint16_t port) +{ + if (!ctx_data->in_sio_cfgmode) + return; + + OUTB(MEC1308_SIO_EXIT_KEY, port); + ctx_data->in_sio_cfgmode = 0; +} + +/** probe for super i/o index + * @port: allocated buffer to store port + * + * returns 0 to indicate success, <0 to indicate error + */ +static int mec1308_get_sio_index(mec1308_data_t *ctx_data, uint16_t *port) +{ + uint16_t ports[] = { MEC1308_SIO_PORT1, + MEC1308_SIO_PORT2, + }; + size_t i; + static uint16_t port_internal, port_found = 0; + + if (port_found) { + *port = port_internal; + return 0; + } + + if (rget_io_perms()) + return -1; + + for (i = 0; i < ARRAY_SIZE(ports); i++) { + uint8_t tmp8; + + /* + * Only after config mode has been successfully entered will the + * index port will read back the last value written to it. + * So we will attempt to enter config mode, set the index + * register, and see if the index register retains the value. + * + * Note: It seems to work "best" when using a device ID register + * as the index and reading from the data port before reading + * the index port. + */ + mec1308_sio_enter(ctx_data, ports[i]); + OUTB(MEC1308_DEVICE_ID_REG, ports[i]); + tmp8 = INB(ports[i] + 1); + tmp8 = INB(ports[i]); + if ((tmp8 != MEC1308_DEVICE_ID_REG)) { + ctx_data->in_sio_cfgmode = 0; + continue; + } + + port_internal = ports[i]; + port_found = 1; + break; + } + + if (!port_found) { + msg_cdbg("\nfailed to obtain super i/o index\n"); + return -1; + } + + msg_cdbg("\nsuper i/o index = 0x%04x\n", port_internal); + *port = port_internal; + return 0; +} + +static uint8_t mbx_read(mec1308_data_t *ctx_data, uint8_t idx) +{ + OUTB(idx, ctx_data->mbx_idx); + return INB(mbx_data); +} + +static int mbx_wait(mec1308_data_t *ctx_data) +{ + int i; + int max_attempts = 10000; + int rc = 0; + + for (i = 0; mbx_read(ctx_data, MEC1308_MBX_CMD); i++) { + if (i == max_attempts) { + rc = 1; + break; + } + /* FIXME: This delay adds determinism to the delay period. It + was chosen arbitrarily thru some experiments. */ + programmer_delay(2); + } + + return rc; +} + +static int mbx_write(mec1308_data_t *ctx_data, uint8_t idx, uint8_t data) +{ + int rc = 0; + + if (idx == MEC1308_MBX_CMD && mbx_wait(ctx_data)) { + msg_perr("%s: command register not clear\n", __func__); + return 1; + } + + OUTB(idx, ctx_data->mbx_idx); + OUTB(data, mbx_data); + + if (idx == MEC1308_MBX_CMD) + rc = mbx_wait(ctx_data); + + return rc; +} + +static void mbx_clear(mec1308_data_t *ctx_data) +{ + int reg; + + for (reg = MEC1308_MBX_DATA_START; reg < MEC1308_MBX_DATA_END; reg++) + mbx_write(ctx_data, reg, 0x00); + mbx_write(ctx_data, MEC1308_MBX_CMD, 0x00); +} + +static int mec1308_exit_passthru_mode(mec1308_data_t *ctx_data) +{ + uint8_t tmp8; + size_t i; + + /* exit passthru mode */ + for (i = 0; i < strlen(MEC1308_CMD_PASSTHRU_EXIT); i++) { + mbx_write(ctx_data, MEC1308_MBX_DATA_START + i, + MEC1308_CMD_PASSTHRU_EXIT[i]); + } + + if (mbx_write(ctx_data, MEC1308_MBX_CMD, MEC1308_CMD_PASSTHRU)) { + msg_pdbg("%s(): exit passthru command timed out\n", __func__); + return 1; + } + + tmp8 = mbx_read(ctx_data, MEC1308_MBX_DATA_START); + msg_pdbg("%s: result: 0x%02x ", __func__, tmp8); + if (tmp8 == MEC1308_CMD_PASSTHRU_SUCCESS) { + msg_pdbg("(exited passthru mode)\n"); + } else if (tmp8 == MEC1308_CMD_PASSTHRU_FAIL) { + msg_pdbg("(failed to exit passthru mode)\n"); + } + + return 0; +} + +static int enter_passthru_mode(mec1308_data_t *ctx_data) +{ + uint8_t tmp8; + size_t i; + + /* + * Enter passthru mode. If the EC does not successfully enter passthru + * mode the first time, we'll clear the mailbox and issue the "exit + * passthru mode" command sequence up to 3 times or until it arrives in + * a known state. + * + * Note: This workaround was developed experimentally. + */ + for (i = 0; i < 3; i++) { + size_t j; + + msg_pdbg("%s(): entering passthru mode, attempt %d out of 3\n", + __func__, (int)(i + 1)); + for (j = 0; j < strlen(MEC1308_CMD_PASSTHRU_ENTER); j++) { + mbx_write(ctx_data, MEC1308_MBX_DATA_START + j, + MEC1308_CMD_PASSTHRU_ENTER[j]); + } + + if (mbx_write(ctx_data, MEC1308_MBX_CMD, MEC1308_CMD_PASSTHRU)) + msg_pdbg("%s(): enter passthru command timed out\n", + __func__); + + tmp8 = mbx_read(ctx_data, MEC1308_MBX_DATA_START); + if (tmp8 == MEC1308_CMD_PASSTHRU_SUCCESS) + break; + + msg_pdbg("%s(): command failed, clearing data registers and " + "issuing full exit passthru command...\n", __func__); + mbx_clear(ctx_data); + mec1308_exit_passthru_mode(ctx_data); + } + + if (tmp8 != MEC1308_CMD_PASSTHRU_SUCCESS) { + msg_perr("%s(): failed to enter passthru mode, result=0x%02x\n", + __func__, tmp8); + return 1; + } + + msg_pdbg("%s(): enter passthru mode return code: 0x%02x\n", + __func__, tmp8); + + /* start passthru mode */ + for (i = 0; i < strlen(MEC1308_CMD_PASSTHRU_START); i++) + mbx_write(ctx_data, MEC1308_MBX_DATA_START + i, + MEC1308_CMD_PASSTHRU_START[i]); + if (mbx_write(ctx_data, MEC1308_MBX_CMD, MEC1308_CMD_PASSTHRU)) { + msg_pdbg("%s(): start passthru command timed out\n", __func__); + return 1; + } + tmp8 = mbx_read(ctx_data, MEC1308_MBX_DATA_START); + if (tmp8 != MEC1308_CMD_PASSTHRU_SUCCESS) { + msg_perr("%s(): failed to enter passthru mode, result=%02x\n", + __func__, tmp8); + return 1; + } + msg_pdbg("%s(): start passthru mode return code: 0x%02x\n", + __func__, tmp8); + + return 0; +} + +static int mec1308_shutdown(void *data) +{ + mec1308_data_t *ctx_data = (mec1308_data_t *)data; + + /* Exit passthru mode before performing commands which do not affect + the SPI ROM */ + mec1308_exit_passthru_mode(ctx_data); + + /* Re-enable SMI and ACPI. + FIXME: is there an ordering dependency? */ + if (mbx_write(ctx_data, MEC1308_MBX_CMD, MEC1308_CMD_SMI_ENABLE)) + msg_pdbg("%s: unable to re-enable SMI\n", __func__); + if (mbx_write(ctx_data, MEC1308_MBX_CMD, MEC1308_CMD_ACPI_ENABLE)) + msg_pdbg("%s: unable to re-enable ACPI\n", __func__); + + free(data); + return 0; +} + +static int mec1308_chip_select(mec1308_data_t *ctx_data) +{ + return mbx_write(ctx_data, MEC1308_MBX_CMD, MEC1308_CMD_PASSTHRU_CS_EN); +} + +static int mec1308_chip_deselect(mec1308_data_t *ctx_data) +{ + return mbx_write(ctx_data, MEC1308_MBX_CMD, MEC1308_CMD_PASSTHRU_CS_DIS); +} + +/* + * MEC1308 will not allow direct access to SPI chip from host if EC is + * connected to LPC bus. This function will forward commands issued thru + * mailbox interface to the SPI flash chip. + */ +static int mec1308_spi_send_command(const struct flashctx *flash, unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + int rc = 0; + size_t i; + mec1308_data_t *ctx_data = (mec1308_data_t *)flash->mst->spi.data; + + if (mec1308_chip_select(ctx_data)) + return 1; + + for (i = 0; i < writecnt; i++) { + if (mbx_write(ctx_data, MEC1308_MBX_DATA_START, writearr[i]) || + mbx_write(ctx_data, MEC1308_MBX_CMD, MEC1308_CMD_PASSTHRU_SEND)) { + msg_pdbg("%s: failed to issue send command\n",__func__); + rc = 1; + goto mec1308_spi_send_command_exit; + } + } + + for (i = 0; i < readcnt; i++) { + if (mbx_write(ctx_data, MEC1308_MBX_CMD, MEC1308_CMD_PASSTHRU_READ)) { + msg_pdbg("%s: failed to issue read command\n",__func__); + rc = 1; + goto mec1308_spi_send_command_exit; + } + readarr[i] = mbx_read(ctx_data, MEC1308_MBX_DATA_START); + } + +mec1308_spi_send_command_exit: + rc |= mec1308_chip_deselect(ctx_data); + return rc; +} + +static struct spi_master spi_master_mec1308 = { + .max_data_read = 256, /* FIXME: should be MAX_DATA_READ_UNLIMITED? */ + .max_data_write = 256, /* FIXME: should be MAX_DATA_WRITE_UNLIMITED? */ + .command = mec1308_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + +int mec1308_init(void) +{ + uint16_t sio_port; + uint8_t device_id; + uint8_t tmp8; + int ret = 0; + char *p = NULL; + mec1308_data_t *ctx_data = NULL; + + msg_pdbg("%s(): entered\n", __func__); + + ctx_data = calloc(1, sizeof(mec1308_data_t)); + if (!ctx_data) { + msg_perr("Unable to allocate space for extra context data.\n"); + return 1; + } + + p = extract_programmer_param("type"); + if (p && strcmp(p, "ec")) { + msg_pdbg("mec1308 only supports \"ec\" type devices\n"); + ret = 1; + goto mec1308_init_exit; + } + + if (mec1308_get_sio_index(ctx_data, &sio_port) < 0) { + msg_pdbg("MEC1308 not found (probe failed).\n"); + ret = 1; + goto mec1308_init_exit; + } + device_id = sio_read(sio_port, MEC1308_DEVICE_ID_REG); + switch(device_id) { + case MEC1308_DEVICE_ID_VAL: + msg_pdbg("Found EC: MEC1308 (ID:0x%02x,Rev:0x%02x) on " + "sio_port:0x%x.\n", device_id, + sio_read(sio_port, MEC1308_DEVICE_REV), sio_port); + break; + case MEC1310_DEVICE_ID_VAL: + msg_pdbg("Found EC: MEC1310 (ID:0x%02x,Rev:0x%02x) on " + "sio_port:0x%x.\n", device_id, + sio_read(sio_port, MEC1308_DEVICE_REV), sio_port); + break; + default: + msg_pdbg("MEC1308 not found\n"); + ret = 1; + goto mec1308_init_exit; + } + + /* + * setup mailbox interface at LDN 9 + */ + sio_write(sio_port, MEC1308_SIOCFG_LDN, 0x09); + tmp8 = sio_read(sio_port, 0x30); + tmp8 |= 1; + sio_write(sio_port, 0x30, tmp8); /* activate logical device */ + + ctx_data->mbx_idx = (unsigned int)sio_read(sio_port, 0x60) << 8 | + sio_read(sio_port, 0x61); + mbx_data = ctx_data->mbx_idx + 1; + msg_pdbg("%s: mbx_idx: 0x%04x, mbx_data: 0x%04x\n", + __func__, ctx_data->mbx_idx, mbx_data); + + /* Exit Super I/O config mode */ + mec1308_sio_exit(ctx_data, sio_port); + + /* Now that we can read the mailbox, we will wait for any remaining + * command to finish.*/ + if (mbx_wait(ctx_data) != 0) { + msg_perr("%s: mailbox is not available\n", __func__); + ret = 1; + goto mec1308_init_exit; + } + + /* Further setup -- disable SMI and ACPI. + FIXME: is there an ordering dependency? */ + if (mbx_write(ctx_data, MEC1308_MBX_CMD, MEC1308_CMD_ACPI_DISABLE)) { + msg_pdbg("%s: unable to disable ACPI\n", __func__); + ret = 1; + goto mec1308_init_exit; + } + + if (mbx_write(ctx_data, MEC1308_MBX_CMD, MEC1308_CMD_SMI_DISABLE)) { + msg_pdbg("%s: unable to disable SMI\n", __func__); + ret = 1; + goto mec1308_init_exit; + } + + if (register_shutdown(mec1308_shutdown, ctx_data)) { + ret = 1; + goto mec1308_init_exit; + } + + /* + * Enter SPI Pass-Thru Mode after commands which do not require access + * to SPI ROM are complete. We'll start by doing the exit_passthru_mode + * sequence, which is benign if the EC is already in passthru mode. + */ + mec1308_exit_passthru_mode(ctx_data); + + if (enter_passthru_mode(ctx_data)) { + ret = 1; + goto mec1308_init_exit; + } + + internal_buses_supported |= BUS_LPC; /* for LPC <--> SPI bridging */ + spi_master_mec1308.data = ctx_data; + register_spi_master(&spi_master_mec1308); + msg_pdbg("%s(): successfully initialized mec1308\n", __func__); + +mec1308_init_exit: + free(p); + if (ret) + free(ctx_data); + return ret; +} +#endif diff --git a/meson.build b/meson.build index 04176f3..fc79c60 100644 --- a/meson.build +++ b/meson.build @@ -47,6 +47,7 @@ config_it8212 = get_option('config_it8212') config_linux_mtd = get_option('config_linux_mtd') config_linux_spi = get_option('config_linux_spi') +config_mec1308 = get_option('config_mec1308') config_mstarddc_spi = get_option('config_mstarddc_spi') config_nic3com = get_option('config_nic3com') config_nicintel_eeprom = get_option('config_nicintel_eeprom') @@ -214,6 +215,10 @@ srcs += 'linux_spi.c' cargs += '-DCONFIG_LINUX_SPI=1' endif +if config_mec1308 + srcs += 'mec1308.c' + cargs += '-DCONFIG_MEC1308=1' +endif if config_mstarddc_spi srcs += 'mstarddc_spi.c' cargs += '-DCONFIG_MSTARDDC_SPI=1' diff --git a/meson_options.txt b/meson_options.txt index ac48e4e..24a1911 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -19,6 +19,7 @@ option('config_it8212', type : 'boolean', value : true, description : 'ITE IT8212F PATA') option('config_linux_mtd', type : 'boolean', value : true, description : 'Linux MTD interfaces') option('config_linux_spi', type : 'boolean', value : true, description : 'Linux spidev interfaces') +option('config_mec1308', type : 'boolean', value : false, description : 'Microchip MEC1308 Embedded Controller') option('config_mstarddc_spi', type : 'boolean', value : false, description : 'MSTAR DDC support') option('config_nic3com', type : 'boolean', value : true, description : '3Com NICs') option('config_nicintel_eeprom', type : 'boolean', value : true, description : 'EEPROM on Intel NICs') diff --git a/programmer.h b/programmer.h index c5cab18..6422541 100644 --- a/programmer.h +++ b/programmer.h @@ -109,6 +109,9 @@ #if CONFIG_USBBLASTER_SPI == 1 PROGRAMMER_USBBLASTER_SPI, #endif +#if CONFIG_MEC1308 == 1 + PROGRAMMER_MEC1308, +#endif #if CONFIG_MSTARDDC_SPI == 1 PROGRAMMER_MSTARDDC_SPI, #endif @@ -689,6 +692,11 @@ /* mcp6x_spi.c */ int mcp6x_spi_init(int want_spi); +/* mec1308.c */ +#if CONFIG_MEC1308 == 1 +int mec1308_init(void); +#endif + /* sb600spi.c */ int sb600_probe_spi(struct pci_dev *dev); -- To view, visit https://review.coreboot.org/c/flashrom/+/44541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2d51b4bdc0b38b6e488e71b9e774eb6232a2069e Gerrit-Change-Number: 44541 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Ding <victording(a)google.com> Gerrit-MessageType: newchange

5 20

Change in flashrom[master]: Add ENE LPC programmer
by Victor Ding (Code Review) 04 Nov '21

04 Nov '21

Victor Ding has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44580 ) Change subject: Add ENE LPC programmer ...................................................................... Add ENE LPC programmer Initial support of ENE LPC interface keyboard controller. BUG=b:156140422 BRANCH=none Signed-off-by: Victor Ding <victording(a)google.com> Change-Id: I970afd8c1bd92c159c60e09f22e2f18c0433729d --- M Makefile A ene_lpc.c M flashrom.c M meson.build M meson_options.txt M programmer.h 6 files changed, 642 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/80/44580/1 diff --git a/Makefile b/Makefile index 803529f..85b4850 100644 --- a/Makefile +++ b/Makefile @@ -170,6 +170,11 @@ else override CONFIG_DEVELOPERBOX_SPI = no endif +ifeq ($(CONFIG_ENE_LPC), yes) +UNSUPPORTED_FEATURES += CONFIG_ENE_LPC=yes +else +override CONFIG_ENE_LPC = no +endif ifeq ($(CONFIG_FT2232_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_FT2232_SPI=yes else @@ -271,6 +276,11 @@ else override CONFIG_ATAPROMISE = no endif +ifeq ($(CONFIG_ENE_LPC), yes) +UNSUPPORTED_FEATURES += CONFIG_ENE_LPC=yes +else +override CONFIG_ENE_LPC = no +endif ifeq ($(CONFIG_IT8212), yes) UNSUPPORTED_FEATURES += CONFIG_IT8212=yes else @@ -381,6 +391,11 @@ else override CONFIG_DEVELOPERBOX_SPI = no endif +ifeq ($(CONFIG_ENE_LPC), yes) +UNSUPPORTED_FEATURES += CONFIG_ENE_LPC=yes +else +override CONFIG_ENE_LPC = no +endif ifeq ($(CONFIG_FT2232_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_FT2232_SPI=yes else @@ -671,6 +686,9 @@ # Promise ATA controller support. CONFIG_ATAPROMISE ?= no +# ENE LPC interface keyboard controller +CONFIG_ENE_LPC ?= yes + # Always enable FT2232 SPI dongles for now. CONFIG_FT2232_SPI ?= yes @@ -855,6 +873,11 @@ NEED_LIBPCI += CONFIG_INTERNAL endif +ifeq ($(CONFIG_ENE_LPC), yes) +FEATURE_CFLAGS += -D'CONFIG_ENE_LPC=1' +PROGRAMMER_OBJS += ene_lpc.o +endif + ifeq ($(CONFIG_SERPROG), yes) FEATURE_CFLAGS += -D'CONFIG_SERPROG=1' PROGRAMMER_OBJS += serprog.o diff --git a/ene_lpc.c b/ene_lpc.c new file mode 100644 index 0000000..701e84e --- /dev/null +++ b/ene_lpc.c @@ -0,0 +1,593 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2012 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * Neither the name of Google or the names of contributors or + * licensors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * This software is provided "AS IS," without a warranty of any kind. + * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, + * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. + * GOOGLE INC AND ITS LICENSORS SHALL NOT BE LIABLE + * FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING + * OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL + * GOOGLE OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, + * OR FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR + * PUNITIVE DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF + * LIABILITY, ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, + * EVEN IF GOOGLE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + */ + +#if defined(__i386__) || defined(__x86_64__) +#include <inttypes.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> +#include <sys/time.h> + +#include "chipdrivers.h" +#include "flash.h" +#include "programmer.h" +#include "hwaccess.h" +#include "spi.h" + +/* MCU registers */ +#define REG_EC_HWVER 0xff00 +#define REG_EC_FWVER 0xff01 +#define REG_EC_EDIID 0xff24 +#define REG_8051_CTRL 0xff14 +#define REG_EC_EXTCMD 0xff10 + +#define CPU_RESET 1 + +/* MCU SPI peripheral registers */ +#define REG_SPI_DATA 0xfeab +#define REG_SPI_COMMAND 0xfeac +#define REG_SPI_CONFIG 0xfead + +#define CFG_CSn_FORCE_LOW (1 << 4) +#define CFG_COMMAND_WRITE_ENABLE (1 << 3) +#define CFG_STATUS (1 << 1) +#define CFG_ENABLE_BUSY_STATUS_CHECK (1 << 0) + +/* Timeout */ +#define EC_COMMAND_TIMEOUT 4 +#define EC_RESTART_TIMEOUT 10 +#define ENE_SPI_DELAY_CYCLE 4 +#define EC_PAUSE_TIMEOUT 12 +#define EC_RESET_TRIES 3 + +#define ENE_KB94X_PAUSE_WAKEUP_PORT 0x64 + +#define MASK_INPUT_BUFFER_FULL 2 +#define MASK_OUTPUT_BUFFER_FULL 1 + +const int port_ene_bank = 1; +const int port_ene_offset = 2; +const int port_ene_data = 3; + +/* Supported ENE ECs, ENE_LAST should always be LAST member */ +enum ene_chip_id { + ENE_KB932 = 0, + ENE_KB94X, + ENE_LAST +}; + +/* EC state */ +enum ene_ec_state { + EC_STATE_NORMAL, + EC_STATE_IDLE, + EC_STATE_RESET, + EC_STATE_UNKNOWN +}; + +/* chip-specific parameters */ +typedef struct { + enum ene_chip_id chip_id; + uint8_t hwver; + uint8_t ediid; + uint32_t port_bios; + uint32_t port_ec_command; + uint32_t port_ec_data; + uint8_t ec_reset_cmd; + uint8_t ec_reset_data; + uint8_t ec_restart_cmd; + uint8_t ec_restart_data; + uint8_t ec_pause_cmd; + uint8_t ec_pause_data; + uint16_t ec_status_buf; + uint8_t ec_is_stopping; + uint8_t ec_is_running; + uint8_t ec_is_pausing; + uint32_t port_io_base; +} ene_chip_t; + +typedef struct +{ + /* pointer to table entry of identified chip */ + ene_chip_t *chip; + /* current ec state */ + enum ene_ec_state ec_state; + struct timeval pause_begin; +} ene_lpc_data_t; + +/* table of supported chips + parameters */ +static ene_chip_t ene_chips[] = { + { + ENE_KB932, /* chip_id */ + 0xa2, 0x02, /* hwver + ediid */ + 0x66, /* port_bios */ + 0x6c, 0x68, /* port_ec_{command,data} */ + 0x59, 0xf2, /* ec_reset_{cmd,data} */ + 0x59, 0xf9, /* ec_restart_{cmd,data} */ + 0x59, 0xf1, /* ec_pause_{cmd,data} */ + 0xf554, /* ec_status_buf */ + 0xa5, 0x00, /* ec_is_{stopping,running} masks */ + 0x33, /* ec_is_pausing mask */ + 0xfd60 /* port_io_base */ + }, + { + ENE_KB94X, /* chip_id */ + 0xa3, 0x05, /* hwver + ediid */ + 0x66, /* port_bios */ + 0x66, 0x68, /* port_ec_{command,data} */ + 0x7d, 0x10, /* ec_reset_{cmd,data} */ + 0x7f, 0x10, /* ec_restart_{cmd,data} */ + 0x7e, 0x10, /* ec_pause_{cmd,data} */ + 0xf710, /* ec_status_buf */ + 0x02, 0x00, /* ec_is_{stopping,running} masks */ + 0x01, /* ec_is_pausing mask */ + 0x0380 /* port_io_base */ + } +}; + +static void ec_command(const ene_chip_t *chip, uint8_t cmd, uint8_t data) +{ + struct timeval begin, now; + + /* Spin wait for EC input buffer empty */ + gettimeofday(&begin, NULL); + while (INB(chip->port_ec_command) & MASK_INPUT_BUFFER_FULL) { + gettimeofday(&now, NULL); + if ((now.tv_sec - begin.tv_sec) >= EC_COMMAND_TIMEOUT) { + msg_pdbg("%s: buf not empty\n", __func__); + return; + } + } + + /* Write command */ + OUTB(cmd, chip->port_ec_command); + + if (chip->chip_id == ENE_KB932) { + /* Spin wait for EC input buffer empty */ + gettimeofday(&begin, NULL); + while (INB(chip->port_ec_command) & + MASK_INPUT_BUFFER_FULL) { + gettimeofday(&now, NULL); + if ((now.tv_sec - begin.tv_sec) >= + EC_COMMAND_TIMEOUT) { + msg_pdbg("%s: buf not empty\n", __func__); + return; + } + } + /* Write data */ + OUTB(data, chip->port_ec_data); + } +} + +static uint8_t ene_read(const ene_chip_t *chip, uint16_t addr) +{ + uint8_t bank; + uint8_t offset; + uint8_t data; + uint32_t port_io_base; + + bank = addr >> 8; + offset = addr & 0xff; + port_io_base = chip->port_io_base; + + OUTB(bank, port_io_base + port_ene_bank); + OUTB(offset, port_io_base + port_ene_offset); + data = INB(port_io_base + port_ene_data); + + return data; +} + +static void ene_write(const ene_chip_t *chip, uint16_t addr, uint8_t data) +{ + uint8_t bank; + uint8_t offset; + uint32_t port_io_base; + + bank = addr >> 8; + offset = addr & 0xff; + port_io_base = chip->port_io_base; + + OUTB(bank, port_io_base + port_ene_bank); + OUTB(offset, port_io_base + port_ene_offset); + + OUTB(data, port_io_base + port_ene_data); +} + +/** + * wait_cycles, wait for n LPC bus clock cycles + * + * @param n: number of LPC cycles to wait + * @return void + */ +static void wait_cycles(const ene_chip_t *chip,int n) +{ + while (n--) + INB(chip->port_io_base + port_ene_bank); +} + +static int is_spicmd_write(uint8_t cmd) +{ + switch (cmd) { + case JEDEC_WREN: + /* Chip Write Enable */ + case JEDEC_EWSR: + /* Write Status Enable */ + case JEDEC_CE_60: + /* Chip Erase 0x60 */ + case JEDEC_CE_C7: + /* Chip Erase 0xc7 */ + case JEDEC_BE_52: + /* Block Erase 0x52 */ + case JEDEC_BE_D8: + /* Block Erase 0xd8 */ + case JEDEC_BE_D7: + /* Block Erase 0xd7 */ + case JEDEC_SE: + /* Sector Erase */ + case JEDEC_BYTE_PROGRAM: + /* Write memory byte */ + case JEDEC_AAI_WORD_PROGRAM: + /* Write AAI word */ + return 1; + } + return 0; +} + +static void ene_spi_start(const ene_chip_t *chip) +{ + int cfg; + + cfg = ene_read(chip, REG_SPI_CONFIG); + cfg |= CFG_CSn_FORCE_LOW; + cfg |= CFG_COMMAND_WRITE_ENABLE; + ene_write(chip, REG_SPI_CONFIG, cfg); + + wait_cycles(chip, ENE_SPI_DELAY_CYCLE); +} + +static void ene_spi_end(const ene_chip_t *chip) +{ + int cfg; + + cfg = ene_read(chip, REG_SPI_CONFIG); + cfg &= ~CFG_CSn_FORCE_LOW; + cfg |= CFG_COMMAND_WRITE_ENABLE; + ene_write(chip, REG_SPI_CONFIG, cfg); + + wait_cycles(chip, ENE_SPI_DELAY_CYCLE); +} + +static int ene_spi_wait(const ene_chip_t *chip) +{ + struct timeval begin, now; + + gettimeofday(&begin, NULL); + while(ene_read(chip, REG_SPI_CONFIG) & CFG_STATUS) { + gettimeofday(&now, NULL); + if ((now.tv_sec - begin.tv_sec) >= EC_COMMAND_TIMEOUT) { + msg_pdbg("%s: spi busy\n", __func__); + return 1; + } + } + return 0; +} + +static int ene_pause_ec(ene_lpc_data_t *ctx_data) +{ + struct timeval begin, now; + const ene_chip_t *chip = ctx_data->chip; + + if (!chip->ec_pause_cmd) + return -1; + + /* EC prepare pause */ + ec_command(chip, chip->ec_pause_cmd, chip->ec_pause_data); + + gettimeofday(&begin, NULL); + /* Spin wait for EC ready */ + while (ene_read(chip, chip->ec_status_buf) != + chip->ec_is_pausing) { + gettimeofday(&now, NULL); + if ((now.tv_sec - begin.tv_sec) >= + EC_COMMAND_TIMEOUT) { + msg_pdbg("%s: unable to pause ec\n", __func__); + return -1; + } + } + + + gettimeofday(&ctx_data->pause_begin, NULL); + ctx_data->ec_state = EC_STATE_IDLE; + return 0; +} + +static int ene_resume_ec(ene_lpc_data_t *ctx_data) +{ + struct timeval begin, now; + const ene_chip_t *chip = ctx_data->chip; + + if (chip->chip_id == ENE_KB94X) + OUTB(0xff, ENE_KB94X_PAUSE_WAKEUP_PORT); + else + /* Trigger 8051 interrupt to resume */ + ene_write(chip, REG_EC_EXTCMD, 0xff); + + gettimeofday(&begin, NULL); + while (ene_read(chip, chip->ec_status_buf) != + chip->ec_is_running) { + gettimeofday(&now, NULL); + if ((now.tv_sec - begin.tv_sec) >= + EC_COMMAND_TIMEOUT) { + msg_pdbg("%s: unable to resume ec\n", __func__); + return -1; + } + } + + ctx_data->ec_state = EC_STATE_NORMAL; + return 0; +} + +static int ene_pause_timeout_check(ene_lpc_data_t *ctx_data) +{ + struct timeval pause_now; + gettimeofday(&pause_now, NULL); + if ((pause_now.tv_sec - ctx_data->pause_begin.tv_sec) >= + EC_PAUSE_TIMEOUT) { + if(ene_resume_ec(ctx_data) == 0) + ene_pause_ec(ctx_data); + + } + return 0; +} + +static int ene_reset_ec(ene_lpc_data_t *ctx_data) +{ + uint8_t reg; + struct timeval begin, now; + const ene_chip_t *chip = ctx_data->chip; + + gettimeofday(&begin, NULL); + + /* EC prepare reset */ + ec_command(chip, chip->ec_reset_cmd, chip->ec_reset_data); + + /* Spin wait for EC ready */ + while (ene_read(chip, chip->ec_status_buf) != + chip->ec_is_stopping) { + gettimeofday(&now, NULL); + if ((now.tv_sec - begin.tv_sec) >= + EC_COMMAND_TIMEOUT) { + msg_pdbg("%s: unable to reset ec\n", __func__); + return -1; + } + } + + /* Wait 1 second */ + sleep(1); + + /* Reset 8051 */ + reg = ene_read(chip, REG_8051_CTRL); + reg |= CPU_RESET; + ene_write(chip, REG_8051_CTRL, reg); + + ctx_data->ec_state = EC_STATE_RESET; + return 0; +} + +static int ene_enter_flash_mode(ene_lpc_data_t *ctx_data) +{ + if (ene_pause_ec(ctx_data)) + return ene_reset_ec(ctx_data); + return 0; +} + +static int ene_spi_send_command(const struct flashctx *flash, + unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + unsigned int i; + int tries = EC_RESET_TRIES; + ene_lpc_data_t *ctx_data = (ene_lpc_data_t *)flash->mst->spi.data; + const ene_chip_t *chip = ctx_data->chip; + + if (ctx_data->ec_state == EC_STATE_IDLE && is_spicmd_write(writearr[0])) { + do { + /* Enter reset mode if we need to write/erase */ + if (ene_resume_ec(ctx_data)) + continue; + + if (!ene_reset_ec(ctx_data)) + break; + } while (--tries > 0); + + if (!tries) { + msg_perr("%s: EC failed reset, skipping write\n", __func__); + ctx_data->ec_state = EC_STATE_IDLE; + return 1; + } + } + else if(chip->chip_id == ENE_KB94X && ctx_data->ec_state == EC_STATE_IDLE) + ene_pause_timeout_check(ctx_data); + + ene_spi_start(chip); + + for (i = 0; i < writecnt; i++) { + ene_write(chip, REG_SPI_COMMAND, writearr[i]); + if (ene_spi_wait(chip)) { + msg_pdbg("%s: write count %d\n", __func__, i); + return 1; + } + } + + for (i = 0; i < readcnt; i++) { + /* Push data by clock the serial bus */ + ene_write(chip, REG_SPI_COMMAND, 0); + if (ene_spi_wait(chip)) { + msg_pdbg("%s: read count %d\n", __func__, i); + return 1; + } + readarr[i] = ene_read(chip, REG_SPI_DATA); + if (ene_spi_wait(chip)) { + msg_pdbg("%s: read count %d\n", __func__, i); + return 1; + } + } + + ene_spi_end(chip); + return 0; +} + +static int ene_leave_flash_mode(void *data) +{ + ene_lpc_data_t *ctx_data = (ene_lpc_data_t *)data; + const ene_chip_t *chip = ctx_data->chip; + int rv = 0; + uint8_t reg; + struct timeval begin, now; + + if (ctx_data->ec_state == EC_STATE_RESET) { + reg = ene_read(chip, REG_8051_CTRL); + reg &= ~CPU_RESET; + ene_write(chip, REG_8051_CTRL, reg); + + gettimeofday(&begin, NULL); + /* EC restart */ + while (ene_read(chip, chip->ec_status_buf) != + chip->ec_is_running) { + gettimeofday(&now, NULL); + if ((now.tv_sec - begin.tv_sec) >= + EC_RESTART_TIMEOUT) { + msg_pdbg("%s: ec restart busy\n", __func__); + rv = 1; + goto exit; + } + } + msg_pdbg("%s: send ec restart\n", __func__); + ec_command(chip, chip->ec_restart_cmd, + chip->ec_restart_data); + + ctx_data->ec_state = EC_STATE_NORMAL; + rv = 0; + goto exit; + } + + rv = ene_resume_ec(ctx_data); + +exit: + /* + * Trigger ec interrupt after pause/reset by sending 0x80 + * to bios command port. + */ + OUTB(0x80, chip->port_bios); + free(data); + return rv; +} + +static struct spi_master spi_master_ene = { + .max_data_read = 256, + .max_data_write = 256, + .command = ene_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + +int ene_lpc_init() +{ + uint8_t hwver, ediid, i; + int ret = 0; + char *p = NULL; + ene_lpc_data_t *ctx_data = NULL; + + msg_pdbg("%s\n", __func__); + + ctx_data = calloc(1, sizeof(ene_lpc_data_t)); + if (!ctx_data) { + msg_perr("Unable to allocate space for extra context data.\n"); + return 1; + } + ctx_data->ec_state = EC_STATE_NORMAL; + + p = extract_programmer_param("type"); + if (p && strcmp(p, "ec")) { + msg_pdbg("ene_lpc only supports \"ec\" type devices\n"); + ret = 1; + goto ene_probe_spi_flash_exit; + } + + for (i = 0; i < ENE_LAST; ++i) { + ctx_data->chip = &ene_chips[i]; + + hwver = ene_read(ctx_data->chip, REG_EC_HWVER); + ediid = ene_read(ctx_data->chip, REG_EC_EDIID); + + if(hwver == ene_chips[i].hwver && + ediid == ene_chips[i].ediid) { + break; + } + } + + if (i == ENE_LAST) { + msg_pdbg("ENE EC not found (probe failed)\n"); + ret = 1; + goto ene_probe_spi_flash_exit; + } + + /* TODO: probe the EC stop protocol + * + * Compal - ec_command(0x41, 0xa1) returns 43 4f 4d 50 41 4c 9c + */ + + + if (register_shutdown(ene_leave_flash_mode, ctx_data)) { + ret = 1; + goto ene_probe_spi_flash_exit; + } + + ene_enter_flash_mode(ctx_data); + + internal_buses_supported |= BUS_LPC; + spi_master_ene.data = ctx_data; + register_spi_master(&spi_master_ene); + msg_pdbg("%s: successfully initialized ene\n", __func__); + +ene_probe_spi_flash_exit: + free(p); + if (ret) + free(ctx_data); + return ret; +} + +#endif /* __i386__ || __x86_64__ */ diff --git a/flashrom.c b/flashrom.c index 4a30986..35ac6f5 100644 --- a/flashrom.c +++ b/flashrom.c @@ -279,6 +279,18 @@ }, #endif +#if CONFIG_ENE_LPC == 1 + { + .name = "ene_lpc", + .type = OTHER, + .devs.note = "ENE LPC interface keyboard controller\n", + .init = ene_lpc_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_RAYER_SPI == 1 { .name = "rayer_spi", diff --git a/meson.build b/meson.build index 04176f3..180b5dd 100644 --- a/meson.build +++ b/meson.build @@ -40,6 +40,7 @@ config_digilent_spi = get_option('config_digilent_spi') config_drkaiser = get_option('config_drkaiser') config_dummy = get_option('config_dummy') +config_ene_lpc = get_option('config_ene_lpc') config_ft2232_spi = get_option('config_ft2232_spi') config_gfxnvidia = get_option('config_gfxnvidia') config_raiden = get_option('config_raiden') @@ -202,6 +203,10 @@ cargs += '-DCONFIG_INTERNAL_DMI=1' endif endif +if config_ene_lpc + srcs += 'ene_lpc.c' + cargs += '-DCONFIG_ENE_LPC=1' +endif if config_it8212 srcs += 'it8212.c' cargs += '-DCONFIG_IT8212=1' diff --git a/meson_options.txt b/meson_options.txt index ac48e4e..ba5130b 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -11,6 +11,7 @@ option('config_digilent_spi', type : 'boolean', value : true, description : 'Digilent Development board JTAG') option('config_drkaiser', type : 'boolean', value : true, description : 'Dr. Kaiser') option('config_dummy', type : 'boolean', value : true, description : 'dummy tracing') +option('config_ene_lpc', type : 'boolean', value : true, description : 'ENE LPC interface keyboard controller') option('config_ft2232_spi', type : 'boolean', value : true, description : 'FT2232 SPI dongles') option('config_gfxnvidia', type : 'boolean', value : true, description : 'NVIDIA graphics cards') option('config_raiden', type : 'boolean', value : true, description : 'ChromiumOS Servo DUT debug board') diff --git a/programmer.h b/programmer.h index c5cab18..b3bc700 100644 --- a/programmer.h +++ b/programmer.h @@ -61,6 +61,9 @@ #if CONFIG_ATAPROMISE == 1 PROGRAMMER_ATAPROMISE, #endif +#if CONFIG_ENE_LPC == 1 + PROGRAMMER_ENE_LPC, +#endif #if CONFIG_IT8212 == 1 PROGRAMMER_IT8212, #endif @@ -578,6 +581,11 @@ extern const struct dev_entry devs_digilent_spi[]; #endif +/* ene_lpc.c */ +#if CONFIG_ENE_LPC == 1 +int ene_lpc_init(void); +#endif + /* jlink_spi.c */ #if CONFIG_JLINK_SPI == 1 int jlink_spi_init(void); -- To view, visit https://review.coreboot.org/c/flashrom/+/44580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I970afd8c1bd92c159c60e09f22e2f18c0433729d Gerrit-Change-Number: 44580 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Ding <victording(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC] flashchips, writeprotect_ranges: add range decoding function
by Nikolai Artemiev (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk. Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58480 ) Change subject: [RFC] flashchips, writeprotect_ranges: add range decoding function ...................................................................... Patch Set 8: (2 comments) File writeprotect_ranges.c: https://review.coreboot.org/c/flashrom/+/58480/comment/a8a45e4e_154f4f85 PS7, Line 20: TODO > Need new line before TODO. Done https://review.coreboot.org/c/flashrom/+/58480/comment/9eb84193_5f71d849 PS7, Line 91: > Probably can remove empty line at the end? (line 91) Done -- To view, visit https://review.coreboot.org/c/flashrom/+/58480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id163ed80938a946a502ed116e48e8236e36eb203 Gerrit-Change-Number: 58480 Gerrit-PatchSet: 8 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 04 Nov 2021 01:27:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: [RFC] writeprotect: add functions to read and write wp_chip_state
by Nikolai Artemiev (Code Review) 04 Nov '21

04 Nov '21

Attention is currently required from: Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk. Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58479 ) Change subject: [RFC] writeprotect: add functions to read and write wp_chip_state ...................................................................... Patch Set 7: (3 comments) File writeprotect.c: https://review.coreboot.org/c/flashrom/+/58479/comment/11276b83_372f1b8d PS6, Line 26: print_wp_chip_state > You can move print_wp_chip_state here on the top, and avoid forward declaration. I think it's a bit nicer to keep it with the other printing functions that get added at the bottom of the file. Alternatively I can change it to a function that writes to a string and declare it in the header since that would be somewhat useful for wp users. https://review.coreboot.org/c/flashrom/+/58479/comment/32435360_69c2f8c5 PS6, Line 28: static int read_reg_bit( : const struct flashctx *flash, : const struct reg_bit_info bit, : uint8_t *value, : bool *present) > Just to check: does this not fit into 112 chars? It really helps to grep when all parameters are on […] Done https://review.coreboot.org/c/flashrom/+/58479/comment/7a1d6e9f_42837122 PS6, Line 73: void *suppress_unused_warning_for_read_wp_chip_state = read_wp_chip_state; > This merely avoids a warning about the `read_wp_chip_state()` function being unused. […] I can move the read/write functions into another commit if it really would be easier to review them that way, but they are helper functions that get used in several places so they don't really belong with any other change. They are also quite complicated but do a well defined task so I thought it would be easier to them review them on their own. -- To view, visit https://review.coreboot.org/c/flashrom/+/58479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad Gerrit-Change-Number: 58479 Gerrit-PatchSet: 7 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 04 Nov 2021 01:26:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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flashrom-gerrit November 2021