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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58481
to look at the new patch set (#13).
Change subject: libflashrom,writeprotect: add flashrom_wp_get_available_ranges()
......................................................................
libflashrom,writeprotect: add flashrom_wp_get_available_ranges()
Generate list of available ranges by enumerating all possible values
that range bits (BPx, TB, ...) can take and using the chip's range
decoding function to get the range associated with each one.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-list
BRANCH=none
Change-Id: Id51f038f03305c8536d80313e52f77d27835f34d
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M libflashrom.h
M writeprotect.c
2 files changed, 146 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/81/58481/13
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58480
to look at the new patch set (#13).
Change subject: flashchips,writeprotect_ranges: add range decoding function
......................................................................
flashchips,writeprotect_ranges: add range decoding function
Allow chips to specify functions that map status register bits to
protection ranges. These are used to enumerate available ranges and
determine the protection state of chips. The patch also adds a range
decoding function for the example chips. Many other chips can also be
handled by it, though some will require different functions (e.g.
MX25L6406 and related chips).
Another approach that has been tried in cros flashrom is maintaining
tables of range data, but it quickly becomes error prone and hard to
validate.
Using a function to interpret the ranges allows compact encoding with
most chips and is flexible enough to allow chips with less predictable
ranges to be handled as well.
BUG=b:195381327,b:153800563
TEST=dumped range tables, checked against datasheets
BRANCH=none
Change-Id: Id163ed80938a946a502ed116e48e8236e36eb203
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M Makefile
M chipdrivers.h
M flash.h
M flashchips.c
M libflashrom.h
M meson.build
A writeprotect_ranges.c
7 files changed, 115 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/80/58480/13
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58479
to look at the new patch set (#12).
Change subject: libflashrom,writeprotect: add flashrom_wp_{read,write}_chip_config()
......................................................................
libflashrom,writeprotect: add flashrom_wp_{read,write}_chip_config()
The read/write functions map between register values and `struct
wp_chip_state` using the chip's register bit map.
All currently supported chips can be handled with a single pair of
read/write functions, though an option for chips to override them might
be necessary in the future.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
BRANCH=none
Change-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M libflashrom.h
M writeprotect.c
2 files changed, 168 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/58479/12
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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58570
to look at the new patch set (#9).
Change subject: spi25_statusreg,flashchips: add SR2 read/write support
......................................................................
spi25_statusreg,flashchips: add SR2 read/write support
This patch adds support for reading and writing the second status
register and enables it on a limited set of flash chips.
Chip support for RDSR2/WRSR2/extended WRSR is represented using feature
flags to be consistent with how other SPI capabilities are represented.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
TEST=logged SR2 read/write values during wp commands
BRANCH=none
Change-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flash.h
M flashchips.c
M spi.h
M spi25_statusreg.c
4 files changed, 58 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/70/58570/9
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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58475
to look at the new patch set (#11).
Change subject: spi25_statusreg: make register read/write functions generic
......................................................................
spi25_statusreg: make register read/write functions generic
This patch adds new spi_{read,write}_register() functions that take the
source/destination register as an argument. Currently they can only
access SR1, support for other registers will be added in another patch.
Since we're refactoring things, this commit also makes
spi_read_register() return an error code, making it possible to identify
error conditions that spi_read_status_register() concealed.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
BRANCH=none
Change-Id: I0a3951bbf993f2d8d830143b29d3ce16cc6901d7
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M chipdrivers.h
M flash.h
M spi25_statusreg.c
3 files changed, 77 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/75/58475/11
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58480 )
Change subject: flashchips,writeprotect_ranges: add range decoding function
......................................................................
Patch Set 12:
(1 comment)
File writeprotect_ranges.c:
https://review.coreboot.org/c/flashrom/+/58480/comment/a7f527e7_3ed58e4c
PS12, Line 41: }
: else {
As a reminder, this should be on one line
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