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Change subject: libflashrom,writeprotect: add flashrom_wp_{config,range,mode}_to_str()
......................................................................
Patch Set 15:
(1 comment)
File writeprotect.c:
https://review.coreboot.org/c/flashrom/+/58484/comment/493bc307_a801332a
PS15, Line 451: }
In this case braces not needed: only one statement in for loop.
And same below in another for loop.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/59529
to look at the new patch set (#3).
Change subject: spi25_statusreg: delete read_status_register()
......................................................................
spi25_statusreg: delete read_status_register()
BUG=b:195381327,b:153800563
TEST=builds
BRANCH=none
Change-Id: I146b4b5439872e66c5d33e156451a729d248c7da
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M chipdrivers.h
M it87spi.c
M s25f.c
M spi25.c
M spi25_statusreg.c
5 files changed, 119 insertions(+), 54 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/29/59529/3
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/59528
to look at the new patch set (#3).
Change subject: spi25_statusreg: inline spi_write_register_flag()
......................................................................
spi25_statusreg: inline spi_write_register_flag()
BUG=b:195381327,b:153800563
TEST=builds
BRANCH=none
Change-Id: I4996b0848d0ed09032bad2ab13ab1f40bbfc0304
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M spi25_statusreg.c
1 file changed, 46 insertions(+), 60 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/28/59528/3
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Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58482 )
Change subject: libflashrom,writeprotect: add flashrom_wp_set_range()
......................................................................
Patch Set 14:
(1 comment)
Patchset:
PS6:
> Thanks Nico and Edward for the points above. […]
I'm going to mark this resolved, we can continue discussing it on the CLI patch: CB:58738.
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Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58481 )
Change subject: libflashrom,writeprotect: add flashrom_wp_get_available_ranges()
......................................................................
Patch Set 14:
(1 comment)
File writeprotect.c:
https://review.coreboot.org/c/flashrom/+/58481/comment/d8e75d46_0372ed65
PS10, Line 192: if (ord == 0) ord = a->range.len - b->range.len;
> Same as before: please move conditional body on new line (and for all the rest of code in the chain) […]
Done
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Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58480 )
Change subject: flashchips,writeprotect_ranges: add range decoding function
......................................................................
Patch Set 14:
(3 comments)
File flash.h:
https://review.coreboot.org/c/flashrom/+/58480/comment/f5e1fba1_1d35f7c2
PS10, Line 319: decode_range
> I like that name better, but it won't fit within 2 tabs like other flashchip fields so the flashchip […]
Resolving.
File writeprotect.c:
https://review.coreboot.org/c/flashrom/+/58480/comment/50403122_339ee94d
PS12, Line 39: int ret = spi_read_register(flash, bit.reg, value);
: return ret;
> You forgot to add `if (ret)` line.
Done
File writeprotect_ranges.c:
https://review.coreboot.org/c/flashrom/+/58480/comment/6805a059_10e30e57
PS12, Line 41: }
: else {
> As a reminder, this should be on one line
Done
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Change subject: libflashrom,writeprotect: add flashrom_wp_{read,write}_chip_config()
......................................................................
Patch Set 13:
(5 comments)
File libflashrom.h:
https://review.coreboot.org/c/flashrom/+/58479/comment/ac4bbb05_a11eb75b
PS11, Line 4: 2010
> It is 2021 now, you are adding the lines in 2021
The `enum flashrom_wp_mode` definition and comments came from the 2010 file. I'll check what this should be.
File writeprotect.c:
https://review.coreboot.org/c/flashrom/+/58479/comment/76cdc8e6_b033381a
PS9, Line 128: return ret;
> But it is still the same, you haven't changed the code? […]
Done
https://review.coreboot.org/c/flashrom/+/58479/comment/78812e62_1388f64b
PS9, Line 161: ord = cfga->cmp - cfgb->cmp;
> You forgot :)
Oops, I changed it but as part of a later CL :)
I've moved it back to this one now
File writeprotect.c:
https://review.coreboot.org/c/flashrom/+/58479/comment/02c34c71_7be199fa
PS11, Line 51: cfg
> Should be "param".
Done
https://review.coreboot.org/c/flashrom/+/58479/comment/9cbea18b_58e43d78
PS11, Line 145: * @cfg[in] cfga The first configuration to compare.
: * @cfg[in] cfgb The second configuration to compare.
> "@cfg" -> "@param"
Done
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Change subject: spi25_statusreg,flashchips: add SR2 read/write support
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS7:
> Cool! When I open CB:58476 there is the chain which looks like previous version of what is under rev […]
Those links are a snapshot of the other CLs that CB:58476 was uploaded with (older patchset number but the same CL number). They are needed for the current chain though so we should leave them open.
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