June 2020 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: sb600spi -> fchspi: Rename AMD SPI programmer
by Edward O'Callaghan (Code Review) 24 Jun '20

24 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36434 ) Change subject: sb600spi -> fchspi: Rename AMD SPI programmer ...................................................................... sb600spi -> fchspi: Rename AMD SPI programmer The AMD FCH controller has two main SPI ip core variants, the so-called 'sb600' variant and the newer 'spi100' variant. The sb600spi.c driver supports both variants and so its name isn't very general. Here we rename it to be more general. Change-Id: Iad92fb224954d66968e7aeb75cb515f075a26ac8 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M Makefile M chipset_enable.c R fchspi.c M meson.build M programmer.h 5 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/36434/1 diff --git a/Makefile b/Makefile index f0a1b61..143a8c1 100644 --- a/Makefile +++ b/Makefile @@ -767,7 +767,7 @@ FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o internal.o ifeq ($(ARCH), x86) -PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o amd_imc.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o fchspi.o amd_imc.o wbsio_spi.o mcp6x_spi.o PROGRAMMER_OBJS += ichspi.o dmi.o ifeq ($(CONFIG_INTERNAL_DMI), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL_DMI=1' diff --git a/chipset_enable.c b/chipset_enable.c index b55852c..e57a18e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1297,7 +1297,7 @@ return enable_flash_amd_via(dev, name, 0xE0); } -static int enable_flash_sb600(struct pci_dev *dev, const char *name) +static int enable_flash_fch(struct pci_dev *dev, const char *name) { uint32_t prot; uint8_t reg; @@ -1330,7 +1330,7 @@ internal_buses_supported &= BUS_LPC | BUS_FWH; - ret = sb600_probe_spi(dev); + ret = fch_probe_spi(dev); /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); @@ -1685,16 +1685,16 @@ const struct penable chipset_enables[] = { #if defined(__i386__) || defined(__x86_64__) {0x1002, 0x4377, B_PFL, OK, "ATI", "SB400", enable_flash_sb400}, - {0x1002, 0x438d, B_FLS, OK, "AMD", "SB600", enable_flash_sb600}, - {0x1002, 0x439d, B_FLS, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600}, + {0x1002, 0x438d, B_FLS, OK, "AMD", "SB600", enable_flash_fch}, + {0x1002, 0x439d, B_FLS, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_fch}, {0x100b, 0x0510, B_PFL, NT, "AMD", "SC1100", enable_flash_sc1100}, {0x1022, 0x2080, B_PFL, OK, "AMD", "CS5536", enable_flash_cs5536}, {0x1022, 0x2090, B_PFL, OK, "AMD", "CS5536", enable_flash_cs5536}, {0x1022, 0x3000, B_PFL, OK, "AMD", "Elan SC520", get_flashbase_sc520}, {0x1022, 0x7440, B_PFL, OK, "AMD", "AMD-768", enable_flash_amd_768_8111}, {0x1022, 0x7468, B_PFL, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111}, - {0x1022, 0x780e, B_FLS, OK, "AMD", "FCH", enable_flash_sb600}, - {0x1022, 0x790e, B_FLS, OK, "AMD", "FP4", enable_flash_sb600}, + {0x1022, 0x780e, B_FLS, OK, "AMD", "FCH", enable_flash_fch}, + {0x1022, 0x790e, B_FLS, OK, "AMD", "FP4", enable_flash_fch}, {0x1039, 0x0406, B_PFL, NT, "SiS", "501/5101/5501", enable_flash_sis501}, {0x1039, 0x0496, B_PFL, NT, "SiS", "85C496+497", enable_flash_sis85c496}, {0x1039, 0x0530, B_PFL, OK, "SiS", "530", enable_flash_sis530}, diff --git a/sb600spi.c b/fchspi.c similarity index 99% rename from sb600spi.c rename to fchspi.c index 7bdd11f..e0eab07 100644 --- a/sb600spi.c +++ b/fchspi.c @@ -579,7 +579,7 @@ return amd_imc_shutdown(dev); } -int sb600_probe_spi(struct pci_dev *dev) +int fch_probe_spi(struct pci_dev *dev) { struct pci_dev *smbus_dev; uint32_t tmp; diff --git a/meson.build b/meson.build index d1f663f..d4bbff7 100644 --- a/meson.build +++ b/meson.build @@ -182,7 +182,7 @@ srcs += 'it85spi.c' srcs += 'it87spi.c' srcs += 'mcp6x_spi.c' - srcs += 'sb600spi.c' + srcs += 'fchspi.c' srcs += 'wbsio_spi.c' endif config_bitbang_spi = true diff --git a/programmer.h b/programmer.h index e42c6bb..e2cadd9 100644 --- a/programmer.h +++ b/programmer.h @@ -657,8 +657,8 @@ /* mcp6x_spi.c */ int mcp6x_spi_init(int want_spi); -/* sb600spi.c */ -int sb600_probe_spi(struct pci_dev *dev); +/* fchspi.c */ +int fch_probe_spi(struct pci_dev *dev); /* wbsio_spi.c */ int wbsio_check_for_spi(void); -- To view, visit https://review.coreboot.org/c/flashrom/+/36434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iad92fb224954d66968e7aeb75cb515f075a26ac8 Gerrit-Change-Number: 36434 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in flashrom[master]: sb600spi.c: Improve IMC runtime detection in handle_imc()
by Edward O'Callaghan (Code Review) 24 Jun '20

24 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36424 ) Change subject: sb600spi.c: Improve IMC runtime detection in handle_imc() ...................................................................... sb600spi.c: Improve IMC runtime detection in handle_imc() The IMC detection in sb600spi is very rudimentary and incomplete. This expands it so that it can actually detect not only whether an IMC is in the system, but whether it's active or not. This is based off ChromiumOS's fork of flashrom where the solution looks to be originally authored by Martin Roth in b/62141938. Change-Id: I13fb2300475c06aad09a4f0e8cd032e212556b14 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M sb600spi.c 1 file changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/24/36424/1 diff --git a/sb600spi.c b/sb600spi.c index c89d5a9..3c83b7b 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -55,6 +55,15 @@ #define FIFO_SIZE_OLD 8 #define FIFO_SIZE_YANGTZE 71 +#define PM_INDEX 0xCD6 +#define PM_DATA 0xCD7 +#define ISA_CONTROL 0x04 +#define MMIO_EN 0x02 +#define ACPI_MMIO_BASE 0xFED80000 +#define MISC_BASE 0xE00 +#define STRAP_STATUS 0x80 +#define EC_ENABLE_STRAP 0x04 + static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); static int spi100_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, @@ -80,6 +89,12 @@ .write_aai = default_spi_write_aai, }; +static uint8_t pm_ioread(uint8_t addr) +{ + OUTB(addr, PM_INDEX); + return INB(PM_DATA); +} + static int find_smbus_dev(uint16_t vendor, uint16_t device) { struct pci_dev *smbus_dev = pci_dev_find(vendor, device); @@ -522,6 +537,25 @@ return 0; } + /* On Yangtze and newer chips, check the EcEnableStrap bit */ + if ((amd_gen >= CHIPSET_YANGTZE) && (pm_ioread(ISA_CONTROL) & MMIO_EN )) { + uint8_t *AcpiMMIO = rphysmap("AMD ACPI registers", ACPI_MMIO_BASE & 0xfffff000, 0x1000); + if (AcpiMMIO != ERROR_PTR) { + AcpiMMIO += MISC_BASE + STRAP_STATUS; + uint32_t straps = mmio_readl(AcpiMMIO); + if ((straps & EC_ENABLE_STRAP) == 0){ + msg_pinfo("IMC is not active.\n"); + return 0; + } else { + msg_pinfo("IMC IS active! Straps: %08x (%p)\n", straps, (void *)AcpiMMIO); + msg_pinfo("StrapOverride: %08x\n", mmio_readl(AcpiMMIO + 4)); + } + + } else { + msg_pinfo("Error reading AMD ACPI registers.\n"); + } + } + if (!amd_imc_force) programmer_may_write = 0; msg_pinfo("Writes have been disabled for safety reasons because the presence of the IMC\n" -- To view, visit https://review.coreboot.org/c/flashrom/+/36424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I13fb2300475c06aad09a4f0e8cd032e212556b14 Gerrit-Change-Number: 36424 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 4

Change in flashrom[master]: [WIP] Add .clang-format to help with patch formatting
by David Hendricks (Code Review) 23 Jun '20

23 Jun '20

Hello Vadim Bendebury, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/38673 to review the following change. Change subject: [WIP] Add .clang-format to help with patch formatting ...................................................................... [WIP] Add .clang-format to help with patch formatting This is based on CB:38208 by Vadim, but with a few added changes. Here is the original commit message. This is a copy from the coreboot tree, could be tweaked to better match the flashrom tree if there are any differences. Once this file is in place a script could be deployed which would format only new/changed lines in git patches. Change-Id: I1fe22809c4a2d73fa02f4de55290d990a9750b86 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- A .clang-format 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/38673/1 diff --git a/.clang-format b/.clang-format new file mode 100644 index 0000000..45c116b --- /dev/null +++ b/.clang-format @@ -0,0 +1,21 @@ +BasedOnStyle: LLVM +Language: Cpp +IndentWidth: 8 +UseTab: Always +BreakBeforeBraces: Linux +AllowShortIfStatementsOnASingleLine: false +IndentCaseLabels: false +SortIncludes: false +ContinuationIndentWidth: 8 +ColumnLimit: 112 +AlwaysBreakBeforeMultilineStrings: true +AllowShortLoopsOnASingleLine: false +AllowShortFunctionsOnASingleLine: false +AlignEscapedNewlinesLeft: false +AlignTrailingComments: true +AllowAllParametersOfDeclarationOnNextLine: false +AlignAfterOpenBracket: true +SpaceAfterCStyleCast: false +MaxEmptyLinesToKeep: 2 +BreakBeforeBinaryOperators: NonAssignment +BreakStringLiterals: false -- To view, visit https://review.coreboot.org/c/flashrom/+/38673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1fe22809c4a2d73fa02f4de55290d990a9750b86 Gerrit-Change-Number: 38673 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-MessageType: newchange

2 7

Change in flashrom[master]: [WIP] Add clang-format on/off markers where appropriate
by David Hendricks (Code Review) 23 Jun '20

23 Jun '20

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/42549 ) Change subject: [WIP] Add clang-format on/off markers where appropriate ...................................................................... [WIP] Add clang-format on/off markers where appropriate Change-Id: I6d31ad2031b7467ba35fd87422adc66fcd942c29 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M board_enable.c M chipset_enable.c M print.c 3 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/49/42549/1 diff --git a/board_enable.c b/board_enable.c index 9cf0103..5bfc4a6 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2348,6 +2348,7 @@ * main pci ids are still required to match, as a safeguard. */ +/* clang-format off */ /* Please keep this list alphabetically ordered by vendor/board name. */ const struct board_match board_matches[] = { @@ -2530,6 +2531,7 @@ #endif { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */ }; +/* clang-format on */ int selfcheck_board_enables(void) { diff --git a/chipset_enable.c b/chipset_enable.c index 632679c..6713842 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1689,6 +1689,7 @@ #define B_LS (BUS_LPC | BUS_SPI) #define B_S (BUS_SPI) +/* clang-format off */ /* Please keep this list numerically sorted by vendor/device ID. */ const struct penable chipset_enables[] = { #if defined(__i386__) || defined(__x86_64__) @@ -2066,6 +2067,7 @@ #endif {0}, }; +/* clang-format on */ int chipset_flash_enable(void) { diff --git a/print.c b/print.c index feca45e..c5ead0c 100644 --- a/print.c +++ b/print.c @@ -514,6 +514,7 @@ #define B(vendor, name, status, url, note) { vendor, name, status } #endif +/* clang-format off */ /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_known[] = { #if defined(__i386__) || defined(__x86_64__) @@ -1142,7 +1143,9 @@ {0}, }; +/* clang-format on */ +/* clang-format off */ /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info laptops_known[] = { #if defined(__i386__) || defined(__x86_64__) @@ -1177,3 +1180,4 @@ {0}, }; #endif +/* clang-format on */ -- To view, visit https://review.coreboot.org/c/flashrom/+/42549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6d31ad2031b7467ba35fd87422adc66fcd942c29 Gerrit-Change-Number: 42549 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in flashrom[master]: mysteries_intel: Add a section for software vs hardware sequencing
by David Hendricks (Code Review) 20 Jun '20

20 Jun '20

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/42485 ) Change subject: mysteries_intel: Add a section for software vs hardware sequencing ...................................................................... mysteries_intel: Add a section for software vs hardware sequencing This attempts to explain software sequencing, hardware sequencing, and the "Opaque flash chip". Change-Id: I2445e926aad96060f26d0bc55dd7642c1a404296 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M Documentation/mysteries_intel.txt 1 file changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/85/42485/1 diff --git a/Documentation/mysteries_intel.txt b/Documentation/mysteries_intel.txt index 60ad21a..8ed7b65 100644 --- a/Documentation/mysteries_intel.txt +++ b/Documentation/mysteries_intel.txt @@ -5,6 +5,47 @@ A0h), so we have no clue if or where it is on ICH8. Out current policy is to not touch it at all and assume/hope it is 0. += Software Sequencing vs. Hardware Sequenching and the "Opaque flash chip" = +Software sequencing and hardware sequencing are two methods used to interface +with the SPI controller on Intel platforms. They can be selected using either +ich_spi_mode=swseq and ich_spi_mode=hwseq programmer parameters. Flashrom will +attempt to automatically detect which mode to use. + +Software sequencing is the traditional method whereby software running on the +CPU handles most of the logic needed to interact with the flash chip. This +offers good flexibility since the user can utilize any opcode available in the +OPMENU registers, and OPMENU can be left unlocked or on coreboot-supported +platforms the owner of the system may program it for their needs before locking +it. Advanced or non-standard features of a chip such as write protection and +OTP may be therefore be directly utilized by software. + +Hardware sequencing is a newer method whereby most of the logic for interacting +with the SPI flash chip is contained within the SPI controller itself, and +software such as flashrom may only select a few operations chosen by Intel via +the Flash Cycle (FCYCLE) field. The chip must conform to specifications from +Intel for each chipset/PCH. There specs are given in the "SPI Programming Guide" +for each chipset/PCH and are usually available under NDA. + +Hardware sequencing simplifies things from a software perspective since the +software is guaranteed some minimal level of support and doesn't even need to +know the chip's ID and know its supported opcodes; it just needs to tell the +SPI controller to perform a certain type of transaction such as "read", "4k +block erase", etc. without knowing the actual opcodes used by the chip for the +transaction. Hence when using hardware sequencing one will see "Opaque flash +chip" as the chip's description, since flashrom will not necessarily even read +the chip's ID. This abstraction also allows the SPI controller to do things like +concatenating multiple chips to appear as a single large one. + +In many non-Intel systems the software has full control of a generic SPI +controller where the software controls the chip select and data buffer and also +constructs the payload including pre-op (e.g. write enable latch), opcode, +address, and data. Intel SPI flash controllers are purpose-built for flash chip +access and the software does not control the hardware directly. This makes Intel +SPI controllers less flexible from a software standpoint, however there are some +benefits such as guaranteed atomicity and multi-master arbitration needed for +modern Intel platforms where the CPU and various microprocessors can share the +same flash chip. + = SMM BIOS Write Protection = Sometimes a hardware vendor will enable "SMM BIOS Write Protect" (SMM_BWP) in the firmware during boot time. The bits that control SMM_BWP are in the -- To view, visit https://review.coreboot.org/c/flashrom/+/42485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2445e926aad96060f26d0bc55dd7642c1a404296 Gerrit-Change-Number: 42485 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

4 19

Change in flashrom[master]: tests/spi25.c: Add unit-test coverage of spi95.c
by Edward O'Callaghan (Code Review) 17 Jun '20

17 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/41656 ) Change subject: tests/spi25.c: Add unit-test coverage of spi95.c ...................................................................... tests/spi25.c: Add unit-test coverage of spi95.c BUG=b:157280555 BRANCH=none TEST=builds Change-Id: I6de59451b82131b58114b268ff6dd0b18cd5952b Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M tests/spi25.c M tests/tests.c M tests/tests.h 3 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/56/41656/1 diff --git a/tests/spi25.c b/tests/spi25.c index cf8345c..8a9b9ee 100644 --- a/tests/spi25.c +++ b/tests/spi25.c @@ -168,3 +168,22 @@ will_return(__wrap_spi_send_command, AT25F_RDID_INSIZE); assert_int_equal(0, probe_spi_at25f(&flashctx)); } + +/* spi95.c */ +void probe_spi_st95_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + /* chip total size < 64K. */ + uint32_t rdid_outsize = ST_M95_RDID_2BA_OUTSIZE; // 16 bit address + + will_return(__wrap_spi_send_command, rdid_outsize); + will_return(__wrap_spi_send_command, ST_M95_RDID); + will_return(__wrap_spi_send_command, ST_M95_RDID_INSIZE); + assert_int_equal(0, probe_spi_st95(&flashctx)); +} diff --git a/tests/tests.c b/tests/tests.c index 2ba293b..e04e204 100644 --- a/tests/tests.c +++ b/tests/tests.c @@ -50,6 +50,7 @@ cmocka_unit_test(probe_spi_res2_test_success), cmocka_unit_test(probe_spi_res3_test_success), cmocka_unit_test(probe_spi_at25f_test_success), + cmocka_unit_test(probe_spi_st95_test_success), /* spi95.c */ }; ret |= cmocka_run_group_tests_name("spi25.c tests", spi25_tests, NULL, NULL); diff --git a/tests/tests.h b/tests/tests.h index b4913f1..a20fb95 100644 --- a/tests/tests.h +++ b/tests/tests.h @@ -26,5 +26,6 @@ void probe_spi_res2_test_success(void **state); void probe_spi_res3_test_success(void **state); void probe_spi_at25f_test_success(void **state); +void probe_spi_st95_test_success(void **state); /* spi95.c */ #endif /* TESTS_H */ -- To view, visit https://review.coreboot.org/c/flashrom/+/41656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6de59451b82131b58114b268ff6dd0b18cd5952b Gerrit-Change-Number: 41656 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 5

Change in flashrom[master]: tests/: Add helper.c unit tests
by Edward O'Callaghan (Code Review) 17 Jun '20

17 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/41655 ) Change subject: tests/: Add helper.c unit tests ...................................................................... tests/: Add helper.c unit tests BUG=b:157280555 BRANCH=none TEST=builds Change-Id: If4a1fe7c499f51bb9d7cd48ef26caf9dfae3c1fa Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- A tests/helpers.c M tests/meson.build M tests/tests.c M tests/tests.h 4 files changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/55/41655/1 diff --git a/tests/helpers.c b/tests/helpers.c new file mode 100644 index 0000000..ab0863f --- /dev/null +++ b/tests/helpers.c @@ -0,0 +1,64 @@ +#include <include/test.h> + +#include "flash.h" + +#include <stdint.h> +#include <stdlib.h> + + +void address_to_bits_test_success(void **state) +{ + (void) state; /* unused */ + assert_int_equal(16, address_to_bits(0xAA55)); +} + +void bitcount_test_success(void **state) +{ + (void) state; /* unused */ + assert_int_equal(4, bitcount(0xAA)); +} + +void minmax_test_success(void **state) +{ + (void) state; /* unused */ + assert_int_equal(0x55, min(0xAA, 0x55)); + assert_int_equal(0xAA, max(0xAA, 0x55)); +} + +void strcat_realloc_test_success(void **state) +{ + (void) state; /* unused */ + const char src0[] = "hello"; + const char src1[] = " world"; + char *dest = calloc(1, 1); + dest = strcat_realloc(dest, src0); + dest = strcat_realloc(dest, src1); + assert_string_equal("hello world", dest); + free(dest); +} + +void tolower_string_test_success(void **state) +{ + (void) state; /* unused */ + char str[] = "HELLO AGAIN"; + assert_string_equal("HELLO AGAIN", str); + tolower_string(str); + assert_string_equal("hello again", str); +} + +void reverse_byte_test_success(void **state) +{ + (void) state; /* unused */ + assert_int_equal(0x5A, reverse_byte(0x5A)); + assert_int_equal(0x0F, reverse_byte(0xF0)); +} + +void reverse_bytes_test_success(void **state) +{ + (void) state; /* unused */ + uint8_t src[] = { 0xAA, 0x55 }; + uint8_t dst[2]; + reverse_bytes(dst, src, 2); + assert_int_equal(src[0], dst[1]); + assert_int_equal(src[1], dst[0]); +} diff --git a/tests/meson.build b/tests/meson.build index aad1372..3cd67b8 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -2,6 +2,7 @@ srcs = [ 'tests.c', + 'helpers.c', 'spi.c', 'flashrom.c', 'spi25.c', diff --git a/tests/tests.c b/tests/tests.c index a3ad791..2ba293b 100644 --- a/tests/tests.c +++ b/tests/tests.c @@ -18,6 +18,17 @@ { int ret = 0; + const struct CMUnitTest helpers_tests[] = { + cmocka_unit_test(address_to_bits_test_success), + cmocka_unit_test(bitcount_test_success), + cmocka_unit_test(minmax_test_success), + cmocka_unit_test(strcat_realloc_test_success), + cmocka_unit_test(tolower_string_test_success), + cmocka_unit_test(reverse_byte_test_success), + cmocka_unit_test(reverse_bytes_test_success), + }; + ret |= cmocka_run_group_tests_name("helpers.c tests", helpers_tests, NULL, NULL); + const struct CMUnitTest spi_tests[] = { cmocka_unit_test(registered_masters_test_success), cmocka_unit_test(programmer_init_test_success), diff --git a/tests/tests.h b/tests/tests.h index 688c280..b4913f1 100644 --- a/tests/tests.h +++ b/tests/tests.h @@ -1,6 +1,15 @@ #ifndef TESTS_H #define TESTS_H +/* helpers.c */ +void address_to_bits_test_success(void **state); +void bitcount_test_success(void **state); +void minmax_test_success(void **state); +void strcat_realloc_test_success(void **state); +void tolower_string_test_success(void **state); +void reverse_byte_test_success(void **state); +void reverse_bytes_test_success(void **state); + void registered_masters_test_success(void **state); void programmer_init_test_success(void **state); -- To view, visit https://review.coreboot.org/c/flashrom/+/41655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If4a1fe7c499f51bb9d7cd48ef26caf9dfae3c1fa Gerrit-Change-Number: 41655 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 6

Change in flashrom[master]: tests/: Add flashrom.c unit tests
by Edward O'Callaghan (Code Review) 17 Jun '20

17 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/41646 ) Change subject: tests/: Add flashrom.c unit tests ...................................................................... tests/: Add flashrom.c unit tests Change-Id: I2d9213f98c6c9639f2417466ba4895117e8d600a Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- A tests/flashrom.c M tests/meson.build M tests/tests.c M tests/tests.h 4 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/46/41646/1 diff --git a/tests/flashrom.c b/tests/flashrom.c new file mode 100644 index 0000000..ad46dd8 --- /dev/null +++ b/tests/flashrom.c @@ -0,0 +1,36 @@ +#include <include/test.h> + +#include "programmer.h" + +void flashbuses_to_text_test_success(void **state) +{ + (void) state; /* unused */ + + enum chipbustype bustype; + + bustype = BUS_NONSPI; + assert_string_equal(flashbuses_to_text(bustype), "Non-SPI"); + + bustype |= BUS_PARALLEL; + assert_string_not_equal(flashbuses_to_text(bustype), "Non-SPI, Parallel"); + + bustype = BUS_PARALLEL; + bustype |= BUS_LPC; + assert_string_equal(flashbuses_to_text(bustype), "Parallel, LPC"); + + bustype |= BUS_FWH; + //BUS_NONSPI = BUS_PARALLEL | BUS_LPC | BUS_FWH, + assert_string_equal(flashbuses_to_text(bustype), "Non-SPI"); + + bustype |= BUS_SPI; + assert_string_equal(flashbuses_to_text(bustype), "Parallel, LPC, FWH, SPI"); + + bustype |= BUS_PROG; + assert_string_equal( + flashbuses_to_text(bustype), + "Parallel, LPC, FWH, SPI, Programmer-specific" + ); + + bustype = BUS_NONE; + assert_string_equal(flashbuses_to_text(bustype), "None"); +} diff --git a/tests/meson.build b/tests/meson.build index 3ed1c3b..aad1372 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -3,6 +3,7 @@ srcs = [ 'tests.c', 'spi.c', + 'flashrom.c', 'spi25.c', ] diff --git a/tests/tests.c b/tests/tests.c index 16f4863..a3ad791 100644 --- a/tests/tests.c +++ b/tests/tests.c @@ -24,6 +24,11 @@ }; ret |= cmocka_run_group_tests_name("spi.c tests", spi_tests, NULL, NULL); + const struct CMUnitTest flashrom_tests[] = { + cmocka_unit_test(flashbuses_to_text_test_success), + }; + ret |= cmocka_run_group_tests_name("flashrom.c tests", flashrom_tests, NULL, NULL); + const struct CMUnitTest spi25_tests[] = { cmocka_unit_test(spi_write_enable_test_success), cmocka_unit_test(spi_write_disable_test_success), diff --git a/tests/tests.h b/tests/tests.h index 9377817..688c280 100644 --- a/tests/tests.h +++ b/tests/tests.h @@ -4,6 +4,9 @@ void registered_masters_test_success(void **state); void programmer_init_test_success(void **state); +/* flashrom.c */ +void flashbuses_to_text_test_success(void **state); + /* spi25.c */ void spi_write_enable_test_success(void **state); void spi_write_disable_test_success(void **state); -- To view, visit https://review.coreboot.org/c/flashrom/+/41646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2d9213f98c6c9639f2417466ba4895117e8d600a Gerrit-Change-Number: 41646 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 6

Change in flashrom[master]: flashchips: Added W25Q256.W
by Simon Buhrow (Code Review) 16 Jun '20

16 Jun '20

Simon Buhrow has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40855 ) Change subject: flashchips: Added W25Q256.W ...................................................................... flashchips: Added W25Q256.W Change-Id: I3608945a38b5ed42b8b2b9b2b388cdea97141d7b --- M flashchips.c M flashchips.h 2 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/55/40855/1 diff --git a/flashchips.c b/flashchips.c index 974ba81..f2bd68b 100644 --- a/flashchips.c +++ b/flashchips.c @@ -16626,6 +16626,47 @@ { .vendor = "Winbond", + .name = "W25Q256.W", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q256_W, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN + | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "Winbond", .name = "W25Q128.JW.DTR", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, diff --git a/flashchips.h b/flashchips.h index 0c77d1d..3332974 100644 --- a/flashchips.h +++ b/flashchips.h @@ -943,6 +943,7 @@ #define WINBOND_NEX_W25Q32_W 0x6016 /* W25Q32DW; W25Q32FV in QPI mode */ #define WINBOND_NEX_W25Q64_W 0x6017 /* W25Q64DW; W25Q64FV in QPI mode */ #define WINBOND_NEX_W25Q128_W 0x6018 /* W25Q128FW; W25Q128FV in QPI mode */ +#define WINBOND_NEX_W25Q256_W 0x6019 /* W25Q256JW */ #define WINBOND_NEX_W25Q128_V_M 0x7018 /* W25Q128JVSM */ #define WINBOND_NEX_W25Q256JV_M 0x7019 /* W25Q256JV_M (QE=0) */ #define WINBOND_NEX_W25Q64JW 0x8017 -- To view, visit https://review.coreboot.org/c/flashrom/+/40855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3608945a38b5ed42b8b2b9b2b388cdea97141d7b Gerrit-Change-Number: 40855 Gerrit-PatchSet: 1 Gerrit-Owner: Simon Buhrow Gerrit-MessageType: newchange

5 20

Change in flashrom[master]: tests/: Add spi25.c unit tests
by Edward O'Callaghan (Code Review) 16 Jun '20

16 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/41645 ) Change subject: tests/: Add spi25.c unit tests ...................................................................... tests/: Add spi25.c unit tests Change-Id: I47112952835ce2c4c773a9d90379ff8ceefaaf9a Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M tests/meson.build A tests/spi25.c M tests/tests.c M tests/tests.h 4 files changed, 196 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/45/41645/1 diff --git a/tests/meson.build b/tests/meson.build index 5af0a3e..3ed1c3b 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -3,11 +3,13 @@ srcs = [ 'tests.c', 'spi.c', + 'spi25.c', ] mocks = [ '-Wl,--wrap=physunmap', '-Wl,--wrap=physmap', + '-Wl,--wrap=spi_send_command', '-Wl,--gc-sections', ] diff --git a/tests/spi25.c b/tests/spi25.c new file mode 100644 index 0000000..cf8345c --- /dev/null +++ b/tests/spi25.c @@ -0,0 +1,170 @@ +#include <include/test.h> + +#include "programmer.h" +#include "flashchips.h" +#include "chipdrivers.h" +#include "spi.h" + +int __wrap_spi_send_command(const struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + check_expected_ptr(flash); + assert_int_equal(writecnt, mock_type(int)); + assert_int_equal(writearr[0], mock_type(int)); + + int rcnt = mock_type(int); + assert_int_equal(readcnt, rcnt); + for (int i = 0; i < rcnt; i++) + readarr[i] = i; + + return 0; +} + +struct flashchip mock_chip = { + .vendor = "Generic", + .name = "unknown SPI chip (RDID)", + .bustype = BUS_SPI, + .manufacture_id = GENERIC_MANUF_ID, + .model_id = GENERIC_DEVICE_ID, + .total_size = 0, + .page_size = 256, + .tested = TEST_BAD_PREW, + .probe = probe_spi_rdid, + .write = NULL, +}; + +void spi_write_enable_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_WREN_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_WREN); + will_return(__wrap_spi_send_command, JEDEC_WREN_INSIZE); + assert_int_equal(0, spi_write_enable(&flashctx)); +} + +void spi_write_disable_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_WRDI_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_WRDI); + will_return(__wrap_spi_send_command, JEDEC_WRDI_INSIZE); + assert_int_equal(0, spi_write_disable(&flashctx)); +} + +void probe_spi_rdid_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_RDID_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_RDID); + will_return(__wrap_spi_send_command, JEDEC_RDID_INSIZE); + assert_int_equal(0, probe_spi_rdid(&flashctx)); +} + +void probe_spi_rdid4_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_RDID_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_RDID); + will_return(__wrap_spi_send_command, JEDEC_RDID_INSIZE + 1); + assert_int_equal(0, probe_spi_rdid4(&flashctx)); +} + +void probe_spi_rems_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_REMS_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_REMS); + will_return(__wrap_spi_send_command, JEDEC_REMS_INSIZE); + assert_int_equal(0, probe_spi_rems(&flashctx)); +} + +void probe_spi_res1_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_RES_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_RES); + will_return(__wrap_spi_send_command, JEDEC_RES_INSIZE + 1); + assert_int_equal(0, probe_spi_res2(&flashctx)); +} + +void probe_spi_res2_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_RES_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_RES); + will_return(__wrap_spi_send_command, JEDEC_RES_INSIZE + 1); + assert_int_equal(0, probe_spi_res2(&flashctx)); +} + +void probe_spi_res3_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, JEDEC_RES_OUTSIZE); + will_return(__wrap_spi_send_command, JEDEC_RES); + will_return(__wrap_spi_send_command, JEDEC_RES_INSIZE + 2); + assert_int_equal(0, probe_spi_res3(&flashctx)); +} + +void probe_spi_at25f_test_success(void **state) +{ + (void) state; /* unused */ + + /* setup initial test state. */ + struct flashctx flashctx = { .chip = &mock_chip }; + expect_memory(__wrap_spi_send_command, flash, + &flashctx, sizeof(flashctx)); + + will_return(__wrap_spi_send_command, AT25F_RDID_OUTSIZE); + will_return(__wrap_spi_send_command, AT25F_RDID); + will_return(__wrap_spi_send_command, AT25F_RDID_INSIZE); + assert_int_equal(0, probe_spi_at25f(&flashctx)); +} diff --git a/tests/tests.c b/tests/tests.c index 338646e..16f4863 100644 --- a/tests/tests.c +++ b/tests/tests.c @@ -24,5 +24,18 @@ }; ret |= cmocka_run_group_tests_name("spi.c tests", spi_tests, NULL, NULL); + const struct CMUnitTest spi25_tests[] = { + cmocka_unit_test(spi_write_enable_test_success), + cmocka_unit_test(spi_write_disable_test_success), + cmocka_unit_test(probe_spi_rdid_test_success), + cmocka_unit_test(probe_spi_rdid4_test_success), + cmocka_unit_test(probe_spi_rems_test_success), + cmocka_unit_test(probe_spi_res1_test_success), + cmocka_unit_test(probe_spi_res2_test_success), + cmocka_unit_test(probe_spi_res3_test_success), + cmocka_unit_test(probe_spi_at25f_test_success), + }; + ret |= cmocka_run_group_tests_name("spi25.c tests", spi25_tests, NULL, NULL); + return ret; } diff --git a/tests/tests.h b/tests/tests.h index ccc3f5e..9377817 100644 --- a/tests/tests.h +++ b/tests/tests.h @@ -4,4 +4,15 @@ void registered_masters_test_success(void **state); void programmer_init_test_success(void **state); +/* spi25.c */ +void spi_write_enable_test_success(void **state); +void spi_write_disable_test_success(void **state); +void probe_spi_rdid_test_success(void **state); +void probe_spi_rdid4_test_success(void **state); +void probe_spi_rems_test_success(void **state); +void probe_spi_res1_test_success(void **state); +void probe_spi_res2_test_success(void **state); +void probe_spi_res3_test_success(void **state); +void probe_spi_at25f_test_success(void **state); + #endif /* TESTS_H */ -- To view, visit https://review.coreboot.org/c/flashrom/+/41645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I47112952835ce2c4c773a9d90379ff8ceefaaf9a Gerrit-Change-Number: 41645 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 6

2024

2023

2022

2021

2020

2019

2018

2017

flashrom-gerrit June 2020