Change in flashrom[master]: mysteries_intel: Add a section for software vs hardware sequencing
David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/42485 )
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
mysteries_intel: Add a section for software vs hardware sequencing
This attempts to explain software sequencing, hardware sequencing, and the "Opaque flash chip".
Change-Id: I2445e926aad96060f26d0bc55dd7642c1a404296 Signed-off-by: David Hendricks david.hendricks@gmail.com --- M Documentation/mysteries_intel.txt 1 file changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/85/42485/1
diff --git a/Documentation/mysteries_intel.txt b/Documentation/mysteries_intel.txt index 60ad21a..8ed7b65 100644 --- a/Documentation/mysteries_intel.txt +++ b/Documentation/mysteries_intel.txt @@ -5,6 +5,47 @@ A0h), so we have no clue if or where it is on ICH8. Out current policy is to not touch it at all and assume/hope it is 0.
+= Software Sequencing vs. Hardware Sequenching and the "Opaque flash chip" = +Software sequencing and hardware sequencing are two methods used to interface +with the SPI controller on Intel platforms. They can be selected using either +ich_spi_mode=swseq and ich_spi_mode=hwseq programmer parameters. Flashrom will +attempt to automatically detect which mode to use. + +Software sequencing is the traditional method whereby software running on the +CPU handles most of the logic needed to interact with the flash chip. This +offers good flexibility since the user can utilize any opcode available in the +OPMENU registers, and OPMENU can be left unlocked or on coreboot-supported +platforms the owner of the system may program it for their needs before locking +it. Advanced or non-standard features of a chip such as write protection and +OTP may be therefore be directly utilized by software. + +Hardware sequencing is a newer method whereby most of the logic for interacting +with the SPI flash chip is contained within the SPI controller itself, and +software such as flashrom may only select a few operations chosen by Intel via +the Flash Cycle (FCYCLE) field. The chip must conform to specifications from +Intel for each chipset/PCH. There specs are given in the "SPI Programming Guide" +for each chipset/PCH and are usually available under NDA. + +Hardware sequencing simplifies things from a software perspective since the +software is guaranteed some minimal level of support and doesn't even need to +know the chip's ID and know its supported opcodes; it just needs to tell the +SPI controller to perform a certain type of transaction such as "read", "4k +block erase", etc. without knowing the actual opcodes used by the chip for the +transaction. Hence when using hardware sequencing one will see "Opaque flash +chip" as the chip's description, since flashrom will not necessarily even read +the chip's ID. This abstraction also allows the SPI controller to do things like +concatenating multiple chips to appear as a single large one. + +In many non-Intel systems the software has full control of a generic SPI +controller where the software controls the chip select and data buffer and also +constructs the payload including pre-op (e.g. write enable latch), opcode, +address, and data. Intel SPI flash controllers are purpose-built for flash chip +access and the software does not control the hardware directly. This makes Intel +SPI controllers less flexible from a software standpoint, however there are some +benefits such as guaranteed atomicity and multi-master arbitration needed for +modern Intel platforms where the CPU and various microprocessors can share the +same flash chip. + = SMM BIOS Write Protection = Sometimes a hardware vendor will enable "SMM BIOS Write Protect" (SMM_BWP) in the firmware during boot time. The bits that control SMM_BWP are in the
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/42485
to look at the new patch set (#2).
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
mysteries_intel: Add a section for software vs hardware sequencing
This attempts to explain software sequencing, hardware sequencing, and the "Opaque flash chip".
Change-Id: I2445e926aad96060f26d0bc55dd7642c1a404296 Signed-off-by: David Hendricks david.hendricks@gmail.com --- M Documentation/mysteries_intel.txt 1 file changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/85/42485/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/42485 )
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
Patch Set 2: Code-Review+1
(4 comments)
https://review.coreboot.org/c/flashrom/+/42485/2/Documentation/mysteries_int... File Documentation/mysteries_intel.txt:
https://review.coreboot.org/c/flashrom/+/42485/2/Documentation/mysteries_int... PS2, Line 20: be therefore be duplicated `be`
https://review.coreboot.org/c/flashrom/+/42485/2/Documentation/mysteries_int... PS2, Line 26: SPI Programming Guide Reference [SPI_PROG] as an example?
https://review.coreboot.org/c/flashrom/+/42485/2/Documentation/mysteries_int... PS2, Line 31: and know nor
https://review.coreboot.org/c/flashrom/+/42485/2/Documentation/mysteries_int... PS2, Line 35: will not necessarily even read : the chip's ID note that sometimes we can't do that at all, because there are multiple chips or because some important opcode for swseq is missing and opmenu is locked
Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/42485
to look at the new patch set (#3).
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
mysteries_intel: Add a section for software vs hardware sequencing
This attempts to explain software sequencing, hardware sequencing, and the "Opaque flash chip".
Change-Id: I2445e926aad96060f26d0bc55dd7642c1a404296 Signed-off-by: David Hendricks david.hendricks@gmail.com --- M Documentation/mysteries_intel.txt 1 file changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/85/42485/3
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/42485 )
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/flashrom/+/42485/2/Documentation/mysteries_int... File Documentation/mysteries_intel.txt:
https://review.coreboot.org/c/flashrom/+/42485/2/Documentation/mysteries_int... PS2, Line 20: be therefore be
duplicated `be`
Done
https://review.coreboot.org/c/flashrom/+/42485/2/Documentation/mysteries_int... PS2, Line 26: SPI Programming Guide
Reference [SPI_PROG] as an example?
I'm not sure what you mean by [SPI_PROG]... I also may have used confusing terminology. Here I am specifically referring to application notes from Intel that they title "SPI Programming Guide" for each PCH. These are usually referenced from the PCH datasheet, for example in https://www.intel.com/content/www/us/en/products/docs/chipsets/300-series-ch....
I'll try to clarify that.
https://review.coreboot.org/c/flashrom/+/42485/2/Documentation/mysteries_int... PS2, Line 31: and know
nor
Done
https://review.coreboot.org/c/flashrom/+/42485/2/Documentation/mysteries_int... PS2, Line 35: will not necessarily even read : the chip's ID
note that sometimes we can't do that at all, because there are multiple chips or because some import […]
I prefer to avoid mentioning software sequencing in this paragraph since it might be confusing, however I used your example of multiple chips to clarify that we might not even be able to read the chip ID.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/42485 )
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
Patch Set 3: Code-Review+1
(2 comments)
https://review.coreboot.org/c/flashrom/+/42485/2/Documentation/mysteries_int... File Documentation/mysteries_intel.txt:
https://review.coreboot.org/c/flashrom/+/42485/2/Documentation/mysteries_int... PS2, Line 26: SPI Programming Guide
I'm not sure what you mean by [SPI_PROG]... I also may have used confusing terminology. […]
It's at the end of this file:
[SPI_PROG] Ibex Peak SPI Programming Guide Document Number: 403598, Revision 1.3, page 79
https://review.coreboot.org/c/flashrom/+/42485/3/Documentation/mysteries_int... File Documentation/mysteries_intel.txt:
https://review.coreboot.org/c/flashrom/+/42485/3/Documentation/mysteries_int... PS3, Line 27: usually referenced from the : chipset/PCH datasheet Uh, not really. AFAIK they come with the ME/TXE kits.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/42485 )
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/flashrom/+/42485/2/Documentation/mysteries_int... File Documentation/mysteries_intel.txt:
https://review.coreboot.org/c/flashrom/+/42485/2/Documentation/mysteries_int... PS2, Line 35: will not necessarily even read : the chip's ID
I prefer to avoid mentioning software sequencing in this paragraph since it might be confusing, howe […]
Good enough
Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/42485
to look at the new patch set (#4).
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
mysteries_intel: Add a section for software vs hardware sequencing
This attempts to explain software sequencing, hardware sequencing, and the "Opaque flash chip".
Change-Id: I2445e926aad96060f26d0bc55dd7642c1a404296 Signed-off-by: David Hendricks david.hendricks@gmail.com --- M Documentation/mysteries_intel.txt 1 file changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/85/42485/4
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/42485 )
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/flashrom/+/42485/2/Documentation/mysteries_int... File Documentation/mysteries_intel.txt:
https://review.coreboot.org/c/flashrom/+/42485/2/Documentation/mysteries_int... PS2, Line 26: SPI Programming Guide
It's at the end of this file: […]
Thanks!
https://review.coreboot.org/c/flashrom/+/42485/3/Documentation/mysteries_int... File Documentation/mysteries_intel.txt:
https://review.coreboot.org/c/flashrom/+/42485/3/Documentation/mysteries_int... PS3, Line 27: usually referenced from the : chipset/PCH datasheet
Uh, not really. AFAIK they come with the ME/TXE kits.
I don't think that's true, at least not in my experience searching for SPI programming guides on developer.intel.com.
In any case I think your suggestion of using [SPI_PROG] as an example makes the point.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/42485 )
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
Patch Set 4: Code-Review+2
(1 comment)
https://review.coreboot.org/c/flashrom/+/42485/3/Documentation/mysteries_int... File Documentation/mysteries_intel.txt:
https://review.coreboot.org/c/flashrom/+/42485/3/Documentation/mysteries_int... PS3, Line 27: usually referenced from the : chipset/PCH datasheet
I don't think that's true, at least not in my experience searching for SPI programming guides on dev […]
Ack
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/42485 )
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
Patch Set 4: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/42485 )
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
Patch Set 4:
(1 comment)
Thank you for taking the time writing this.
https://review.coreboot.org/c/flashrom/+/42485/4/Documentation/mysteries_int... File Documentation/mysteries_intel.txt:
https://review.coreboot.org/c/flashrom/+/42485/4/Documentation/mysteries_int... PS4, Line 26: There The?
Hello build bot (Jenkins), Angel Pons, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/42485
to look at the new patch set (#5).
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
mysteries_intel: Add a section for software vs hardware sequencing
This attempts to explain software sequencing, hardware sequencing, and the "Opaque flash chip".
Change-Id: I2445e926aad96060f26d0bc55dd7642c1a404296 Signed-off-by: David Hendricks david.hendricks@gmail.com --- M Documentation/mysteries_intel.txt 1 file changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/85/42485/5
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/42485 )
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/flashrom/+/42485/4/Documentation/mysteries_int... File Documentation/mysteries_intel.txt:
https://review.coreboot.org/c/flashrom/+/42485/4/Documentation/mysteries_int... PS4, Line 10: either removed "either"
https://review.coreboot.org/c/flashrom/+/42485/4/Documentation/mysteries_int... PS4, Line 26: There
The?
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/42485 )
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
Patch Set 5: Code-Review+1
(1 comment)
Uhm, Jenkins farted it seems. Anyway, here's a suggested change if you want to try retriggering it.
https://review.coreboot.org/c/flashrom/+/42485/4/Documentation/mysteries_int... File Documentation/mysteries_intel.txt:
https://review.coreboot.org/c/flashrom/+/42485/4/Documentation/mysteries_int... PS4, Line 10: either
removed "either"
I would have used "either ... or ..." in this case
Hello build bot (Jenkins), Angel Pons, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/42485
to look at the new patch set (#6).
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
mysteries_intel: Add a section for software vs hardware sequencing
This attempts to explain software sequencing, hardware sequencing, and the "Opaque flash chip".
Change-Id: I2445e926aad96060f26d0bc55dd7642c1a404296 Signed-off-by: David Hendricks david.hendricks@gmail.com --- M Documentation/mysteries_intel.txt 1 file changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/85/42485/6
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/42485 )
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
Patch Set 6:
(1 comment)
Yay, Jenkins succeeded this time! LMK if there's anything else, or we can just merge it as is.
https://review.coreboot.org/c/flashrom/+/42485/4/Documentation/mysteries_int... File Documentation/mysteries_intel.txt:
https://review.coreboot.org/c/flashrom/+/42485/4/Documentation/mysteries_int... PS4, Line 10: either
I would have used "either ... or ... […]
Done.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/42485 )
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
Patch Set 6: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/42485 )
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
Patch Set 6:
Patch Set 6:
(1 comment)
Yay, Jenkins succeeded this time! LMK if there's anything else, or we can just merge it as is.
LGTM, I'll submit it.
Angel Pons has submitted this change. ( https://review.coreboot.org/c/flashrom/+/42485 )
Change subject: mysteries_intel: Add a section for software vs hardware sequencing ......................................................................
mysteries_intel: Add a section for software vs hardware sequencing
This attempts to explain software sequencing, hardware sequencing, and the "Opaque flash chip".
Change-Id: I2445e926aad96060f26d0bc55dd7642c1a404296 Signed-off-by: David Hendricks david.hendricks@gmail.com Reviewed-on: https://review.coreboot.org/c/flashrom/+/42485 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M Documentation/mysteries_intel.txt 1 file changed, 42 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/Documentation/mysteries_intel.txt b/Documentation/mysteries_intel.txt index 60ad21a..088abb8 100644 --- a/Documentation/mysteries_intel.txt +++ b/Documentation/mysteries_intel.txt @@ -5,6 +5,48 @@ A0h), so we have no clue if or where it is on ICH8. Out current policy is to not touch it at all and assume/hope it is 0.
+= Software Sequencing vs. Hardware Sequencing and the "Opaque flash chip" = +Software sequencing and hardware sequencing are two methods used to interface +with the SPI controller on Intel platforms. They can be selected using either +ich_spi_mode=swseq or ich_spi_mode=hwseq programmer parameters. Flashrom will +attempt to automatically detect which mode to use. + +Software sequencing is the traditional method whereby software running on the +CPU handles most of the logic needed to interact with the flash chip. This +offers good flexibility since the user can utilize any opcode available in the +OPMENU registers, and OPMENU can be left unlocked or on coreboot-supported +platforms the owner of the system may program it for their needs before locking +it. Advanced or non-standard features of a chip such as write protection and +OTP may therefore be directly utilized by software. + +Hardware sequencing is a newer method (since around 2011) whereby most of the +logic for interacting with the SPI flash chip is contained within the SPI +controller itself and software such as flashrom may only select a few operations +chosen by Intel via the Flash Cycle (FCYCLE) field. The chip must conform to +specifications from Intel for each chipset/PCH. The specs are given in the +"SPI Programming Guide" application note. See [SPI_PROG] cited at the bottom of +this document for an example. + +Hardware sequencing simplifies things from a software perspective since the +software is guaranteed some minimal level of support and doesn't even need to +know the chip's ID or opcodes; it just needs to tell the SPI controller to +perform a type of transaction such as "read", "4k block erase", etc. Hence when +using hardware sequencing one will see "Opaque flash chip" as the chip's +description since software might not be able to identify the chip. The SPI +controller can combine multiple physical flash chips to logically appear as a +single large flash device, and in such cases it would not make sense for +flashrom to try to identify the chip. + +In many non-Intel systems the software has full control of a generic SPI +controller where the software controls the SPI signals and also constructs the +data payload including pre-op (e.g. write enable latch), opcode, address, and +data. Intel SPI flash controllers are purpose-built for flash chip access and +the software does not control the hardware directly. This makes Intel SPI +controllers less flexible from a software standpoint, however there are some +benefits such as guaranteed atomicity and multi-master arbitration needed for +modern Intel platforms where the CPU and various microprocessors can share the +same flash chip. + = SMM BIOS Write Protection = Sometimes a hardware vendor will enable "SMM BIOS Write Protect" (SMM_BWP) in the firmware during boot time. The bits that control SMM_BWP are in the
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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David Hendricks (Code Review)
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Paul Menzel (Code Review)