November 2020 - flashrom-gerrit

Change in flashrom[master]: sst49lfxxxc.c: add unlock function for SST chips
by Nikolai Artemiev (Code Review) 27 Nov '20

27 Nov '20

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48108 ) Change subject: sst49lfxxxc.c: add unlock function for SST chips ...................................................................... sst49lfxxxc.c: add unlock function for SST chips Function imported from cros flashrom at `1f38d1ab13d72912fc2d90c7e964dd15e9ec2c9b` Change-Id: I019bbb622b2348a05e7d03fbd0aa3bfac5f81175 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M chipdrivers.h M sst49lfxxxc.c 2 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/48108/1 diff --git a/chipdrivers.h b/chipdrivers.h index cf03811..82ac3a2 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -165,6 +165,7 @@ /* sst49lfxxxc.c */ int erase_sector_49lfxxxc(struct flashctx *flash, unsigned int address, unsigned int sector_size); +int unlock_49lfxxxc(struct flashctx *flash); /* sst_fwhub.c */ int printlock_sst_fwhub(struct flashctx *flash); diff --git a/sst49lfxxxc.c b/sst49lfxxxc.c index a69ab75..9bb4d5d 100644 --- a/sst49lfxxxc.c +++ b/sst49lfxxxc.c @@ -18,6 +18,43 @@ #include "flash.h" #include "chipdrivers.h" +#include <inttypes.h> + +static int write_lockbits_block_49lfxxxc(struct flashctx *flash, unsigned long address, unsigned char bits) +{ + unsigned long lock = flash->virtual_registers + address + 2; + msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", lock, chip_readb(flash, lock)); + chip_writeb(flash, bits, lock); + + return 0; +} + +static int write_lockbits_49lfxxxc(struct flashctx *flash, unsigned char bits) +{ + chipaddr registers = flash->virtual_registers; + unsigned int i, left = flash->chip->total_size * 1024; + unsigned long address; + + msg_cdbg("\nbios=0x%08" PRIxPTR "\n", registers); + for (i = 0; left > 65536; i++, left -= 65536) { + write_lockbits_block_49lfxxxc(flash, i * 65536, bits); + } + address = i * 65536; + write_lockbits_block_49lfxxxc(flash, address, bits); + address += 32768; + write_lockbits_block_49lfxxxc(flash, address, bits); + address += 8192; + write_lockbits_block_49lfxxxc(flash, address, bits); + address += 8192; + write_lockbits_block_49lfxxxc(flash, address, bits); + + return 0; +} + +int unlock_49lfxxxc(struct flashctx *flash) +{ + return write_lockbits_49lfxxxc(flash, 0); +} int erase_sector_49lfxxxc(struct flashctx *flash, unsigned int address, unsigned int sector_size) -- To view, visit https://review.coreboot.org/c/flashrom/+/48108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I019bbb622b2348a05e7d03fbd0aa3bfac5f81175 Gerrit-Change-Number: 48108 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: lspcon_i2c_spi.c: Fix style
by Shiyu Sun (Code Review) 26 Nov '20

26 Nov '20

Shiyu Sun has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47874 ) Change subject: lspcon_i2c_spi.c: Fix style ...................................................................... lspcon_i2c_spi.c: Fix style Avoid define the variable i at the for loop statement. BUG=None TEST=None Signed-off-by: Shiyu Sun <sshiyu(a)chromium.org> Change-Id: I4068ae7bdf6e053606cb063f7781dbb2d77792ff --- M lspcon_i2c_spi.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/74/47874/1 diff --git a/lspcon_i2c_spi.c b/lspcon_i2c_spi.c index 7b9f1c0..f468031 100644 --- a/lspcon_i2c_spi.c +++ b/lspcon_i2c_spi.c @@ -377,6 +377,7 @@ unsigned int start, unsigned int len) { int ret = 0; + unsigned int i; if (start & 0xff) return default_spi_write_256(flash, buf, start, len); @@ -389,7 +390,7 @@ ret |= lspcon_i2c_spi_enable_hw_write(fd); ret |= lspcon_i2c_clt2_spi_reset(fd); - for (unsigned int i = 0; i < len; i += PAGE_SIZE) { + for (i = 0; i < len; i += PAGE_SIZE) { ret |= lspcon_i2c_spi_map_page(fd, start + i); ret |= lspcon_i2c_spi_write_page(fd, buf + i, min(len - i, PAGE_SIZE)); } -- To view, visit https://review.coreboot.org/c/flashrom/+/47874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4068ae7bdf6e053606cb063f7781dbb2d77792ff Gerrit-Change-Number: 47874 Gerrit-PatchSet: 1 Gerrit-Owner: Shiyu Sun <sshiyu(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: layout: Add -i <region>[:<file>] support
by Edward O'Callaghan (Code Review) 26 Nov '20

26 Nov '20

Edward O'Callaghan has uploaded a new patch set (#16) to the change originally created by David Hendricks. ( https://review.coreboot.org/c/flashrom/+/23021 ) Change subject: layout: Add -i <region>[:<file>] support ...................................................................... layout: Add -i <region>[:<file>] support Add an optional sub-parameter to the -i parameter to allow building the image to be written from multiple files. This will also allow regions to be read from flash and written to separate image files. This is a rebase of a patch that was ported from chromiumos. A lot of things have changed, but the idea is the same. Original patch by Louis Yung-Chieh Lo <yjlou(a)chromium.org>: Summary: Support -i partition:file feature for both read and write. Commit: 9c7525f Review URL: http://codereview.chromium.org/6611015 Ported version by Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> and Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>: Summary: [PATCH 2/6] layout: Add -i <region>[:<file>] support. Review URL: https://mail.coreboot.org/pipermail/flashrom/2013-October/011729.html Change-Id: Ic5465659605d8431d931053967b40290195cfd99 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Co-Authored-by: Edward O'Callaghan <quasisec(a)google.com> --- M cli_classic.c M dummyflasher.c M flash.h M flashrom.8.tmpl M flashrom.c M layout.c M layout.h 7 files changed, 233 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/23021/16 -- To view, visit https://review.coreboot.org/c/flashrom/+/23021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic5465659605d8431d931053967b40290195cfd99 Gerrit-Change-Number: 23021 Gerrit-PatchSet: 16 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: sb600spi.c: Don't access spibar directly
by Edward O'Callaghan (Code Review) 26 Nov '20

26 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36433 ) Change subject: sb600spi.c: Don't access spibar directly ...................................................................... sb600spi.c: Don't access spibar directly Constrain the manner in which the global state of spibar is set and then subsequently accessed. This makes it easier to write unit-tests and instrument the code. Change-Id: Ic26372b9c1baebb20716eea1db1e942239ed3e48 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M sb600spi.c 1 file changed, 53 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/33/36433/1 diff --git a/sb600spi.c b/sb600spi.c index 23b36ee..7bdd11f 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -40,7 +40,13 @@ *}; */ -static uint8_t *sb600_spibar = NULL; +static uint8_t *g_sb600_spibar = NULL; + +static inline uint8_t * get_spibar(void) +{ + return g_sb600_spibar; +} + enum amd_chipset { CHIPSET_AMD_UNKNOWN, CHIPSET_SB6XX, @@ -180,16 +186,18 @@ static void reset_internal_fifo_pointer(void) { - mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2); + uint8_t *spibar = get_spibar(); + mmio_writeb(mmio_readb(spibar + 2) | 0x10, spibar + 2); /* FIXME: This loop needs a timeout and a clearer message. */ - while (mmio_readb(sb600_spibar + 0xD) & 0x7) + while (mmio_readb(spibar + 0xD) & 0x7) msg_pspew("reset\n"); } static int compare_internal_fifo_pointer(uint8_t want) { - uint8_t have = mmio_readb(sb600_spibar + 0xd) & 0x07; + uint8_t *spibar = get_spibar(); + uint8_t have = mmio_readb(spibar + 0xd) & 0x07; want %= FIFO_SIZE_OLD; if (have != want) { msg_perr("AMD SPI FIFO pointer corruption! Pointer is %d, wanted %d\n", have, want); @@ -224,8 +232,9 @@ static void execute_command(void) { msg_pspew("Executing... "); - mmio_writeb(mmio_readb(sb600_spibar + 2) | 1, sb600_spibar + 2); - while (mmio_readb(sb600_spibar + 2) & 1) + uint8_t *spibar = get_spibar(); + mmio_writeb(mmio_readb(spibar + 2) | 1, spibar + 2); + while (mmio_readb(spibar + 2) & 1) ; msg_pspew("done\n"); } @@ -239,7 +248,8 @@ unsigned char cmd = *writearr++; writecnt--; msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, cmd, writecnt, readcnt); - mmio_writeb(cmd, sb600_spibar + 0); + uint8_t *spibar = get_spibar(); + mmio_writeb(cmd, spibar + 0); int ret = check_readwritecnt(flash, writecnt, readcnt); if (ret != 0) @@ -253,14 +263,14 @@ */ unsigned int readoffby1 = (writecnt > 0) ? 0 : 1; uint8_t readwrite = (readcnt + readoffby1) << 4 | (writecnt); - mmio_writeb(readwrite, sb600_spibar + 1); + mmio_writeb(readwrite, spibar + 1); reset_internal_fifo_pointer(); msg_pspew("Filling FIFO: "); unsigned int count; for (count = 0; count < writecnt; count++) { msg_pspew("[%02x]", writearr[count]); - mmio_writeb(writearr[count], sb600_spibar + 0xC); + mmio_writeb(writearr[count], spibar + 0xC); } msg_pspew("\n"); if (compare_internal_fifo_pointer(writecnt)) @@ -291,7 +301,7 @@ /* Skip the bytes we sent. */ msg_pspew("Skipping: "); for (count = 0; count < writecnt; count++) { - msg_pspew("[%02x]", mmio_readb(sb600_spibar + 0xC)); + msg_pspew("[%02x]", mmio_readb(spibar + 0xC)); } msg_pspew("\n"); if (compare_internal_fifo_pointer(writecnt)) @@ -299,14 +309,14 @@ msg_pspew("Reading FIFO: "); for (count = 0; count < readcnt; count++) { - readarr[count] = mmio_readb(sb600_spibar + 0xC); + readarr[count] = mmio_readb(spibar + 0xC); msg_pspew("[%02x]", readarr[count]); } msg_pspew("\n"); if (compare_internal_fifo_pointer(writecnt+readcnt)) return SPI_PROGRAMMER_ERROR; - if (mmio_readb(sb600_spibar + 1) != readwrite) { + if (mmio_readb(spibar + 1) != readwrite) { msg_perr("Unexpected change in AMD SPI read/write count!\n"); msg_perr("Something else is accessing the flash chip and causes random corruption.\n" "Please stop all applications and drivers and IPMI which access the flash chip.\n"); @@ -325,21 +335,22 @@ unsigned char cmd = *writearr++; writecnt--; msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, cmd, writecnt, readcnt); - mmio_writeb(cmd, sb600_spibar + 0); + uint8_t *spibar = get_spibar(); + mmio_writeb(cmd, spibar + 0); int ret = check_readwritecnt(flash, writecnt, readcnt); if (ret != 0) return ret; /* Use the extended TxByteCount and RxByteCount registers. */ - mmio_writeb(writecnt, sb600_spibar + 0x48); - mmio_writeb(readcnt, sb600_spibar + 0x4b); + mmio_writeb(writecnt, spibar + 0x48); + mmio_writeb(readcnt, spibar + 0x4b); msg_pspew("Filling buffer: "); unsigned int count; for (count = 0; count < writecnt; count++) { msg_pspew("[%02x]", writearr[count]); - mmio_writeb(writearr[count], sb600_spibar + 0x80 + count); + mmio_writeb(writearr[count], spibar + 0x80 + count); } msg_pspew("\n"); @@ -347,7 +358,7 @@ msg_pspew("Reading buffer: "); for (count = 0; count < readcnt; count++) { - readarr[count] = mmio_readb(sb600_spibar + 0x80 + (writecnt + count) % FIFO_SIZE_YANGTZE); + readarr[count] = mmio_readb(spibar + 0x80 + (writecnt + count) % FIFO_SIZE_YANGTZE); msg_pspew("[%02x]", readarr[count]); } msg_pspew("\n"); @@ -375,16 +386,17 @@ { bool success = false; uint8_t speed = spispeed->speed; + uint8_t *spibar = get_spibar(); msg_pdbg("Setting SPI clock to %s (0x%x).\n", spispeed->name, speed); if (amd_gen >= CHIPSET_YANGTZE) { - rmmio_writew((speed << 12) | (speed << 8) | (speed << 4) | speed, sb600_spibar + 0x22); - uint16_t tmp = mmio_readw(sb600_spibar + 0x22); + rmmio_writew((speed << 12) | (speed << 8) | (speed << 4) | speed, spibar + 0x22); + uint16_t tmp = mmio_readw(spibar + 0x22); success = (((tmp >> 12) & 0xf) == speed && ((tmp >> 8) & 0xf) == speed && ((tmp >> 4) & 0xf) == speed && ((tmp >> 0) & 0xf) == speed); } else { - rmmio_writeb((mmio_readb(sb600_spibar + 0xd) & ~(0x3 << 4)) | (speed << 4), sb600_spibar + 0xd); - success = (speed == ((mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3)); + rmmio_writeb((mmio_readb(spibar + 0xd) & ~(0x3 << 4)) | (speed << 4), spibar + 0xd); + success = (speed == ((mmio_readb(spibar + 0xd) >> 4) & 0x3)); } if (!success) { @@ -396,11 +408,12 @@ static int set_mode(struct pci_dev *dev, uint8_t read_mode) { - uint32_t tmp = mmio_readl(sb600_spibar + 0x00); + uint8_t *spibar = get_spibar(); + uint32_t tmp = mmio_readl(spibar + 0x00); tmp &= ~(0x6 << 28 | 0x1 << 18); /* Clear mode bits */ tmp |= ((read_mode & 0x6) << 28) | ((read_mode & 0x1) << 18); - rmmio_writel(tmp, sb600_spibar + 0x00); - if (tmp != mmio_readl(sb600_spibar + 0x00)) + rmmio_writel(tmp, spibar + 0x00); + if (tmp != mmio_readl(spibar + 0x00)) return 1; return 0; } @@ -409,6 +422,7 @@ { uint32_t tmp; uint8_t spispeed_idx = 3; /* Default to 16.5 MHz */ + uint8_t *spibar = get_spibar(); char *spispeed = extract_programmer_param("spispeed"); if (spispeed != NULL) { @@ -450,7 +464,7 @@ "Normal (up to 66 MHz)", /* 6 */ "Fast Read", /* 7 (Not defined in the Bolton datasheet.) */ }; - tmp = mmio_readl(sb600_spibar + 0x00); + tmp = mmio_readl(spibar + 0x00); uint8_t read_mode = ((tmp >> 28) & 0x6) | ((tmp >> 18) & 0x1); msg_pdbg("SpiReadMode=%s (%i)\n", spireadmodes[read_mode], read_mode); if (read_mode != 6) { @@ -463,11 +477,11 @@ } if (amd_gen >= CHIPSET_YANGTZE) { - tmp = mmio_readb(sb600_spibar + 0x20); + tmp = mmio_readb(spibar + 0x20); msg_pdbg("UseSpi100 is %sabled\n", (tmp & 0x1) ? "en" : "dis"); if ((tmp & 0x1) == 0) { - rmmio_writeb(tmp | 0x1, sb600_spibar + 0x20); - tmp = mmio_readb(sb600_spibar + 0x20) & 0x1; + rmmio_writeb(tmp | 0x1, spibar + 0x20); + tmp = mmio_readb(spibar + 0x20) & 0x1; if (tmp == 0) { msg_perr("Enabling Spi100 failed.\n"); return 1; @@ -475,7 +489,7 @@ msg_pdbg("Enabling Spi100 succeeded.\n"); } - tmp = mmio_readw(sb600_spibar + 0x22); /* SPI 100 Speed Config */ + tmp = mmio_readw(spibar + 0x22); /* SPI 100 Speed Config */ msg_pdbg("NormSpeedNew is %s\n", spispeeds[(tmp >> 12) & 0xf].name); msg_pdbg("FastSpeedNew is %s\n", spispeeds[(tmp >> 8) & 0xf].name); msg_pdbg("AltSpeedNew is %s\n", spispeeds[(tmp >> 4) & 0xf].name); @@ -483,15 +497,15 @@ } } else { if (amd_gen >= CHIPSET_SB89XX && amd_gen <= CHIPSET_HUDSON234) { - bool fast_read = (mmio_readl(sb600_spibar + 0x00) >> 18) & 0x1; + bool fast_read = (mmio_readl(spibar + 0x00) >> 18) & 0x1; msg_pdbg("Fast Reads are %sabled\n", fast_read ? "en" : "dis"); if (fast_read) { msg_pdbg("Disabling them temporarily.\n"); - rmmio_writel(mmio_readl(sb600_spibar + 0x00) & ~(0x1 << 18), - sb600_spibar + 0x00); + rmmio_writel(mmio_readl(spibar + 0x00) & ~(0x1 << 18), + spibar + 0x00); } } - tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; + tmp = (mmio_readb(spibar + 0xd) >> 4) & 0x3; msg_pdbg("NormSpeed is %s\n", spispeeds[tmp].name); } return set_speed(dev, amd_gen, &spispeeds[spispeed_idx]); @@ -581,14 +595,14 @@ return 0; /* Physical memory has to be mapped at page (4k) boundaries. */ - sb600_spibar = rphysmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); - if (sb600_spibar == ERROR_PTR) + g_sb600_spibar = rphysmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); + if (g_sb600_spibar == ERROR_PTR) return ERROR_FATAL; /* The low bits of the SPI base address are used as offset into * the mapped page. */ - sb600_spibar += tmp & 0xfff; + g_sb600_spibar += tmp & 0xfff; int amd_gen = determine_generation(dev); if (amd_gen < 0) @@ -649,7 +663,8 @@ * * <1> see handle_speed */ - tmp = mmio_readl(sb600_spibar + 0x00); + uint8_t *spibar = get_spibar(); + tmp = mmio_readl(spibar + 0x00); msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%i", tmp, (tmp >> 19) & 0x1); if (amd_gen >= CHIPSET_YANGTZE) msg_pdbg(", IllegalAccess=%i", (tmp >> 21) & 0x1); @@ -679,7 +694,7 @@ } if (amd_gen >= CHIPSET_SB89XX) { - tmp = mmio_readb(sb600_spibar + 0x1D); + tmp = mmio_readb(spibar + 0x1D); msg_pdbg("Using SPI_CS%d\n", tmp & 0x3); /* FIXME: Handle SpiProtect* configuration on Yangtze. */ } -- To view, visit https://review.coreboot.org/c/flashrom/+/36433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic26372b9c1baebb20716eea1db1e942239ed3e48 Gerrit-Change-Number: 36433 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: sb600spi.c: Remove 'amd_gen' out of global state.
by Edward O'Callaghan (Code Review) 25 Nov '20

25 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36432 ) Change subject: sb600spi.c: Remove 'amd_gen' out of global state. ...................................................................... sb600spi.c: Remove 'amd_gen' out of global state. Have 'determine_generation()' explicitly return 'amd_gen' and then pass the state into what requires it. Thus making the code more pure, easier to read and more unit-testable. Change-Id: I99fbad9486123c6b921eab83756de54a53ddfa7a Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M sb600spi.c 1 file changed, 12 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/32/36432/1 diff --git a/sb600spi.c b/sb600spi.c index 8daaf03..23b36ee 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -51,7 +51,6 @@ CHIPSET_YANGTZE, CHIPSET_PROMONTORY, }; -static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; #define FIFO_SIZE_OLD 8 #define FIFO_SIZE_YANGTZE 71 @@ -110,7 +109,7 @@ /* Determine the chipset's version and identify the respective SMBUS device. */ static int determine_generation(struct pci_dev *dev) { - amd_gen = CHIPSET_AMD_UNKNOWN; + enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; msg_pdbg2("Trying to determine the generation of the SPI interface... "); if (dev->device_id == 0x438d) { amd_gen = CHIPSET_SB6XX; @@ -173,11 +172,10 @@ "Please report this to flashrom(a)flashrom.org and include this log and\n" "the output of lspci -nnvx, thanks!\n", __func__, dev->vendor_id, dev->device_id); - if (amd_gen == CHIPSET_AMD_UNKNOWN) { + if (amd_gen == CHIPSET_AMD_UNKNOWN) msg_perr("Could not determine chipset generation."); - return -1; - } - return 0; + + return amd_gen; } static void reset_internal_fifo_pointer(void) @@ -373,7 +371,7 @@ { "800 kHz", 0x07 }, }; -static int set_speed(struct pci_dev *dev, const struct spispeed *spispeed) +static int set_speed(struct pci_dev *dev, enum amd_chipset amd_gen, const struct spispeed *spispeed) { bool success = false; uint8_t speed = spispeed->speed; @@ -407,7 +405,7 @@ return 0; } -static int handle_speed(struct pci_dev *dev) +static int handle_speed(struct pci_dev *dev, enum amd_chipset amd_gen) { uint32_t tmp; uint8_t spispeed_idx = 3; /* Default to 16.5 MHz */ @@ -496,10 +494,10 @@ tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; msg_pdbg("NormSpeed is %s\n", spispeeds[tmp].name); } - return set_speed(dev, &spispeeds[spispeed_idx]); + return set_speed(dev, amd_gen, &spispeeds[spispeed_idx]); } -static int handle_imc(struct pci_dev *dev) +static int handle_imc(struct pci_dev *dev, enum amd_chipset amd_gen) { /* Handle IMC everywhere but sb600 which does not have one. */ if (amd_gen == CHIPSET_SB6XX) @@ -592,7 +590,8 @@ */ sb600_spibar += tmp & 0xfff; - if (determine_generation(dev) < 0) + int amd_gen = determine_generation(dev); + if (amd_gen < 0) return ERROR_NONFATAL; /* How to read the following table and similar ones in this file: @@ -725,10 +724,10 @@ return 0; } - if (handle_speed(dev) != 0) + if (handle_speed(dev, amd_gen) != 0) return ERROR_FATAL; - if (handle_imc(dev) != 0) + if (handle_imc(dev, amd_gen) != 0) return ERROR_FATAL; /* Starting with Yangtze the SPI controller got a different interface with a much bigger buffer. */ -- To view, visit https://review.coreboot.org/c/flashrom/+/36432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I99fbad9486123c6b921eab83756de54a53ddfa7a Gerrit-Change-Number: 36432 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

5 15

Change in flashrom[master]: dummyflasher.c: Allow filling with either 0x00 or 0xff
by Edward O'Callaghan (Code Review) 25 Nov '20

25 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47859 ) Change subject: dummyflasher.c: Allow filling with either 0x00 or 0xff ...................................................................... dummyflasher.c: Allow filling with either 0x00 or 0xff This upstreams a ChromiumOS feature that allows the user of the dummyflasher spi master to either fill with 0x00 or 0xff in the fake flash content by way of a spi master param. BUG=b:140394053 BRANCH=none TEST=none Change-Id: I37c6dee932e449201d8bbfb03ca6d139da3cb6a2 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M dummyflasher.c 1 file changed, 22 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/59/47859/1 diff --git a/dummyflasher.c b/dummyflasher.c index 82aa3c8..d9c4085 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -52,6 +52,7 @@ enum emu_chip emu_chip; char *emu_persistent_image; unsigned int emu_chip_size; + int erase_to_zero; int emu_modified; /* is the image modified since reading it? */ uint8_t emu_status; /* If "freq" parameter is passed in from command line, commands will delay @@ -454,6 +455,21 @@ free(tmp); return 1; } + + /* Should emulated flash erase to zero (yes/no)? */ + tmp = extract_programmer_param("erase_to_zero"); + if (tmp) { + if (!strcmp(tmp, "yes")) { + msg_pdbg("Emulated chip will erase to 0x00\n"); + data->erase_to_zero = 1; + } else if (!strcmp(tmp, "no")) { + msg_pdbg("Emulated chip will erase to 0xff\n"); + } else { + msg_perr("erase_to_zero can be \"yes\" or \"no\"\n"); + return 1; + } + } + free(tmp); flashchip_contents = malloc(data->emu_chip_size); if (!flashchip_contents) { @@ -478,8 +494,9 @@ } #endif - msg_pdbg("Filling fake flash chip with 0xff, size %i\n", data->emu_chip_size); - memset(flashchip_contents, 0xff, data->emu_chip_size); + msg_pdbg("Filling fake flash chip with 0x%02x, size %i\n", + data->erase_to_zero ? 0x00 : 0xff, data->emu_chip_size); + memset(flashchip_contents, data->erase_to_zero ? 0x00 : 0xff, data->emu_chip_size); /* Will be freed by shutdown function if necessary. */ data->emu_persistent_image = extract_programmer_param("image"); @@ -1052,6 +1069,9 @@ msg_cdbg("%s: set flash->total_size to %dK bytes.\n", __func__, flash->chip->total_size); + if (emu_data->erase_to_zero) + flash->chip->feature_bits |= FEATURE_ERASED_ZERO; + /* Update the first count of each of the block_erasers. */ for (i = 0; i < NUM_ERASEFUNCTIONS; i++) { struct block_eraser *eraser = &flash->chip->block_erasers[i]; -- To view, visit https://review.coreboot.org/c/flashrom/+/47859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I37c6dee932e449201d8bbfb03ca6d139da3cb6a2 Gerrit-Change-Number: 47859 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 7

Change in flashrom[master]: programmer.h,c: Drop dead noop_chip_writeb() fn
by Edward O'Callaghan (Code Review) 24 Nov '20

24 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47894 ) Change subject: programmer.h,c: Drop dead noop_chip_writeb() fn ...................................................................... programmer.h,c: Drop dead noop_chip_writeb() fn Drop dead code. BUG=none BRANCH=none TEST=`git grep noop_chip_writeb` Change-Id: I160406df903b3b0a49a5ff3ec78a030e10fa60a0 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M programmer.c M programmer.h 2 files changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/47894/1 diff --git a/programmer.c b/programmer.c index f4b4384..5c841ef 100644 --- a/programmer.c +++ b/programmer.c @@ -35,11 +35,6 @@ { } -/* No-op chip_writeb() for parallel style drivers not supporting writes */ -void noop_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) -{ -} - /* Little-endian fallback for drivers not supporting 16 bit accesses */ void fallback_chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr) diff --git a/programmer.h b/programmer.h index 1bd0d37..ed30d89 100644 --- a/programmer.h +++ b/programmer.h @@ -730,7 +730,6 @@ int noop_shutdown(void); void *fallback_map(const char *descr, uintptr_t phys_addr, size_t len); void fallback_unmap(void *virt_addr, size_t len); -void noop_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); void fallback_chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr); void fallback_chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr); void fallback_chip_writen(const struct flashctx *flash, const uint8_t *buf, chipaddr addr, size_t len); -- To view, visit https://review.coreboot.org/c/flashrom/+/47894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I160406df903b3b0a49a5ff3ec78a030e10fa60a0 Gerrit-Change-Number: 47894 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 2

Change in flashrom[master]: WIP: wpce775x.c: import file from cros flashrom
by Nikolai Artemiev (Code Review) 24 Nov '20

24 Nov '20

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47641 ) Change subject: WIP: wpce775x.c: import file from cros flashrom ...................................................................... WIP: wpce775x.c: import file from cros flashrom Change-Id: I10ef0ae65a8f2bf5e3abc4f80be31dd70c7d31b4 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M Makefile M programmer.h A wpce775x.c 3 files changed, 1,009 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/41/47641/1 diff --git a/Makefile b/Makefile index 0498624..d2d8152 100644 --- a/Makefile +++ b/Makefile @@ -648,7 +648,7 @@ CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \ sst28sf040.o 82802ab.o \ sst49lfxxxc.o sst_fwhub.o edi.o flashchips.o spi.o spi25.o spi25_statusreg.o \ - spi95.o opaque.o sfdp.o en29lv640b.o at45db.o writeprotect.o + spi95.o opaque.o sfdp.o en29lv640b.o at45db.o writeprotect.o wpce775x.o ############################################################################### # Library code. diff --git a/programmer.h b/programmer.h index 1bd0d37..9916605 100644 --- a/programmer.h +++ b/programmer.h @@ -787,6 +787,9 @@ int serialport_read(unsigned char *buf, unsigned int readcnt); int serialport_read_nonblock(unsigned char *c, unsigned int readcnt, unsigned int timeout, unsigned int *really_read); +/* wpce775x.c */ +int wpce775x_probe_spi_flash(const char *name); + /* Serial port/pin mapping: 1 CD <- diff --git a/wpce775x.c b/wpce775x.c new file mode 100644 index 0000000..7f3b56e --- /dev/null +++ b/wpce775x.c @@ -0,0 +1,1005 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * Neither the name of Nuvoton Technology Corporation. or the names of + * contributors or licensors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * This software is provided "AS IS," without a warranty of any kind. + * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, + * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. + * NUVOTON TECHNOLOGY CORPORATION. ("NUVOTON") AND ITS LICENSORS SHALL NOT BE LIABLE + * FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING + * OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL + * SUN OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, + * OR FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR + * PUNITIVE DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF + * LIABILITY, ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, + * EVEN IF SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * + * This is an UNOFFICIAL patch for the Nuvoton WPCE775x/NPCE781x. It was tested + * for a specific hardware and firmware configuration and should be considered + * unreliable. Please see the following URL for Nuvoton's authoritative, + * officially supported flash update utility: + * http://sourceforge.net/projects/nuvflashupdate/ + */ + +#if defined(__i386__) || defined(__x86_64__) +#include <assert.h> +#include <string.h> +#include <sys/time.h> +#include <time.h> +#include <unistd.h> +#include <stdlib.h> +#include "flash.h" +#include "chipdrivers.h" +#include "flashchips.h" +#include "programmer.h" +#include "spi.h" +#include "writeprotect.h" + +/** + * Definition of WPCE775X WCB (Write Command Buffer), as known as Shared Access + * Window 2. + * + * The document name is "WPCE775X Software User Guide Revision 1.2". + * + * Assume the host is little endian. + */ +struct __attribute__((packed)) wpce775x_wcb { + /* Byte 0: semaphore byte */ + uint8_t exe:1; /* Bit0-RW- set by host. means wcb is ready to execute. + should be cleared by host after RDY=1. */ + uint8_t resv0_41:4; + uint8_t pcp:1; /* Bit5-RO- set by EPCE775x. means preparation operations for + flash update process is complete. */ + uint8_t err:1; /* Bit6-RO- set by EPCE775x. means an error occurs. */ + uint8_t rdy:1; /* Bit7-RO- set by EPCE775x. means operation is completed. */ + + /* Byte 1-2: reserved */ + uint8_t byte1; + uint8_t byte2; + + /* Byte 3: command code */ + uint8_t code; + + /* Byte 4-15: command field */ + uint8_t field[12]; +}; + +/* The physical address of WCB -- Shared Access Window 2. */ +static chipaddr wcb_physical_address; + +/* The virtual address of WCB -- Shared Access Window 2. */ +static volatile struct wpce775x_wcb *volatile wcb; + +/* count of entering flash update mode */ +static int in_flash_update_mode; + +static int firmware_changed; + +/* + * Bytes 0x4-0xf of init_flash command. These represent opcodes and various + * parameters the WPCE775x will use when communicating with the SPI flash + * device. DO NOT RE-ORDER THIS STRUCTURE. + */ +struct wpce775x_initflash_cfg { + uint8_t read_device_id; /* Byte 0x04. Ex: JEDEC_RDID */ + uint8_t write_status_enable; /* Byte 0x05. Ex: JEDEC_EWSR */ + uint8_t write_enable; /* Byte 0x06. Ex: JEDEC_WREN */ + uint8_t read_status_register; /* Byte 0x07. Ex: JEDEC_RDSR */ + uint8_t write_status_register; /* Byte 0x08. Ex: JEDEC_WRSR */ + uint8_t flash_program; /* Byte 0x09. Ex: JEDEC_BYTE_PROGRAM */ + + /* Byte 0x0A. Ex: sector/block/chip erase opcode */ + uint8_t block_erase; + + uint8_t status_busy_mask; /* Byte B: bit position of BUSY bit */ + + /* Byte 0x0C: value to remove write protection */ + uint8_t status_reg_value; + + /* Byte 0x0D: Number of bytes to program in each write transaction. */ + uint8_t program_unit_size; + + uint8_t page_size; /* Byte 0x0E: 2^n bytes */ + + /* + * Byte 0x0F: Method to read device ID. 0x47 will cause ID bytes to be + * read immediately after read_device_id command is issued. Otherwise, + * 3 dummy address bytes are sent after the read_device_id code. + */ + uint8_t read_device_id_type; +} __attribute__((packed)); + +/* + * The WPCE775x can use init_flash multiple times during an update. We'll use + * this ability primarily for changing write protection bits. + */ +static struct wpce775x_initflash_cfg *initflash_cfg; + +/* SuperI/O related definitions and functions. */ +/* Strapping options */ +#define NUVOTON_SIO_PORT1 0x2e /* No pull-down resistor */ +#define NUVOTON_SIO_PORT2 0x164e /* Pull-down resistor on BADDR0 */ +/* Note: There's another funky state that we won't worry about right now */ + +/* SuperI/O Config */ +#define NUVOTON_SIOCFG_LDN 0x07 /* LDN Bank Selector */ +#define NUVOTON_SIOCFG_SID 0x20 /* SuperI/O ID */ +#define NUVOTON_SIOCFG_SRID 0x27 /* SuperI/O Revision ID */ +#define NUVOTON_LDN_SHM 0x0f /* LDN of SHM module */ + +/* WPCE775x shared memory config registers (LDN 0x0f) */ +#define WPCE775X_SHM_BASE_MSB 0x60 +#define WPCE775X_SHM_BASE_LSB 0x61 +#define WPCE775X_SHM_CFG 0xf0 +#define WPCE775X_SHM_CFG_BIOS_FWH_EN (1 << 3) +#define WPCE775X_SHM_CFG_FLASH_ACC_EN (1 << 2) +#define WPCE775X_SHM_CFG_BIOS_EXT_EN (1 << 1) +#define WPCE775X_SHM_CFG_BIOS_LPC_EN (1 << 0) +#define WPCE775X_WIN_CFG 0xf1 /* window config */ +#define WPCE775X_WIN_CFG_SHWIN_ACC (1 << 6) + +/* Shared access window 2 bar address registers */ +#define WPCE775X_SHAW2BA_0 0xf8 +#define WPCE775X_SHAW2BA_1 0xf9 +#define WPCE775X_SHAW2BA_2 0xfa +#define WPCE775X_SHAW2BA_3 0xfb + +/* Read/write buffer size */ +#define WPCE775X_MAX_WRITE_SIZE 8 +#define WPCE775X_MAX_READ_SIZE 12 + +/** probe for super i/o index + * @returns 0 to indicate success, <0 to indicate error + */ +static int nuvoton_get_sio_index(uint16_t *port) +{ + uint16_t ports[] = { NUVOTON_SIO_PORT2, + NUVOTON_SIO_PORT1, + }; + static uint16_t port_internal, port_found = 0; + + if (port_found) { + *port = port_internal; + return 0; + } + + if (rget_io_perms()) + return 1; + + for (size_t i = 0; i < ARRAY_SIZE(ports); i++) { + uint8_t sid = sio_read(ports[i], NUVOTON_SIOCFG_SID); + + if (sid == 0xfc) { /* Family ID */ + port_internal = ports[i]; + port_found = 1; + break; + } + } + + if (!port_found) { + msg_cdbg("\nfailed to obtain super i/o index\n"); + return -1; + } + + msg_cdbg("\nsuper i/o index = 0x%04x\n", port_internal); + *port = port_internal; + return 0; +} + +/** Call superio to get pre-configured WCB address. + * Read LDN 0x0f (SHM) idx:f8-fb (little-endian). + */ +static int get_shaw2ba(chipaddr *shaw2ba) +{ + uint16_t idx; + uint8_t org_ldn; + uint8_t win_cfg; + uint8_t shm_cfg; + + if (nuvoton_get_sio_index(&idx) < 0) + return -1; + + org_ldn = sio_read(idx, NUVOTON_SIOCFG_LDN); + sio_write(idx, NUVOTON_SIOCFG_LDN, NUVOTON_LDN_SHM); + + /* + * To obtain shared access window 2 base address, we must OR the base + * address bytes, where SHAW2BA_0 is least significant and SHAW2BA_3 + * most significant. + */ + *shaw2ba = sio_read(idx, WPCE775X_SHAW2BA_0) | + ((chipaddr)sio_read(idx, WPCE775X_SHAW2BA_1) << 8) | + ((chipaddr)sio_read(idx, WPCE775X_SHAW2BA_2) << 16) | + ((chipaddr)sio_read(idx, WPCE775X_SHAW2BA_3) << 24); + + /* + * If SHWIN_ACC is cleared, then we're using LPC memory access + * and SHAW2BA_3-0 indicate bits 31-0. If SHWIN_ACC is set, then + * bits 7-4 of SHAW2BA_3 are ignored and bits 31-28 are indicated + * by the idsel nibble. (See table 25 "supported host address ranges" + * for more details) + */ + win_cfg = sio_read(idx, WPCE775X_WIN_CFG); + if (win_cfg & WPCE775X_WIN_CFG_SHWIN_ACC) { + uint8_t idsel; + + /* Make sure shared BIOS memory is enabled */ + shm_cfg = sio_read(idx, WPCE775X_SHM_CFG); + if ((shm_cfg & WPCE775X_SHM_CFG_BIOS_FWH_EN)) + idsel = 0xf; + else { + msg_cdbg("Shared BIOS memory is diabled.\n"); + msg_cdbg("Please check SHM_CFG:BIOS_FWH_EN.\n"); + goto error; + } + + *shaw2ba &= 0x0fffffff; + *shaw2ba |= (chipaddr)idsel << 28; + } + + sio_write(idx, NUVOTON_SIOCFG_LDN, org_ldn); + return 0; +error: + sio_write(idx, NUVOTON_SIOCFG_LDN, org_ldn); + return -1; +} + +/* Call superio to get pre-configured fwh_id. + * Read LDN 0x0f (SHM) idx:f0. + */ +static int get_fwh_id(uint8_t *fwh_id) +{ + uint16_t idx; + uint8_t org_ldn; + + if (nuvoton_get_sio_index(&idx) < 0) + return -1; + + org_ldn = sio_read(idx, NUVOTON_SIOCFG_LDN); + sio_write(idx, NUVOTON_SIOCFG_LDN, NUVOTON_LDN_SHM); + *fwh_id = sio_read(idx, WPCE775X_SHM_CFG); + sio_write(idx, NUVOTON_SIOCFG_LDN, org_ldn); + + return 0; +} + +/** helper function to make sure the exe bit is 0 (no one is using EC). + * @return 1 for error; 0 for success. + */ +static int assert_ec_is_free(void) +{ + if (wcb->exe) + msg_perr("ASSERT(wcb->exe==0), entering busy loop.\n"); + while(wcb->exe); + return 0; +} + +/** Trigger EXE bit, and block until operation completes. + * @return 1 for error; and 0 for success. + */ +static int blocked_exec(void) +{ + struct timeval begin, now; + int timeout; /* not zero if timeout occurs */ + int err; + + assert(wcb->rdy==0); + + /* raise EXE bit, and wait for operation complete or error occur. */ + wcb->exe = 1; + + timeout = 0; + gettimeofday(&begin, NULL); + while(wcb->rdy==0 && wcb->err==0) { + gettimeofday(&now, NULL); + /* According to Nuvoton's suggestion, few seconds is enough for + * longest flash operation, which is erase. + * Cutted from W25X16 datasheet, for max operation time + * Byte program tBP1 50us + * Page program tPP 3ms + * Sector Erase (4KB) tSE 200ms + * Block Erase (64KB) tBE 1s + * Chip Erase tCE 20s + * Since WPCE775x doesn't support chip erase, + * 3 secs is long enough for block erase. + */ + if ((now.tv_sec - begin.tv_sec) >= 4) { + timeout += 1; + break; + } + } + + /* keep ERR bit before clearing EXE bit. */ + err = wcb->err; + + /* Clear EXE bit, and wait for RDY back to 0. */ + wcb->exe = 0; + gettimeofday(&begin, NULL); + while(wcb->rdy) { + gettimeofday(&now, NULL); + /* 1 sec should be long enough for clearing rdy bit. */ + if (((now.tv_sec - begin.tv_sec)*1000*1000 + + (now.tv_usec - begin.tv_usec)) >= 1000*1000) { + timeout += 1; + break; + } + } + + if (err || timeout) { + msg_cdbg("err=%d timeout=%d\n", err, timeout); + return 1; + } + return 0; +} + +/** Initialize the EC parameters. + + * @return 1 for error; 0 for success. + */ +static int init_flash() +{ + if (!initflash_cfg) { + msg_perr("%s(): init_flash config is not defined\n", __func__); + return 1; + } + + assert_ec_is_free(); + /* Byte 3: command code: Init Flash */ + wcb->code = 0x5A; + msg_pdbg("%s(): init_flash bytes: ", __func__); + for (size_t i = 0; i < sizeof(struct wpce775x_initflash_cfg); i++) { + wcb->field[i] = *((uint8_t *)initflash_cfg + i); + msg_pdbg("%02x ", wcb->field[i]); + } + msg_pdbg("\n"); + + if (blocked_exec()) + return 1; + return 0; +} + +/* log2() could be used if we link with -lm */ +static int logbase2(int x) +{ + int log = 0; + + /* naive way */ + while (x) { + x >>= 1; + log++; + } + return log; +} + +/* initialize initflash_cfg struct */ +static int initflash_cfg_setup(const struct flashctx *flash) +{ + if (!initflash_cfg) + initflash_cfg = malloc(sizeof(*initflash_cfg)); + + /* Set "sane" defaults. If the flash chip is known, then use parameters + from it. */ + initflash_cfg->read_device_id = JEDEC_RDID; + if (flash && (flash->chip->feature_bits | FEATURE_WRSR_WREN)) + initflash_cfg->write_status_enable = JEDEC_WREN; + else if (flash && (flash->chip->feature_bits | FEATURE_WRSR_EWSR)) + initflash_cfg->write_status_enable = JEDEC_EWSR; + else + initflash_cfg->write_status_enable = JEDEC_WREN; + initflash_cfg->write_enable = JEDEC_WREN; + initflash_cfg->read_status_register = JEDEC_RDSR; + initflash_cfg->write_status_register = JEDEC_WRSR; + initflash_cfg->flash_program = JEDEC_BYTE_PROGRAM; + + /* note: these members are likely to be overridden later */ + initflash_cfg->block_erase = JEDEC_SE; + initflash_cfg->status_busy_mask = 0x01; + initflash_cfg->status_reg_value = 0x00; + + /* back to "sane" defaults... */ + initflash_cfg->program_unit_size = 0x01; + if (flash) + initflash_cfg->page_size = logbase2(flash->chip->page_size); + else + initflash_cfg->page_size = 0x08; + + initflash_cfg->read_device_id_type = 0x00; + + return 0; +} + +/** Read flash vendor/device IDs through EC. + * @param id0, id1, id2, id3 Pointers to store detected IDs. NULL will be ignored. + * @return 1 for error; 0 for success. + */ +static int read_id(const struct flashctx *flash, + uint8_t* id0, uint8_t* id1, + uint8_t* id2, uint8_t* id3) +{ + if (!initflash_cfg) { + initflash_cfg_setup(flash); + init_flash(); + } + + assert_ec_is_free(); + + wcb->code = 0xC0; /* Byte 3: command code: Read ID */ + if (blocked_exec()) + return 1; + + msg_cdbg("id0: 0x%2x, id1: 0x%2x, id2: 0x%2x, id3: 0x%2x\n", + wcb->field[0], wcb->field[1], wcb->field[2], wcb->field[3]); + if (id0) { + *id0 = wcb->field[0]; + } + if (id1) { + *id1 = wcb->field[1]; + } + if (id2) { + *id2 = wcb->field[2]; + } + if (id3) { + *id3 = wcb->field[3]; + } + + return 0; +} + +/** Tell EC to "enter flash update" mode. */ +static int enter_flash_update() +{ + if (in_flash_update_mode) { + /* already in update mode */ + msg_pdbg("%s: in_flash_update_mode: %d\n", + __func__, in_flash_update_mode); + return 0; + } + assert_ec_is_free(); + + wcb->code = 0x10; /* Enter Flash Update */ + wcb->field[0] = 0x55; /* required pattern by EC */ + wcb->field[1] = 0xAA; /* required pattern by EC */ + wcb->field[2] = 0xCD; /* required pattern by EC */ + wcb->field[3] = 0xBE; /* required pattern by EC */ + if (blocked_exec()) { + return 1; + } else { + in_flash_update_mode = 1; + return 0; + } +} + +/** Tell EC to "exit flash update" mode. + * Without calling this function, the EC stays in busy-loop and will not + * response further request from host, which means system will halt. + */ +static int exit_flash_update(uint8_t exit_code) +{ + /* + * Note: exit_flash_update must be called before shutting down the + * machine, otherwise the EC will be stuck in update mode, leaving + * the machine in a "wedged" state until power cycled. + */ + if (!in_flash_update_mode) { + msg_cdbg("Not in flash update mode yet.\n"); + return 1; + } + + wcb->code = exit_code; /* Exit Flash Update */ + if (blocked_exec()) { + return 1; + } + + in_flash_update_mode = 0; + return 0; +} + +/* + * Note: The EC firmware this patch has been tested with uses the following + * codes to indicate flash update status: + * 0x20 is used for EC F/W no change, but BIOS changed (in Share mode) + * 0x21 is used for EC F/W changed. Goto EC F/W, wait system reboot. + * 0x22 is used for EC F/W changed, Goto EC Watchdog reset. */ +static int exit_flash_update_firmware_no_change(void) { + return exit_flash_update(0x20); +} + +static int exit_flash_update_firmware_changed(void) { + return exit_flash_update(0x21); +} + +static int wpce775x_read(int addr, uint8_t *buf, unsigned int nbytes) +{ + unsigned int bytes_read = 0; + + assert_ec_is_free(); + msg_pspew("%s: reading %d bytes at 0x%06x\n", __func__, nbytes, addr); + + /* Set initial address; WPCE775x auto-increments address for successive + read and write operations. */ + wcb->code = 0xA0; + wcb->field[0] = addr & 0xff; + wcb->field[1] = (addr >> 8) & 0xff; + wcb->field[2] = (addr >> 16) & 0xff; + wcb->field[3] = (addr >> 24) & 0xff; + if (blocked_exec()) { + return 1; + } + + for (unsigned int offset = 0; offset < nbytes; offset += bytes_read) { + unsigned int bytes_left; + + bytes_left = nbytes - offset; + if (bytes_left > 0 && bytes_left < WPCE775X_MAX_READ_SIZE) + bytes_read = bytes_left; + else + bytes_read = WPCE775X_MAX_READ_SIZE; + wcb->code = 0xD0 | bytes_read; + if (blocked_exec()) { + return 1; + } + + for (size_t i = 0; i < bytes_read; i++) + buf[offset + i] = wcb->field[i]; + } + + return 0; +} + +static int wpce775x_erase_new(const struct flashctx *flash, int blockaddr, uint8_t opcode) { + unsigned int blocksize; + int ret = 0; + + assert_ec_is_free(); + + /* + * FIXME: In the long-run we should examine block_erasers within the + * flash struct to ensure the proper blocksize is used. This is because + * some chips implement commands differently. For now, we'll support + * only a few "safe" block erase commands with predictable block size. + * + * Looking thru the list of flashchips, it seems JEDEC_BE_52 and + * JEDEC_BE_D8 are not uniformly implemented. Thus, we cannot safely + * assume a blocksize. + * + * Also, I was unable to test chip erase (due to equipment and time + * constraints), but they might work. + */ + switch(opcode) { + case JEDEC_SE: + case JEDEC_BE_D7: + blocksize = 4 * 1024; + break; + case JEDEC_BE_52: + case JEDEC_BE_D8: + case JEDEC_CE_60: + case JEDEC_CE_C7: + default: + msg_perr("%s(): erase opcode=0x%02x not supported\n", + __func__, opcode); + return 1; + } + + msg_pspew("%s(): blockaddr=%d, blocksize=%d, opcode=0x%02x\n", + __func__, blockaddr, blocksize, opcode); + + if (!initflash_cfg) + initflash_cfg_setup(flash); + initflash_cfg->block_erase = opcode; + init_flash(); + + /* Set Write Window on flash chip (optional). + * You may limit the window to partial flash for experimental. */ + wcb->code = 0xC5; /* Set Write Window */ + wcb->field[0] = 0x00; /* window base: little-endian */ + wcb->field[1] = 0x00; + wcb->field[2] = 0x00; + wcb->field[3] = 0x00; + wcb->field[4] = 0x00; /* window length: little-endian */ + wcb->field[5] = 0x00; + wcb->field[6] = 0x20; + wcb->field[7] = 0x00; + if (blocked_exec()) + return 1; + + msg_pspew("Erasing ... 0x%08x 0x%08x\n", blockaddr, blocksize); + + for (unsigned int current = 0; + current < blocksize; + current += blocksize) { + wcb->code = 0x80; /* Sector/block erase */ + + /* WARNING: assume the block address for EC is always little-endian. */ + unsigned int addr = blockaddr + current; + wcb->field[0] = addr & 0xff; + wcb->field[1] = (addr >> 8) & 0xff; + wcb->field[2] = (addr >> 16) & 0xff; + wcb->field[3] = (addr >> 24) & 0xff; + if (blocked_exec()) { + ret = 1; + goto wpce775x_erase_new_exit; + } + } + +wpce775x_erase_new_exit: + firmware_changed = 1; + return ret; +} + +static int wpce775x_nbyte_program(int addr, const uint8_t *buf, + unsigned int nbytes) +{ + int ret = 0; + unsigned int written = 0; + + assert_ec_is_free(); + msg_pspew("%s: writing %d bytes to 0x%06x\n", __func__, nbytes, addr); + + /* Set initial address; WPCE775x auto-increments address for successive + read and write operations. */ + wcb->code = 0xA0; + wcb->field[0] = addr & 0xff; + wcb->field[1] = (addr >> 8) & 0xff; + wcb->field[2] = (addr >> 16) & 0xff; + wcb->field[3] = (addr >> 24) & 0xff; + if (blocked_exec()) { + return 1; + } + + for (unsigned int offset = 0; offset < nbytes; offset += written) { + unsigned int bytes_left; + + bytes_left = nbytes - offset; + if (bytes_left > 0 && bytes_left < WPCE775X_MAX_WRITE_SIZE) + written = bytes_left; + else + written = WPCE775X_MAX_WRITE_SIZE; + wcb->code = 0xB0 | written; + + for (size_t i = 0; i < written; i++) + wcb->field[i] = buf[offset + i]; + if (blocked_exec()) { + ret = 1; + goto wpce775x_nbyte_program_exit; + } + } + +wpce775x_nbyte_program_exit: + firmware_changed = 1; + return ret; +} + +static int wpce775x_spi_read(struct flashctx *flash, uint8_t * buf, + unsigned int start, unsigned int len) +{ + if (!initflash_cfg) { + initflash_cfg_setup(flash); + init_flash(); + } + return spi_read_chunked(flash, buf, start, len, + flash->chip->page_size); +} + +static int wpce775x_spi_write_256(struct flashctx *flash, const uint8_t *buf, + unsigned int start, unsigned int len) +{ + if (!initflash_cfg) { + initflash_cfg_setup(flash); + init_flash(); + } + return spi_write_chunked(flash, buf, start, len, + flash->chip->page_size); +} + +static int wpce775x_spi_read_status_register(unsigned int readcnt, uint8_t *readarr) +{ + uint8_t before[2]; + int ret = 0; + + assert_ec_is_free(); + msg_pdbg("%s(): reading status register.\n", __func__); + + /* We need to detect if EC firmware support this 0x30 command. + * 1. write a non-sense value to field[0] and field[1]. + * 2. execute command 0x30. + * 3. if field[0] is NOT changed, that means 0x30 is not supported, + * use initflash_cfg->status_reg_value instead. + * else, 0x30 works and returns field[]. + */ + wcb->field[0] = ~initflash_cfg->status_reg_value; + wcb->field[1] = 0xfc; /* set reserved bits to 1s */ + /* save original values */ + for (size_t i = 0; i < ARRAY_SIZE(before); i++) + before[i] = wcb->field[i]; + + wcb->code = 0x30; /* JEDEC_RDSR */ + if (blocked_exec()) { + ret = 1; + msg_perr("%s(): blocked_exec() returns error.\n", __func__); + } + msg_pdbg("%s(): WCB code=0x%02x field[]= ", __func__, wcb->code); + for (size_t i = 0; i < readcnt; ++i) { + readarr[i] = wcb->field[i]; + msg_pdbg("%02x ", wcb->field[i]); + } + msg_pdbg("\n"); + + /* FIXME: not sure EC returns 1 or 2 bytes for command 0x30, + * now we check field[0] only. + * Shall check field[1] if EC always returns 2 bytes. */ + if (wcb->field[0] == before[0]) { + /* field is not changed, 0x30 command doesn't work. */ + readarr[0] = initflash_cfg->status_reg_value; + readarr[1] = 0; /* TODO: if second status register exists */ + msg_pdbg("%s(): command 0x30 seems NOT working.\n", __func__); + } else { + /* 0x30 command seems working! */ + initflash_cfg->status_reg_value = readarr[0]; + msg_pdbg("%s(): command 0x30 seems working.\n", __func__); + } + + return ret; +} + +static int wpce775x_spi_write_status_register(const struct flashctx *flash, uint8_t val) +{ + assert_ec_is_free(); + msg_pdbg("%s(): writing 0x%02x to status register\n", __func__, val); + + if (!initflash_cfg) + initflash_cfg_setup(flash); + + initflash_cfg->status_reg_value = val; + if (in_flash_update_mode) { + exit_flash_update_firmware_no_change(); + in_flash_update_mode = 0; + } + if (init_flash()) + return 1; + if (enter_flash_update()) + return 1; + return 0; +} + +/* + * WPCE775x does not allow direct access to SPI chip from host. This function + * will translate SPI commands to valid WPCE775x WCB commands. + */ +static int wpce775x_spi_send_command(const struct flashctx *flash, + unsigned int writecnt, + unsigned int readcnt, + const uint8_t *writearr, + uint8_t *readarr) +{ + int rc = 0; + uint8_t opcode = writearr[0]; + + switch(opcode){ + case JEDEC_RDID:{ + uint8_t dummy = 0; + if (readcnt == 3) + read_id(flash, &readarr[0], &readarr[1], &readarr[2], &dummy); + else if (readcnt == 4) + read_id(flash, &readarr[0], &readarr[1], &readarr[2], &readarr[3]); + break; + } + case JEDEC_RDSR: + rc = wpce775x_spi_read_status_register(readcnt, readarr); + break; + case JEDEC_READ:{ + int blockaddr = ((int)writearr[1] << 16) | + ((int)writearr[2] << 8) | + writearr[3]; + rc = wpce775x_read(blockaddr, readarr, readcnt); + break; + } + case JEDEC_WRSR: + wpce775x_spi_write_status_register(flash, writearr[1]); + rc = 0; + break; + case JEDEC_WREN: + case JEDEC_EWSR: + /* Handled by init_flash() */ + rc = 0; + break; + case JEDEC_SE: + case JEDEC_BE_52: + case JEDEC_BE_D7: + case JEDEC_BE_D8: + case JEDEC_CE_60: + case JEDEC_CE_C7:{ + int blockaddr = ((int)writearr[1] << 16) | + ((int)writearr[2] << 8) | + writearr[3]; + + rc = wpce775x_erase_new(flash, blockaddr, opcode); + break; + } + case JEDEC_BYTE_PROGRAM:{ + int blockaddr = ((int)writearr[1] << 16) | + ((int)writearr[2] << 8) | + writearr[3]; + int nbytes = writecnt - 4; + + rc = wpce775x_nbyte_program(blockaddr, &writearr[4], nbytes); + break; + } + case JEDEC_REMS: + case JEDEC_RES: + case JEDEC_WRDI: + case JEDEC_AAI_WORD_PROGRAM: + default: + /* unsupported opcodes */ + msg_pdbg("unsupported SPI opcode: %02x\n", opcode); + rc = 1; + break; + } + + msg_pdbg("%s: opcode: 0x%02x\n", __func__, opcode); + return rc; +} + +static int wpce775x_shutdown(void *data) +{ + msg_pdbg("%s(): firmware %s\n", __func__, + firmware_changed ? "changed" : "not changed"); + + msg_pdbg("%s: in_flash_update_mode: %d\n", __func__, in_flash_update_mode); + if (in_flash_update_mode) { + if (firmware_changed) + exit_flash_update_firmware_changed(); + else + exit_flash_update_firmware_no_change(); + + in_flash_update_mode = 0; + } + + if (initflash_cfg) + free(initflash_cfg); + else + msg_perr("%s(): No initflash_cfg to free?!?\n", __func__); + + return 0; +} + +static const struct spi_master spi_master_wpce775x = { + .max_data_read = 256, /* FIXME: should be MAX_DATA_READ_UNLIMITED? */ + .max_data_write = 256, /* FIXME: should be MAX_DATA_WRITE_UNLIMITED? */ + .command = wpce775x_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = wpce775x_spi_read, + .write_256 = wpce775x_spi_write_256, +}; + +static int wpce775x_spi_common_init(void) +{ + uint8_t fwh_id; + + msg_pdbg("%s(): entered\n", __func__); + + /* + * FIXME: This is necessary to ensure that access to the shared access + * window region is sent on the LPC bus. The old CLI syntax + * (-p internal:bus=lpc) would cause the chipset enable code to set the + * target bus appropriately before this function gets run, but the new + * syntax ("-p ec") does not cause that to happen. + */ + // WIP: need to change this! + // target_bus = BUS_LPC; + // msg_pdbg("%s: forcing target bus: 0x%08x\n", __func__, target_bus); + chipset_flash_enable(); + + /* get the address of Shadow Window 2. */ + if (get_shaw2ba(&wcb_physical_address) < 0) { + msg_pdbg("Cannot get the address of Shadow Window 2"); + return 1; + } + msg_pdbg("Get the address of WCB(SHA WIN2) at 0x%08lx\n", + wcb_physical_address); + wcb = (struct wpce775x_wcb *) + programmer_map_flash_region("WPCE775X WCB", + wcb_physical_address, + getpagesize() /* min page size */); + msg_pdbg("mapped wcb address: %p for physical addr: 0x%08lx\n", wcb, wcb_physical_address); + if (!wcb) { + msg_perr("FATAL! Cannot map memory area for wcb physical address.\n"); + return 1; + } + memset((void*)wcb, 0, sizeof(*wcb)); + + if (get_fwh_id(&fwh_id) < 0) { + msg_pdbg("Cannot get fwh_id value.\n"); + return 1; + } + msg_pdbg("get fwh_id: 0x%02x\n", fwh_id); + + /* TODO: set fwh_idsel of chipset. + Currently, we employ "-p internal:fwh_idsel=0x0000223e". */ + + if (register_shutdown(wpce775x_shutdown, NULL)) + return 1; + + /* Enter flash update mode unconditionally. This is required even + for reading. */ + if (enter_flash_update()) return 1; + + /* Add FWH | LPC to list of buses supported if they are not + * both there already. */ + // WIP: need to change this! + // buses_supported |= BUS_FWH | BUS_LPC; + register_spi_master(&spi_master_wpce775x); + msg_pdbg("%s(): successfully initialized wpce775x\n", __func__); + return 0; +} + +static int wpce775x_probe_superio() +{ + uint16_t sio_port; + uint8_t srid; + + /* detect if wpce775x exists */ + if (nuvoton_get_sio_index(&sio_port) < 0) { + msg_pdbg("No Nuvoton chip is found.\n"); + return 1; + } + srid = sio_read(sio_port, NUVOTON_SIOCFG_SRID); + if ((srid & 0xE0) == 0xA0) { + msg_pdbg("Found EC: WPCE775x " + "(Vendor:0x%02x,ID:0x%02x,Rev:0x%02x) on sio_port:0x%x.\n", + sio_read(sio_port, NUVOTON_SIOCFG_SID), + srid >> 5, srid & 0x1f, sio_port); + } else { + msg_pdbg("Found EC: Nuvoton " + "(Vendor:0x%02x,ID:0x%02x,Rev:0x%02x) on sio_port:0x%x.\n", + sio_read(sio_port, NUVOTON_SIOCFG_SID), + srid >> 5, srid & 0x1f, sio_port); + } + + return 0; +} + +/* Called by internal_init() */ +int wpce775x_probe_spi_flash(const char *name) +{ + int ret = 0; + char *p = NULL; + + p = extract_programmer_param("type"); + if (p && strcmp(p, "ec")) { + msg_pdbg("mec1308 only supports \"ec\" type devices\n"); + ret = 1; + goto wpce775x_probe_spi_flash_exit; + } + + if (wpce775x_probe_superio()) { + ret = 1; + goto wpce775x_probe_spi_flash_exit; + } + + if (wpce775x_spi_common_init()) { + ret = 1; + goto wpce775x_probe_spi_flash_exit; + } + +wpce775x_probe_spi_flash_exit: + free(p); + return ret; +} +#endif /* __i386__ || __x86_64__ */ -- To view, visit https://review.coreboot.org/c/flashrom/+/47641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I10ef0ae65a8f2bf5e3abc4f80be31dd70c7d31b4 Gerrit-Change-Number: 47641 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

2 4

Change in flashrom[master]: tests/: [RFC]: Implement unit-testing using mtest
by Edward O'Callaghan (Code Review) 24 Nov '20

24 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38954 ) Change subject: tests/: [RFC]: Implement unit-testing using mtest ...................................................................... tests/: [RFC]: Implement unit-testing using mtest The following allows the use of a ultra minimal unit-testing framework and includes an example that exercises the libflashrom init self-check and tear-down. Some work is needed to get include paths into a healthy state so that inner logic can be instrumented however this sets the tone. Change-Id: I18d68d3ace32b5be264aae2988a8ed84c779be43 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M meson.build A tests/meson.build A tests/selfcheck.c 3 files changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/38954/1 diff --git a/meson.build b/meson.build index 375089c..8a998d0 100644 --- a/meson.build +++ b/meson.build @@ -402,3 +402,10 @@ ) subdir('util') + +# unit-test framework +munit_dep = dependency( + 'munit', + fallback: ['munit', 'munit_dep'] +) +subdir('tests') diff --git a/tests/meson.build b/tests/meson.build new file mode 100644 index 0000000..af65a81 --- /dev/null +++ b/tests/meson.build @@ -0,0 +1,12 @@ +root_includes = include_directories(['../', '../subprojects']) + +srcs = files('selfcheck.c') + +flashrom_tests = executable('flashrom_unit_tests', + srcs, + include_directories : root_includes, + dependencies : munit_dep, + link_with : flashrom +) + +test('munit test flashrom', flashrom_tests) diff --git a/tests/selfcheck.c b/tests/selfcheck.c new file mode 100644 index 0000000..abe88b1 --- /dev/null +++ b/tests/selfcheck.c @@ -0,0 +1,41 @@ +#include <stdlib.h> + +#include "munit/munit.h" + +#include "libflashrom.h" + + +MunitResult self_check_test(const MunitParameter params[], void* user_data_or_fixture) +{ + //Programmer table miscompilation! + munit_assert(flashrom_init(1 /*perform_selfcheck*/) == 0); + munit_assert(flashrom_shutdown() == 0); + + return MUNIT_OK; +} + +MunitTest tests[] = { + { + (char *)"/self_check", /* name */ + self_check_test, /* test */ + NULL, /* setup */ + NULL, /* tear_down */ + MUNIT_TEST_OPTION_NONE, /* options */ + NULL /* parameters */ + }, + /* Mark the end of the array with an entry where the test + * function is NULL */ + { NULL, NULL, NULL, NULL, MUNIT_TEST_OPTION_NONE, NULL } +}; + +static const MunitSuite suite = { + (char *)"/basic", /* name */ + tests, /* tests */ + NULL, /* suites */ + 1, /* iterations */ + MUNIT_SUITE_OPTION_NONE /* options */ +}; + +int main (int argc, char* argv[]) { + return munit_suite_main(&suite, (char*)"flashrom", argc, argv); +} -- To view, visit https://review.coreboot.org/c/flashrom/+/38954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I18d68d3ace32b5be264aae2988a8ed84c779be43 Gerrit-Change-Number: 38954 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: wbsio_spi.c: Move singleton state into spi master state tracker
by Edward O'Callaghan (Code Review) 23 Nov '20

23 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47854 ) Change subject: wbsio_spi.c: Move singleton state into spi master state tracker ...................................................................... wbsio_spi.c: Move singleton state into spi master state tracker Make use of the reneterent framework by moving singleton static state out of the global life-time and into a per-spi_master basis. This allows for the it87spi master to be reneterent and its internal state's life-time to be correctly handled by Flashrom's core dispatch logic. BUG=none TEST=builds Change-Id: Ic97fa41daf26f27b68ced11ddc2a4da91d18f68e Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M wbsio_spi.c 1 file changed, 37 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/47854/1 diff --git a/wbsio_spi.c b/wbsio_spi.c index 26e3bb9..632ff72 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -16,6 +16,8 @@ #if defined(__i386__) || defined(__x86_64__) +#include <stdlib.h> + #include "flash.h" #include "chipdrivers.h" #include "programmer.h" @@ -25,7 +27,9 @@ #define WBSIO_PORT1 0x2e #define WBSIO_PORT2 0x4e -static uint16_t wbsio_spibase = 0; +struct wbsio_spi_data { + uint16_t spibase; +}; static uint16_t wbsio_get_spibase(uint16_t port) { @@ -87,10 +91,13 @@ msg_pspew("%s:", __func__); + const struct wbsio_spi_data *data = + (const struct wbsio_spi_data *)flash->mst->spi.data; + if (1 == writecnt && 0 == readcnt) { mode = 0x10; } else if (2 == writecnt && 0 == readcnt) { - OUTB(writearr[1], wbsio_spibase + 4); + OUTB(writearr[1], data->spibase + 4); msg_pspew(" data=0x%02x", writearr[1]); mode = 0x20; } else if (1 == writecnt && 2 == readcnt) { @@ -98,28 +105,28 @@ } else if (4 == writecnt && 0 == readcnt) { msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); for (i = 2; i < writecnt; i++) { - OUTB(writearr[i], wbsio_spibase + i); + OUTB(writearr[i], data->spibase + i); msg_pspew("%02x", writearr[i]); } mode = 0x40 | (writearr[1] & 0x0f); } else if (5 == writecnt && 0 == readcnt) { msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); for (i = 2; i < 4; i++) { - OUTB(writearr[i], wbsio_spibase + i); + OUTB(writearr[i], data->spibase + i); msg_pspew("%02x", writearr[i]); } - OUTB(writearr[i], wbsio_spibase + i); + OUTB(writearr[i], data->spibase + i); msg_pspew(" data=0x%02x", writearr[i]); mode = 0x50 | (writearr[1] & 0x0f); } else if (8 == writecnt && 0 == readcnt) { msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); for (i = 2; i < 4; i++) { - OUTB(writearr[i], wbsio_spibase + i); + OUTB(writearr[i], data->spibase + i); msg_pspew("%02x", writearr[i]); } msg_pspew(" data=0x"); for (; i < writecnt; i++) { - OUTB(writearr[i], wbsio_spibase + i); + OUTB(writearr[i], data->spibase + i); msg_pspew("%02x", writearr[i]); } mode = 0x60 | (writearr[1] & 0x0f); @@ -133,7 +140,7 @@ } else if (4 == writecnt && readcnt >= 1 && readcnt <= 4) { msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); for (i = 2; i < writecnt; i++) { - OUTB(writearr[i], wbsio_spibase + i); + OUTB(writearr[i], data->spibase + i); msg_pspew("%02x", writearr[i]); } mode = ((7 + readcnt) << 4) | (writearr[1] & 0x0f); @@ -147,8 +154,8 @@ return SPI_INVALID_LENGTH; } - OUTB(writearr[0], wbsio_spibase); - OUTB(mode, wbsio_spibase + 1); + OUTB(writearr[0], data->spibase); + OUTB(mode, data->spibase + 1); programmer_delay(10); if (!readcnt) @@ -156,7 +163,7 @@ msg_pspew("%s: returning data =", __func__); for (i = 0; i < readcnt; i++) { - readarr[i] = INB(wbsio_spibase + 4 + i); + readarr[i] = INB(data->spibase + 4 + i); msg_pspew(" 0x%02x", readarr[i]); } msg_pspew("\n"); @@ -170,7 +177,7 @@ return 0; } -static const struct spi_master spi_master_wbsio = { +static struct spi_master spi_master_wbsio = { .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, .command = wbsio_spi_send_command, @@ -180,8 +187,16 @@ .write_aai = spi_chip_write_1, }; +static int wbsio_spi_shutdown(void *data) +{ + free(data); + return 0; +} + int wbsio_check_for_spi(void) { + uint16_t wbsio_spibase = 0; + if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1))) if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT2))) return 1; @@ -191,6 +206,16 @@ msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " "1024 kB!\n", __func__); max_rom_decode.spi = 1024 * 1024; + + struct wbsio_spi_data * data = calloc(1, sizeof(struct wbsio_spi_data)); + if (!data) { + msg_perr("Unable to allocate space for extra SPI master data.\n"); + return SPI_GENERIC_ERROR; + } + data->spibase = wbsio_spibase; + + register_shutdown(wbsio_spi_shutdown, data); + spi_master_wbsio.data = data; register_spi_master(&spi_master_wbsio); return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/47854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic97fa41daf26f27b68ced11ddc2a4da91d18f68e Gerrit-Change-Number: 47854 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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