Change in flashrom[master]: sst49lfxxxc.c: add unlock function for SST chips

[Nikolai Artemiev (Code Review)]

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48108 )

Change subject: sst49lfxxxc.c: add unlock function for SST chips
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sst49lfxxxc.c: add unlock function for SST chips

Function imported from cros flashrom at
`1f38d1ab13d72912fc2d90c7e964dd15e9ec2c9b`

Change-Id: I019bbb622b2348a05e7d03fbd0aa3bfac5f81175
Signed-off-by: Nikolai Artemiev 
---
M chipdrivers.h
M sst49lfxxxc.c
2 files changed, 38 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/48108/1

diff --git a/chipdrivers.h b/chipdrivers.h
index cf03811..82ac3a2 100644
--- a/chipdrivers.h
+++ b/chipdrivers.h
@@ -165,6 +165,7 @@

/* sst49lfxxxc.c */
 int erase_sector_49lfxxxc(struct flashctx *flash, unsigned int address, unsigned int sector_size);
+int unlock_49lfxxxc(struct flashctx *flash);

/* sst_fwhub.c */
 int printlock_sst_fwhub(struct flashctx *flash);
diff --git a/sst49lfxxxc.c b/sst49lfxxxc.c
index a69ab75..9bb4d5d 100644
--- a/sst49lfxxxc.c
+++ b/sst49lfxxxc.c
@@ -18,6 +18,43 @@

#include "flash.h"
 #include "chipdrivers.h"
+#include <inttypes.h>
+
+static int write_lockbits_block_49lfxxxc(struct flashctx *flash, unsigned long address, unsigned char bits)
+{
+	unsigned long lock = flash->virtual_registers + address + 2;
+	msg_cdbg("lockbits at address=0x%08lx is 0x%01x\n", lock, chip_readb(flash, lock));
+	chip_writeb(flash, bits, lock);
+
+	return 0;
+}
+
+static int write_lockbits_49lfxxxc(struct flashctx *flash, unsigned char bits)
+{
+	chipaddr registers = flash->virtual_registers;
+	unsigned int i, left = flash->chip->total_size * 1024;
+	unsigned long address;
+
+	msg_cdbg("\nbios=0x%08" PRIxPTR "\n", registers);
+	for (i = 0; left > 65536; i++, left -= 65536) {
+		write_lockbits_block_49lfxxxc(flash, i * 65536, bits);
+	}
+	address = i * 65536;
+	write_lockbits_block_49lfxxxc(flash, address, bits);
+	address += 32768;
+	write_lockbits_block_49lfxxxc(flash, address, bits);
+	address += 8192;
+	write_lockbits_block_49lfxxxc(flash, address, bits);
+	address += 8192;
+	write_lockbits_block_49lfxxxc(flash, address, bits);
+
+	return 0;
+}
+
+int unlock_49lfxxxc(struct flashctx *flash)
+{
+	return write_lockbits_49lfxxxc(flash, 0);
+}

int erase_sector_49lfxxxc(struct flashctx *flash, unsigned int address,
    		  unsigned int sector_size)

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/48108 )

Change subject: sst49lfxxxc.c: add unlock function for SST chips
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Patch Set 1: Code-Review-1

(1 comment)

https://review.coreboot.org/c/flashrom/+/48108/1/sst49lfxxxc.c 
File sst49lfxxxc.c:

https://review.coreboot.org/c/flashrom/+/48108/1/sst49lfxxxc.c@32 
PS1, Line 32: write_lockbits_49lfxxxc
did this come from?

```
commit 9af0ce8bee6cb0ef2eece004799c184e9df9437d
Author: uwe 
Date:   Mon Jan 22 20:21:17 2007 +0000

Original v2 revision: 2537

Add support for the SST-49LF004C, SST-49LF008C, SST-49LF016C in flashrom.
    Also add suport for NVIDIA MCP55.

Signed-off-by: Yinghai Lu 
    Signed-off-by: Uwe Hermann 
    Acked-by: Peter Stuge

git-svn-id: svn://coreboot.org/flashrom/trunk@85 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
```

&& looks like it was removed in

```
commit ef3ac8ac17eac9d2041ea9c9e711a9b059412b59
Author: Carl-Daniel Hailfinger 
Date:   Sun Aug 3 13:05:34 2014 +0000

Refactor unlocking of many chips with locking at register space address +2

This includes PMC Pm49*, SST 49LF00*, ST M50* and Winbond W39* families.
    The erase and write test status bits of all affected chips have been reset.

Corresponding to flashrom svn r1833.

Signed-off-by: Carl-Daniel Hailfinger 
    Signed-off-by: Stefan Tauner 
    Acked-by: Stefan Tauner 
```

[Nikolai Artemiev (Code Review)]

Nikolai Artemiev has abandoned this change. ( https://review.coreboot.org/c/flashrom/+/48108 )

Change subject: sst49lfxxxc.c: add unlock function for SST chips
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Abandoned