November 2020 - flashrom-gerrit

Change in flashrom[master]: Disable ENE_LPC and MEC1308 on non-x86 arch
by Victor Ding (Code Review) 12 Nov '20

12 Nov '20

Victor Ding has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47394 ) Change subject: Disable ENE_LPC and MEC1308 on non-x86 arch ...................................................................... Disable ENE_LPC and MEC1308 on non-x86 arch Both requires PCI port I/O and hence works only on x86. TEST=builds on Ubuntu for Raspberry Pi Signed-off-by: Victor Ding <victording(a)google.com> Change-Id: I69e1fbd87819b0b6370f31e9ee4c474500fb3759 --- M Makefile 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/47394/1 diff --git a/Makefile b/Makefile index 225db9d..0498624 100644 --- a/Makefile +++ b/Makefile @@ -544,6 +544,16 @@ else override CONFIG_SATAMV = no endif +ifeq ($(CONFIG_ENE_LPC), yes) +UNSUPPORTED_FEATURES += CONFIG_ENE_LPC=yes +else +override CONFIG_ENE_LPC = no +endif +ifeq ($(CONFIG_MEC1308), yes) +UNSUPPORTED_FEATURES += CONFIG_MEC1308=yes +else +override CONFIG_MEC1308 = no +endif endif # Disable all drivers needing raw access (memory, PCI, port I/O) on -- To view, visit https://review.coreboot.org/c/flashrom/+/47394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I69e1fbd87819b0b6370f31e9ee4c474500fb3759 Gerrit-Change-Number: 47394 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Ding <victording(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call
by Nico Huber (Code Review) 10 Nov '20

10 Nov '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40477 ) Change subject: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call ...................................................................... Patch Set 16: (5 comments) > hm... anyone having time to review/merge this? I´d like to get this done... Sorry to let you know after you went through many cycles already, but I think this needs a re-write :-/ There is already everything in place in flashrom to avoid such a layering violation, namely the `.multicommand` member of struct spi_master. The biggest problem with your current implementation is that you assume that there is always a JEDEC flash chip, but that's not generally true. So, the correct way to do this is to implement `.multicommand` instead of `.command`. I would roughly do it as follows: Loop Put write part of command into buffer. If not last command and read part is empty, Continue with next loop iteration. Execute buffer. Execute read part if any. While not last command. https://review.coreboot.org/c/flashrom/+/40477/16//COMMIT_MSG Commit Message: https://review.coreboot.org/c/flashrom/+/40477/16//COMMIT_MSG@25 PS16, Line 25: in a similar way. The infrastructure is already in place. You just have to implement `.multicommand` instead of `.command` for the programmer. https://review.coreboot.org/c/flashrom/+/40477/16/ft2232_spi.c File ft2232_spi.c: https://review.coreboot.org/c/flashrom/+/40477/16/ft2232_spi.c@172 PS16, Line 172: .multicommand = default_spi_send_multicommand, You just need to implement this and will get both commands passed at once. https://review.coreboot.org/c/flashrom/+/40477/16/ft2232_spi.c@497 PS16, Line 497: bufsize = max(writecnt + 19, 261 + 19); This assumes `i` is at most 10. But there is really no guarantee because we could have been called with WREN multiple times (by accident). Easy to fix though, replace the assumed 10 in `writecnt + 19` with `i`: `i + writecnt + 9`. Btw. this `max(..., 261 + 19)` optimization seems insignificant in the presence of USB transfers (which probably have 100 times more overhead than realloc()). I would probably drop it. https://review.coreboot.org/c/flashrom/+/40477/16/ft2232_spi.c@562 PS16, Line 562: if (writearr[0] == JEDEC_WREN) { What if the chip isn't JEDEC? 0x06 (WREN) could mean something very different. This is pretty much a blocker. Especially because the proper infrastructure (.multicommand) is already in place. https://review.coreboot.org/c/flashrom/+/40477/16/ft2232_spi.c@568 PS16, Line 568: } else { To "quote" checkpatch from memory: `else` is not needed after a return. -- To view, visit https://review.coreboot.org/c/flashrom/+/40477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie4a07499ec5ef0af23818593f45dc427285a9e8a Gerrit-Change-Number: 40477 Gerrit-PatchSet: 16 Gerrit-Owner: Simon Buhrow Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 10 Nov 2020 11:51:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call
by Simon Buhrow (Code Review) 10 Nov '20

10 Nov '20

Simon Buhrow has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40477 ) Change subject: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call ...................................................................... Patch Set 16: hm... anyone having time to review/merge this? I´d like to get this done... -- To view, visit https://review.coreboot.org/c/flashrom/+/40477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie4a07499ec5ef0af23818593f45dc427285a9e8a Gerrit-Change-Number: 40477 Gerrit-PatchSet: 16 Gerrit-Owner: Simon Buhrow Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 10 Nov 2020 07:34:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: test patch
by Eizan Miyamoto (Code Review) 10 Nov '20

10 Nov '20

Eizan Miyamoto has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47379 ) Change subject: test patch ...................................................................... test patch Change-Id: I171ecd540524e4f11859b8b95c2e57cc6941bba0 --- M README 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/47379/1 diff --git a/README b/README index 4e7bd4f..9dd92f9 100644 --- a/README +++ b/README @@ -2,6 +2,7 @@ flashrom README ------------------------------------------------------------------------------- + flashrom is a utility for detecting, reading, writing, verifying and erasing flash chips. It is often used to flash BIOS/EFI/coreboot/firmware images in-system using a supported mainboard, but it also supports flashing of network -- To view, visit https://review.coreboot.org/c/flashrom/+/47379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I171ecd540524e4f11859b8b95c2e57cc6941bba0 Gerrit-Change-Number: 47379 Gerrit-PatchSet: 1 Gerrit-Owner: Eizan Miyamoto <eizan(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: programmer.h: Reorder MEC1308 and ENE_LPC enumerators
by Edward O'Callaghan (Code Review) 10 Nov '20

10 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47353 ) Change subject: programmer.h: Reorder MEC1308 and ENE_LPC enumerators ...................................................................... programmer.h: Reorder MEC1308 and ENE_LPC enumerators BUG=b:172668501 TEST=None BRANCH=None Original-Change-Id: I2e9d3df6a6fd6d5d8e3a5a13ee56f5997b10ea52 Original-Signed-off-by: Sam McNally <sammc(a)chromium.org> Change-Id: I8e7a57b7c30e2dd2306d6fe7268eee8bb9d0c8a5 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M programmer.h 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/53/47353/1 diff --git a/programmer.h b/programmer.h index 9a7892d..1bd0d37 100644 --- a/programmer.h +++ b/programmer.h @@ -31,6 +31,9 @@ #if CONFIG_DUMMY == 1 PROGRAMMER_DUMMY, #endif +#if CONFIG_MEC1308 == 1 + PROGRAMMER_MEC1308, +#endif #if CONFIG_NIC3COM == 1 PROGRAMMER_NIC3COM, #endif @@ -61,9 +64,6 @@ #if CONFIG_ATAPROMISE == 1 PROGRAMMER_ATAPROMISE, #endif -#if CONFIG_ENE_LPC == 1 - PROGRAMMER_ENE_LPC, -#endif #if CONFIG_IT8212 == 1 PROGRAMMER_IT8212, #endif @@ -82,6 +82,9 @@ #if CONFIG_DEVELOPERBOX_SPI == 1 PROGRAMMER_DEVELOPERBOX_SPI, #endif +#if CONFIG_ENE_LPC == 1 + PROGRAMMER_ENE_LPC, +#endif #if CONFIG_RAYER_SPI == 1 PROGRAMMER_RAYER_SPI, #endif @@ -112,9 +115,6 @@ #if CONFIG_USBBLASTER_SPI == 1 PROGRAMMER_USBBLASTER_SPI, #endif -#if CONFIG_MEC1308 == 1 - PROGRAMMER_MEC1308, -#endif #if CONFIG_MSTARDDC_SPI == 1 PROGRAMMER_MSTARDDC_SPI, #endif -- To view, visit https://review.coreboot.org/c/flashrom/+/47353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8e7a57b7c30e2dd2306d6fe7268eee8bb9d0c8a5 Gerrit-Change-Number: 47353 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: test_build.sh: Move build test procedure to repository
by Patrick Georgi (Code Review) 03 Nov '20

03 Nov '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46894 ) Change subject: test_build.sh: Move build test procedure to repository ...................................................................... test_build.sh: Move build test procedure to repository Instead of hard coding the test procedure on qa.coreboot.org, allow running a script in the repo instead. The server is already adapted to do that, so once there's a test_build.sh file in the toplevel directory, it's run in place of the default operation. The content of this change mirrors the default operation exactly so should serve as a good starting point. The script is executed in an encapsulate[0] context with the workspace, /tmp and $HOME/.ccache writable, everything else read-only and network disabled. It should return 0 on success, anything else on failure, as is normal for UNIX processes. [0] https://review.coreboot.org/cgit/encapsulate.git Change-Id: I37a8e925d1b283c3b8f87cb3d0f1ed8920f2cf95 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- A test_build.sh 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/46894/1 diff --git a/test_build.sh b/test_build.sh new file mode 100755 index 0000000..0e7f37a --- /dev/null +++ b/test_build.sh @@ -0,0 +1,8 @@ +#!/bin/sh +set -e + +make CONFIG_EVERYTHING=yes WARNERROR=yes + +meson -p out +(cd out && ninja) +(cd out && ninja test) -- To view, visit https://review.coreboot.org/c/flashrom/+/46894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I37a8e925d1b283c3b8f87cb3d0f1ed8920f2cf95 Gerrit-Change-Number: 46894 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: chipset_enable.c: Add all the lakes support
by Edward O'Callaghan (Code Review) 02 Nov '20

02 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47092 ) Change subject: chipset_enable.c: Add all the lakes support ...................................................................... chipset_enable.c: Add all the lakes support Pulled out of ChromiumOS tree. - pid=0x02a4 -> "Cometlake" - pid=0x34a4 -> "Icelake" - pid=0x4da4 -> "Jasperlake" - pid=0x51a4 -> "Alderlake-P" - pid=0x7aa4 -> "Alderlake-S" - pid=0x9d24 -> "Skylake" - pid=0x9da4 -> "Cannonlake" - pid=0xa0a4 -> "Tigerlake" BUG=b:XXX BRANCH=none TEST=none Change-Id: I403b11bbfc698e593fedd272921ade2bf8b3c2ca Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M chipset_enable.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/92/47092/1 diff --git a/chipset_enable.c b/chipset_enable.c index 01d0291..3312483 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1815,6 +1815,7 @@ {0x1166, 0x0200, B_P, OK, "Broadcom", "OSB4", enable_flash_osb4}, {0x1166, 0x0205, B_PFL, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, {0x17f3, 0x6030, B_PFL, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610}, + {0x8086, 0x02a4, B_FS, OK, "Intel", "Cometlake", enable_flash_pch100}, {0x8086, 0x0c60, B_FS, NT, "Intel", "S12x0", enable_flash_s12x0}, {0x8086, 0x0f1c, B_FS, OK, "Intel", "Bay Trail", enable_flash_silvermont}, {0x8086, 0x0f1d, B_FS, NT, "Intel", "Bay Trail", enable_flash_silvermont}, @@ -1897,6 +1898,7 @@ {0x8086, 0x2918, B_FS, DEP, "Intel", "ICH9", enable_flash_ich9}, {0x8086, 0x2919, B_FS, DEP, "Intel", "ICH9M", enable_flash_ich9}, {0x8086, 0x31f0, B_FS, OK, "Intel", "Geminilake", enable_flash_apl}, + {0x8086, 0x34a4, B_FS, OK, "Intel", "Icelake", enable_flash_pch100}, {0x8086, 0x3a10, B_FS, NT, "Intel", "ICH10R Eng. Sample", enable_flash_ich10}, {0x8086, 0x3a14, B_FS, DEP, "Intel", "ICH10DO", enable_flash_ich10}, {0x8086, 0x3a16, B_FS, DEP, "Intel", "ICH10R", enable_flash_ich10}, @@ -1920,11 +1922,14 @@ {0x8086, 0x3b14, B_FS, DEP, "Intel", "3420", enable_flash_pch5}, {0x8086, 0x3b16, B_FS, NT, "Intel", "3450", enable_flash_pch5}, {0x8086, 0x3b1e, B_FS, NT, "Intel", "B55", enable_flash_pch5}, + {0x8086, 0x4da4, B_FS, OK, "Intel", "Jasperlake", enable_flash_pch100}, {0x8086, 0x5031, B_FS, OK, "Intel", "EP80579", enable_flash_ich7}, + {0x8086, 0x51a4, B_FS, OK, "Intel", "Alderlake-P", enable_flash_pch100}, {0x8086, 0x5af0, B_FS, OK, "Intel", "Apollolake", enable_flash_apl}, {0x8086, 0x7000, B_P, OK, "Intel", "PIIX3", enable_flash_piix4}, {0x8086, 0x7110, B_P, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, {0x8086, 0x7198, B_P, OK, "Intel", "440MX", enable_flash_piix4}, + {0x8086, 0x7aa4, B_FS, OK, "Intel", "Alderlake-S", enable_flash_pch100}, {0x8086, 0x8119, B_FL, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo}, {0x8086, 0x8186, B_FS, OK, "Intel", "Atom E6xx(T) (Tunnel Creek)", enable_flash_tunnelcreek}, {0x8086, 0x8c40, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, @@ -2008,6 +2013,7 @@ {0x8086, 0x9cc7, B_FS, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp}, {0x8086, 0x9cc9, B_FS, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp}, {0x8086, 0x9ccb, B_FS, NT, "Intel", "Broadwell H", enable_flash_pch9}, + {0x8086, 0x9d24, B_FS, OK, "Intel", "Skylake", enable_flash_pch100}, {0x8086, 0x9d41, B_S, NT, "Intel", "Skylake / Kaby Lake Sample", enable_flash_pch100}, {0x8086, 0x9d43, B_S, NT, "Intel", "Skylake U Base", enable_flash_pch100}, {0x8086, 0x9d46, B_S, NT, "Intel", "Skylake Y Premium", enable_flash_pch100}, @@ -2020,7 +2026,9 @@ {0x8086, 0x9d56, B_S, NT, "Intel", "Kaby Lake Y Premium", enable_flash_pch100}, {0x8086, 0x9d58, B_S, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100}, {0x8086, 0x9d84, B_S, DEP, "Intel", "Cannon Lake U Premium", enable_flash_pch300}, + {0x8086, 0x9da4, B_FS, OK, "Intel", "Cannonlake", enable_flash_pch100}, {0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400}, + {0x8086, 0xa0a4, B_FS, OK, "Intel", "Tigerlake", enable_flash_pch100}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, {0x8086, 0xa143, B_S, NT, "Intel", "H110", enable_flash_pch100}, @@ -2055,6 +2063,7 @@ {0x8086, 0xa1cb, B_S, NT, "Intel", "C621A Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1cc, B_S, NT, "Intel", "C627A Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1cd, B_S, NT, "Intel", "C629A Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa224, B_FS, OK, "Intel", "Lewisburg", enable_flash_pch100}, {0x8086, 0xa240, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa241, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa242, B_S, NT, "Intel", "C624 Series Chipset Supersku", enable_flash_c620}, @@ -2085,6 +2094,7 @@ {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300}, {0x8086, 0xa30e, B_S, DEP, "Intel", "CM246", enable_flash_pch300}, {0x8086, 0x3482, B_S, DEP, "Intel", "Ice Lake U Premium", enable_flash_pch300}, + {0x8086, 0xa0a4, B_FS, OK, "Intel", "Tigerlake", enable_flash_pch100}, #endif {0}, }; -- To view, visit https://review.coreboot.org/c/flashrom/+/47092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I403b11bbfc698e593fedd272921ade2bf8b3c2ca Gerrit-Change-Number: 47092 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: fmap: Bring in CrOS get_fmap_entries() verbatim
by Edward O'Callaghan (Code Review) 01 Nov '20

01 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47063 ) Change subject: fmap: Bring in CrOS get_fmap_entries() verbatim ...................................................................... fmap: Bring in CrOS get_fmap_entries() verbatim Change-Id: I0b2372e3473939064515f698b23ad4c0048bb408 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M fmap.c M fmap.h 2 files changed, 314 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/63/47063/1 diff --git a/fmap.c b/fmap.c index 2f34a5c..b3d8542 100644 --- a/fmap.c +++ b/fmap.c @@ -38,8 +38,15 @@ #include <stdlib.h> #include <string.h> #include <sys/types.h> +#include <arpa/inet.h> + #include "flash.h" #include "fmap.h" +#include "layout.h" +#include "search.h" + +#define ACPI_FMAP_PATH "/sys/devices/platform/chromeos_acpi/FMAP" +#define FDT_FMAP_PATH "/proc/device-tree/firmware/chromeos/fmap-offset" static size_t fmap_size(const struct fmap *fmap) { @@ -146,6 +153,14 @@ return 0; } +int fmap_find(struct fmap *fmap) +{ + if (!is_valid_fmap(fmap)) + return 0; + + return fmap_size(fmap); +} + static int fmap_lsearch_rom(struct fmap **fmap_out, struct flashctx *const flashctx, size_t rom_offset, size_t len) { @@ -329,3 +344,301 @@ return ret; } + +/* Read value from ACPI in sysfs, if it exists. */ +__attribute__((unused)) static int read_fmap_base_acpi(uint32_t *out) +{ + int rv = 0; + FILE *f; + + if (!(f = fopen(ACPI_FMAP_PATH, "r"))) + return -1; + + /* FMAP base is an ASCII signed integer. */ + if (fscanf(f, "%d", (int *)out) != 1) + rv = -1; + + fclose(f); + + if (rv) + msg_gdbg("%s: failed to read fmap_base from ACPI\n", __func__); + else + msg_gdbg("%s: read fmap_base from ACPI\n", __func__); + + return rv; +} + +/* Read value from FDT, if it exists. */ +__attribute__((unused)) static int read_fmap_base_fdt(uint32_t *out) +{ + int rv = 0; + uint32_t data; + FILE *f; + + if (!(f = fopen(FDT_FMAP_PATH, "r"))) + return -1; + + /* Value is stored as network-byte order dword. */ + if (fread(&data, sizeof(data), 1, f) != 1) + rv = -1; + else + *out = ntohl(data); + + fclose(f); + + if (rv) + msg_gdbg("%s: failed to read fmap_base from FDT\n", __func__); + else + msg_gdbg("%s: read fmap_base from FDT\n", __func__); + + return rv; +} + +/* + * Find the FMAP base from ACPI or FDT. + * @search: Search information + * @offset: Place to put offset + * @return 0 if offset found, -1 if not + */ +static int get_fmap_base(struct search_info *search, off_t *offset) +{ + uint32_t fmap_base; + uint32_t from_top; + +#if IS_X86 + if (read_fmap_base_acpi(&fmap_base) < 0) + return -1; +#elif IS_ARM + if (read_fmap_base_fdt(&fmap_base) < 0) + return -1; +#else + return -1; +#endif + + /* + * TODO(b/158017386): see if we can remove this hack. It may + * only apply to older platforms which are now AUE. + * + * There are 2 kinds of fmap_base. + * + * 1. Shadow ROM/BIOS area (x86), such as 0xFFxxxxxx. + * 2. Offset to start of flash, such as 0x00xxxxxx. + * + * The shadow ROM is a cached copy of the BIOS ROM which resides below + * 4GB host/CPU memory address space on x86. The top of BIOS address + * aligns to the last byte of address space, 0xFFFFFFFF. So to obtain + * the ROM offset when shadow ROM is used, we subtract the fmap_base + * from 4G minus 1. + * + * CPU address flash address + * space p space + * 0xFFFFFFFF +-------+ --- +-------+ 0x400000 + * | | ^ | | ^ + * | 4MB | | | | | from_top + * | | v | | v + * fmap_base--> | -fmap | ------|--fmap-|-- the offset we need. + * ^ | | | | + * | +-------+-------+-------+ 0x000000 + * | | | + * | | | + * | | | + * | | | + * 0x00000000 +-------+ + * + * We'll use bit 31 to determine if the shadow BIOS area is being used. + * This is sort of a hack, but allows us to perform sanity checking for + * older x86-based Chrome OS platforms. + */ + + msg_gdbg("%s: fmap_base: %#x, ROM size: 0x%zx\n", + __func__, fmap_base, search->total_size); + + if (fmap_base & (1 << 31)) { + from_top = 0xFFFFFFFF - fmap_base + 1; + msg_gdbg("%s: fmap is located in shadow ROM, from_top: %#x\n", + __func__, from_top); + if (from_top > search->total_size) + return -1; + *offset = search->total_size - from_top; + } else { + msg_gdbg("%s: fmap is located in physical ROM\n", __func__); + if (fmap_base > search->total_size) + return -1; + *offset = fmap_base; + } + + msg_gdbg("%s: ROM offset: %#jx\n", __func__, (intmax_t)*offset); + return 0; +} + +static int add_fmap_entries_from_buf(const uint8_t *buf) +{ + struct fmap *fmap; + int i; + struct flashrom_layout *const layout = get_global_layout(); + + fmap = (struct fmap *)(buf); + + for (i = 0; i < fmap->nareas; i++) { + if (layout->num_entries >= MAX_ROMLAYOUT) { + msg_gerr("ROM image contains too many regions\n"); + return -1; + } + layout->entries[layout->num_entries].start = fmap->areas[i].offset; + + /* + * Flashrom rom entries use absolute addresses. So for non-zero + * length entries, we need to subtract 1 from offset + size to + * determine the end address. + */ + layout->entries[layout->num_entries].end = fmap->areas[i].offset + + fmap->areas[i].size; + if (fmap->areas[i].size) + layout->entries[layout->num_entries].end--; + + size_t name_len = sizeof(fmap->areas[i].name); + layout->entries[layout->num_entries].name = calloc(1, name_len); + memcpy(layout->entries[layout->num_entries].name, fmap->areas[i].name, name_len); + + layout->entries[layout->num_entries].included = 0; + strcpy(layout->entries[layout->num_entries].file, ""); + + msg_gdbg("added fmap region \"%s\" (file=\"%s\") as %sincluded," + " start: 0x%08x, end: 0x%08x\n", + layout->entries[layout->num_entries].name, + layout->entries[layout->num_entries].file, + layout->entries[layout->num_entries].included ? "" : "not ", + layout->entries[layout->num_entries].start, + layout->entries[layout->num_entries].end); + layout->num_entries++; + } + + return layout->num_entries; +} + +enum found_t { + FOUND_NONE, + FOUND_FMAP, +}; + +/* returns the number of entries added, or <0 to indicate error */ +static int add_fmap_entries(void *source_handle, + size_t image_size, + int (*read_chunk)(void *handle, + void *dest, + size_t offset, + size_t size)) +{ + static enum found_t found = FOUND_NONE; + struct search_info search; + struct fmap fmap_header; + uint8_t *buf = NULL; + off_t offset; + struct flashrom_layout *const layout = get_global_layout(); + + if (found != FOUND_NONE) { + msg_gdbg("Already found fmap entries, not searching again.\n"); + return 0; + } + + search_init(&search, source_handle, + image_size, sizeof(fmap_header), read_chunk); + search.handler = get_fmap_base; + while (found == FOUND_NONE && !search_find_next(&search, &offset)) { + if (search.image) { + memcpy(&fmap_header, search.image + offset, + sizeof(fmap_header)); + } else if (read_chunk(source_handle, (uint8_t *)&fmap_header, + offset, sizeof(fmap_header))) { + msg_gdbg("[L%d] failed to read flash at offset %#jx\n", + __LINE__, (intmax_t)offset); + return -1; + } + int buf_size = fmap_find(&fmap_header); + if (buf_size == 0) + continue; + buf = calloc(1, buf_size); + + if (read_chunk(source_handle, buf, offset, buf_size)) { + msg_gdbg("[L%d] failed to read %d bytes at offset 0x%lx\n", + __LINE__, buf_size, (unsigned long)offset); + return -1; + } else { + found = FOUND_FMAP; + } + } + + switch (found) { + case FOUND_FMAP: + layout->num_entries = add_fmap_entries_from_buf(buf); + break; + default: + msg_gdbg("%s: no fmap present\n", __func__); + } + if (buf) + free(buf); + search_free(&search); + + return layout->num_entries; +} + +/* + * read_chunk() callback used when reading contents from a file. + */ +static int read_from_file(void *fhandle, + void *dest, + size_t offset, + size_t size) +{ + FILE *handle = fhandle; + + if (fseek(handle, offset, SEEK_SET)) { + msg_cerr("%s failed to seek to position %zd\n", + __func__, offset); + return 1; + } + + if (fread(dest, 1, size, handle) != size) { + msg_cerr("%s failed to read %zd bytes\n", + __func__, offset); + return 1; + } + + return 0; +} + +/* + * read_chunk() callback used when reading contents from the flash device. + */ +static int read_from_flash(void *handle, + void *dest, + size_t offset, + size_t size) +{ + struct flashctx *flash = handle; + + return read_flash(flash, dest, offset, size); +} + +int get_fmap_entries(const char *filename, struct flashctx *flash) +{ + int rv; + size_t image_size = flash->chip->total_size * 1024; + + /* Let's try retrieving entries from file. */ + if (filename) { + FILE *handle; + + handle = fopen(filename, "r"); + if (handle) { + rv = add_fmap_entries(handle, + image_size, read_from_file); + fclose(handle); + if (rv > 0) + return rv; + msg_cerr("No fmap entries found in %s\n", filename); + } + } + + return add_fmap_entries(flash, image_size, read_from_flash); +} diff --git a/fmap.h b/fmap.h index 924e11f..840de3d 100644 --- a/fmap.h +++ b/fmap.h @@ -67,5 +67,6 @@ int fmap_read_from_buffer(struct fmap **fmap_out, const uint8_t *buf, size_t len); int fmap_read_from_rom(struct fmap **fmap_out, struct flashctx *const flashctx, size_t rom_offset, size_t len); +int get_fmap_entries(const char *filename, struct flashctx *flash); #endif /* __FMAP_H__*/ -- To view, visit https://review.coreboot.org/c/flashrom/+/47063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0b2372e3473939064515f698b23ad4c0048bb408 Gerrit-Change-Number: 47063 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in flashrom[master]: fmap.c: inline fmap_find()
by Edward O'Callaghan (Code Review) 01 Nov '20

01 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47064 ) Change subject: fmap.c: inline fmap_find() ...................................................................... fmap.c: inline fmap_find() Change-Id: I2925cf62465ea35faf76b8d570eb886091250c07 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M fmap.c 1 file changed, 2 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/47064/1 diff --git a/fmap.c b/fmap.c index b3d8542..8155aa3 100644 --- a/fmap.c +++ b/fmap.c @@ -153,14 +153,6 @@ return 0; } -int fmap_find(struct fmap *fmap) -{ - if (!is_valid_fmap(fmap)) - return 0; - - return fmap_size(fmap); -} - static int fmap_lsearch_rom(struct fmap **fmap_out, struct flashctx *const flashctx, size_t rom_offset, size_t len) { @@ -554,9 +546,9 @@ __LINE__, (intmax_t)offset); return -1; } - int buf_size = fmap_find(&fmap_header); - if (buf_size == 0) + if (!is_valid_fmap(&fmap_header)) continue; + int buf_size = fmap_size(&fmap_header); buf = calloc(1, buf_size); if (read_chunk(source_handle, buf, offset, buf_size)) { -- To view, visit https://review.coreboot.org/c/flashrom/+/47064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2925cf62465ea35faf76b8d570eb886091250c07 Gerrit-Change-Number: 47064 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in flashrom[master]: fmap.c: Port to upstream
by Edward O'Callaghan (Code Review) 01 Nov '20

01 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47065 ) Change subject: fmap.c: Port to upstream ...................................................................... fmap.c: Port to upstream Change-Id: I489761f531c3a44978f6450cdd0f1ff991f13d87 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M fmap.c M layout.h 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/65/47065/1 diff --git a/fmap.c b/fmap.c index 8155aa3..fb6e0d3 100644 --- a/fmap.c +++ b/fmap.c @@ -609,7 +609,7 @@ { struct flashctx *flash = handle; - return read_flash(flash, dest, offset, size); + return flash->chip->read(flash, dest, offset, size); } int get_fmap_entries(const char *filename, struct flashctx *flash) diff --git a/layout.h b/layout.h index 8e4eb13..b32d0ca 100644 --- a/layout.h +++ b/layout.h @@ -40,6 +40,7 @@ chipoff_t end; bool included; char *name; + char file[256]; /* file[0]=='\0' means not specified. */ }; struct flashrom_layout { -- To view, visit https://review.coreboot.org/c/flashrom/+/47065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I489761f531c3a44978f6450cdd0f1ff991f13d87 Gerrit-Change-Number: 47065 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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flashrom-gerrit November 2020