November 2020 - flashrom-gerrit

Change in flashrom[master]: wbsio_spi.c: Move singleton state into spi master state tracker
by Edward O'Callaghan (Code Review) 23 Nov '20

23 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47854 ) Change subject: wbsio_spi.c: Move singleton state into spi master state tracker ...................................................................... wbsio_spi.c: Move singleton state into spi master state tracker Make use of the reneterent framework by moving singleton static state out of the global life-time and into a per-spi_master basis. This allows for the it87spi master to be reneterent and its internal state's life-time to be correctly handled by Flashrom's core dispatch logic. BUG=none TEST=builds Change-Id: Ic97fa41daf26f27b68ced11ddc2a4da91d18f68e Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M wbsio_spi.c 1 file changed, 37 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/47854/1 diff --git a/wbsio_spi.c b/wbsio_spi.c index 26e3bb9..632ff72 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -16,6 +16,8 @@ #if defined(__i386__) || defined(__x86_64__) +#include <stdlib.h> + #include "flash.h" #include "chipdrivers.h" #include "programmer.h" @@ -25,7 +27,9 @@ #define WBSIO_PORT1 0x2e #define WBSIO_PORT2 0x4e -static uint16_t wbsio_spibase = 0; +struct wbsio_spi_data { + uint16_t spibase; +}; static uint16_t wbsio_get_spibase(uint16_t port) { @@ -87,10 +91,13 @@ msg_pspew("%s:", __func__); + const struct wbsio_spi_data *data = + (const struct wbsio_spi_data *)flash->mst->spi.data; + if (1 == writecnt && 0 == readcnt) { mode = 0x10; } else if (2 == writecnt && 0 == readcnt) { - OUTB(writearr[1], wbsio_spibase + 4); + OUTB(writearr[1], data->spibase + 4); msg_pspew(" data=0x%02x", writearr[1]); mode = 0x20; } else if (1 == writecnt && 2 == readcnt) { @@ -98,28 +105,28 @@ } else if (4 == writecnt && 0 == readcnt) { msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); for (i = 2; i < writecnt; i++) { - OUTB(writearr[i], wbsio_spibase + i); + OUTB(writearr[i], data->spibase + i); msg_pspew("%02x", writearr[i]); } mode = 0x40 | (writearr[1] & 0x0f); } else if (5 == writecnt && 0 == readcnt) { msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); for (i = 2; i < 4; i++) { - OUTB(writearr[i], wbsio_spibase + i); + OUTB(writearr[i], data->spibase + i); msg_pspew("%02x", writearr[i]); } - OUTB(writearr[i], wbsio_spibase + i); + OUTB(writearr[i], data->spibase + i); msg_pspew(" data=0x%02x", writearr[i]); mode = 0x50 | (writearr[1] & 0x0f); } else if (8 == writecnt && 0 == readcnt) { msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); for (i = 2; i < 4; i++) { - OUTB(writearr[i], wbsio_spibase + i); + OUTB(writearr[i], data->spibase + i); msg_pspew("%02x", writearr[i]); } msg_pspew(" data=0x"); for (; i < writecnt; i++) { - OUTB(writearr[i], wbsio_spibase + i); + OUTB(writearr[i], data->spibase + i); msg_pspew("%02x", writearr[i]); } mode = 0x60 | (writearr[1] & 0x0f); @@ -133,7 +140,7 @@ } else if (4 == writecnt && readcnt >= 1 && readcnt <= 4) { msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); for (i = 2; i < writecnt; i++) { - OUTB(writearr[i], wbsio_spibase + i); + OUTB(writearr[i], data->spibase + i); msg_pspew("%02x", writearr[i]); } mode = ((7 + readcnt) << 4) | (writearr[1] & 0x0f); @@ -147,8 +154,8 @@ return SPI_INVALID_LENGTH; } - OUTB(writearr[0], wbsio_spibase); - OUTB(mode, wbsio_spibase + 1); + OUTB(writearr[0], data->spibase); + OUTB(mode, data->spibase + 1); programmer_delay(10); if (!readcnt) @@ -156,7 +163,7 @@ msg_pspew("%s: returning data =", __func__); for (i = 0; i < readcnt; i++) { - readarr[i] = INB(wbsio_spibase + 4 + i); + readarr[i] = INB(data->spibase + 4 + i); msg_pspew(" 0x%02x", readarr[i]); } msg_pspew("\n"); @@ -170,7 +177,7 @@ return 0; } -static const struct spi_master spi_master_wbsio = { +static struct spi_master spi_master_wbsio = { .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, .command = wbsio_spi_send_command, @@ -180,8 +187,16 @@ .write_aai = spi_chip_write_1, }; +static int wbsio_spi_shutdown(void *data) +{ + free(data); + return 0; +} + int wbsio_check_for_spi(void) { + uint16_t wbsio_spibase = 0; + if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1))) if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT2))) return 1; @@ -191,6 +206,16 @@ msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " "1024 kB!\n", __func__); max_rom_decode.spi = 1024 * 1024; + + struct wbsio_spi_data * data = calloc(1, sizeof(struct wbsio_spi_data)); + if (!data) { + msg_perr("Unable to allocate space for extra SPI master data.\n"); + return SPI_GENERIC_ERROR; + } + data->spibase = wbsio_spibase; + + register_shutdown(wbsio_spi_shutdown, data); + spi_master_wbsio.data = data; register_spi_master(&spi_master_wbsio); return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/47854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic97fa41daf26f27b68ced11ddc2a4da91d18f68e Gerrit-Change-Number: 47854 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 3

Change in flashrom[master]: wbsio_spi.c: Reorder functions with primitives at the top
by Edward O'Callaghan (Code Review) 23 Nov '20

23 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47853 ) Change subject: wbsio_spi.c: Reorder functions with primitives at the top ...................................................................... wbsio_spi.c: Reorder functions with primitives at the top Reshuffle file with no semantic changes, this avoids unnecessary prototypes for static member functions as to pave the way for further cleanups as well as an easier to parse implementation. BUG=none TEST=builds Change-Id: Iae9426b6a8ba6a824f7d7e9aaf9f8174b044d04c Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M wbsio_spi.c 1 file changed, 27 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/53/47853/1 diff --git a/wbsio_spi.c b/wbsio_spi.c index 1674825..26e3bb9 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -57,39 +57,6 @@ return flashport; } -static int wbsio_spi_send_command(const struct flashctx *flash, unsigned int writecnt, - unsigned int readcnt, - const unsigned char *writearr, - unsigned char *readarr); -static int wbsio_spi_read(struct flashctx *flash, uint8_t *buf, - unsigned int start, unsigned int len); - -static const struct spi_master spi_master_wbsio = { - .max_data_read = MAX_DATA_UNSPECIFIED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .command = wbsio_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = wbsio_spi_read, - .write_256 = spi_chip_write_1, - .write_aai = spi_chip_write_1, -}; - -int wbsio_check_for_spi(void) -{ - if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1))) - if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT2))) - return 1; - - msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); - - msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " - "1024 kB!\n", __func__); - max_rom_decode.spi = 1024 * 1024; - register_spi_master(&spi_master_wbsio); - - return 0; -} - /* W83627DHG has 11 command modes: * 1=1 command only * 2=1 command+1 data write @@ -203,4 +170,30 @@ return 0; } -#endif +static const struct spi_master spi_master_wbsio = { + .max_data_read = MAX_DATA_UNSPECIFIED, + .max_data_write = MAX_DATA_UNSPECIFIED, + .command = wbsio_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = wbsio_spi_read, + .write_256 = spi_chip_write_1, + .write_aai = spi_chip_write_1, +}; + +int wbsio_check_for_spi(void) +{ + if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1))) + if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT2))) + return 1; + + msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); + + msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " + "1024 kB!\n", __func__); + max_rom_decode.spi = 1024 * 1024; + register_spi_master(&spi_master_wbsio); + + return 0; +} + +#endif /* defined(__i386__) || defined(__x86_64__) */ -- To view, visit https://review.coreboot.org/c/flashrom/+/47853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iae9426b6a8ba6a824f7d7e9aaf9f8174b044d04c Gerrit-Change-Number: 47853 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 2

Change in flashrom[master]: cli_classic.c: Add runtime measurement
by Simon Buhrow (Code Review) 23 Nov '20

23 Nov '20

Simon Buhrow has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47805 ) Change subject: cli_classic.c: Add runtime measurement ...................................................................... cli_classic.c: Add runtime measurement To get an fast and easy feedback on how parameters effect runtime (e.g. clock setting, polling delays, ...). Signed-off-by: Simon Buhrow <simon.buhrow(a)posteo.de> Change-Id: I2238b3f3e6c2ab7745994662a88787fa2e86d480 --- M cli_classic.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/05/47805/1 diff --git a/cli_classic.c b/cli_classic.c index ae7f6ef..0d5381f 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -24,6 +24,7 @@ #include <string.h> #include <stdlib.h> #include <getopt.h> +#include <time.h> #include "flash.h" #include "flashchips.h" #include "fmap.h" @@ -142,6 +143,7 @@ /* Probe for up to eight flash chips. */ struct flashctx flashes[8] = {{0}}; struct flashctx *fill_flash; + struct timespec time_start, time_end; const char *name; int namelen, opt, i, j; int startchip = -1, chipcount = 0, option_index = 0, force = 0, ifd = 0, fmap = 0; @@ -528,6 +530,8 @@ /* FIXME: Delay calibration should happen in programmer code. */ myusec_calibrate_delay(); + timespec_get(&time_start, TIME_UTC); + if (programmer_init(prog, pparam)) { msg_perr("Error: Programmer initialization failed.\n"); ret = 1; @@ -806,6 +810,9 @@ for (i = 0; i < chipcount; i++) free(flashes[i].chip); + timespec_get(&time_end, TIME_UTC); + msg_gdbg("Runtime: %d:%2d min:s\n", (int)((time_end.tv_sec-time_start.tv_sec) / 60), (int)(time_end.tv_sec-time_start.tv_sec) % 60); + layout_cleanup(&include_args); free(filename); free(fmapfile); -- To view, visit https://review.coreboot.org/c/flashrom/+/47805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2238b3f3e6c2ab7745994662a88787fa2e86d480 Gerrit-Change-Number: 47805 Gerrit-PatchSet: 1 Gerrit-Owner: Simon Buhrow Gerrit-MessageType: newchange

3 5

Change in flashrom[master]: sb600spi.c: Reorder functions with primitives at the top
by Edward O'Callaghan (Code Review) 22 Nov '20

22 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47665 ) Change subject: sb600spi.c: Reorder functions with primitives at the top ...................................................................... sb600spi.c: Reorder functions with primitives at the top Reshuffle file with no semantic changes, this avoids unnecessary prototypes for static member functions as to be an easier implementation to parse. BUG=none TEST=builds Change-Id: If3970d850989eafc59cec9158ecfcdafc7a8caea Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M sb600spi.c 1 file changed, 20 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/65/47665/1 diff --git a/sb600spi.c b/sb600spi.c index 5892d57..8eaf41f 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -56,31 +56,6 @@ #define FIFO_SIZE_OLD 8 #define FIFO_SIZE_YANGTZE 71 -static int sb600_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -static int spi100_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); - -static struct spi_master spi_master_sb600 = { - .max_data_read = FIFO_SIZE_OLD, - .max_data_write = FIFO_SIZE_OLD - 3, - .command = sb600_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, -}; - -static struct spi_master spi_master_yangtze = { - .max_data_read = FIFO_SIZE_YANGTZE - 3, /* Apparently the big SPI 100 buffer is not a ring buffer. */ - .max_data_write = FIFO_SIZE_YANGTZE - 3, - .command = spi100_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, -}; - static int find_smbus_dev_rev(uint16_t vendor, uint16_t device) { struct pci_dev *smbus_dev = pci_dev_find(vendor, device); @@ -570,6 +545,26 @@ return amd_imc_shutdown(dev); } +static struct spi_master spi_master_sb600 = { + .max_data_read = FIFO_SIZE_OLD, + .max_data_write = FIFO_SIZE_OLD - 3, + .command = sb600_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, +}; + +static struct spi_master spi_master_yangtze = { + .max_data_read = FIFO_SIZE_YANGTZE - 3, /* Apparently the big SPI 100 buffer is not a ring buffer. */ + .max_data_write = FIFO_SIZE_YANGTZE - 3, + .command = spi100_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, +}; + int sb600_probe_spi(struct pci_dev *dev) { struct pci_dev *smbus_dev; -- To view, visit https://review.coreboot.org/c/flashrom/+/47665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If3970d850989eafc59cec9158ecfcdafc7a8caea Gerrit-Change-Number: 47665 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 2

Change in flashrom[master]: bitbang_spi.c: Reorder functions with primitives at the top
by Edward O'Callaghan (Code Review) 22 Nov '20

22 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47664 ) Change subject: bitbang_spi.c: Reorder functions with primitives at the top ...................................................................... bitbang_spi.c: Reorder functions with primitives at the top Reshuffle file with no semantic changes, this avoids unnecessary prototypes for static member functions as to be an easier implementation to parse. BUG=none TEST=builds Change-Id: Ided41c6c64376e0cddeb17b936773a86c36d5f72 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M bitbang_spi.c 1 file changed, 46 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/47664/1 diff --git a/bitbang_spi.c b/bitbang_spi.c index ac50e67..c402119 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -64,57 +64,6 @@ return master->get_miso(); } -static int bitbang_spi_send_command(const struct flashctx *flash, - unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, - unsigned char *readarr); - -static const struct spi_master spi_master_bitbang = { - .features = SPI_MASTER_4BA, - .max_data_read = MAX_DATA_READ_UNLIMITED, - .max_data_write = MAX_DATA_WRITE_UNLIMITED, - .command = bitbang_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, -}; - -#if 0 // until it is needed -static int bitbang_spi_shutdown(const struct bitbang_spi_master *master) -{ - /* FIXME: Run bitbang_spi_release_bus here or per command? */ - return 0; -} -#endif - -int register_spi_bitbang_master(const struct bitbang_spi_master *master) -{ - struct spi_master mst = spi_master_bitbang; - /* If someone forgot to initialize a bitbang function, we catch it here. */ - if (!master || !master->set_cs || - !master->set_sck || !master->set_mosi || !master->get_miso || - (master->request_bus && !master->release_bus) || - (!master->request_bus && master->release_bus)) { - msg_perr("Incomplete SPI bitbang master setting!\n" - "Please report a bug at flashrom(a)flashrom.org\n"); - return ERROR_FLASHROM_BUG; - } - - mst.data = master; - register_spi_master(&mst); - - /* Only mess with the bus if we're sure nobody else uses it. */ - bitbang_spi_request_bus(master); - bitbang_spi_set_cs(master, 1); - bitbang_spi_set_sck_set_mosi(master, 0, 0); - /* FIXME: Release SPI bus here and request it again for each command or - * don't release it now and only release it on programmer shutdown? - */ - bitbang_spi_release_bus(master); - return 0; -} - static uint8_t bitbang_spi_read_byte(const struct bitbang_spi_master *master) { uint8_t ret = 0; @@ -173,3 +122,49 @@ return 0; } + +static const struct spi_master spi_master_bitbang = { + .features = SPI_MASTER_4BA, + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, + .command = bitbang_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, +}; + +#if 0 // until it is needed +static int bitbang_spi_shutdown(const struct bitbang_spi_master *master) +{ + /* FIXME: Run bitbang_spi_release_bus here or per command? */ + return 0; +} +#endif + +int register_spi_bitbang_master(const struct bitbang_spi_master *master) +{ + struct spi_master mst = spi_master_bitbang; + /* If someone forgot to initialize a bitbang function, we catch it here. */ + if (!master || !master->set_cs || + !master->set_sck || !master->set_mosi || !master->get_miso || + (master->request_bus && !master->release_bus) || + (!master->request_bus && master->release_bus)) { + msg_perr("Incomplete SPI bitbang master setting!\n" + "Please report a bug at flashrom(a)flashrom.org\n"); + return ERROR_FLASHROM_BUG; + } + + mst.data = master; + register_spi_master(&mst); + + /* Only mess with the bus if we're sure nobody else uses it. */ + bitbang_spi_request_bus(master); + bitbang_spi_set_cs(master, 1); + bitbang_spi_set_sck_set_mosi(master, 0, 0); + /* FIXME: Release SPI bus here and request it again for each command or + * don't release it now and only release it on programmer shutdown? + */ + bitbang_spi_release_bus(master); + return 0; +} -- To view, visit https://review.coreboot.org/c/flashrom/+/47664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ided41c6c64376e0cddeb17b936773a86c36d5f72 Gerrit-Change-Number: 47664 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 2

Change in flashrom[master]: it87spi.c: Remove 'it8716f_' prefix from local state tracker
by Edward O'Callaghan (Code Review) 22 Nov '20

22 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47663 ) Change subject: it87spi.c: Remove 'it8716f_' prefix from local state tracker ...................................................................... it87spi.c: Remove 'it8716f_' prefix from local state tracker The local state inhabited within the state tracker has now obvious scope and therefore we can drop the redundant prefix for readability. BUG=b:173477683 TEST=builds Change-Id: Ic1c9647ef640152417a66dbb411554b83e30ad75 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M it87spi.c 1 file changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/63/47663/1 diff --git a/it87spi.c b/it87spi.c index 78fd19c..09f949e 100644 --- a/it87spi.c +++ b/it87spi.c @@ -39,7 +39,7 @@ #define CHIP_VER_REG 0x22 struct it8716f_spi_data { - uint16_t it8716f_flashport; + uint16_t flashport; /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ int fast_spi; }; @@ -127,11 +127,11 @@ if (result) return result; /* FIXME: The command below seems to be redundant or wrong. */ - OUTB(0x06, data->it8716f_flashport + 1); - OUTB(((2 + (data->fast_spi ? 1 : 0)) << 4), data->it8716f_flashport); + OUTB(0x06, data->flashport + 1); + OUTB(((2 + (data->fast_spi ? 1 : 0)) << 4), data->flashport); for (i = 0; i < flash->chip->page_size; i++) mmio_writeb(buf[i], (void *)(bios + start + i)); - OUTB(0, data->it8716f_flashport); + OUTB(0, data->flashport); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-10 ms, so wait in 1 ms steps. */ @@ -161,7 +161,7 @@ return SPI_GENERIC_ERROR; do { - busy = INB(data->it8716f_flashport) & 0x80; + busy = INB(data->flashport) & 0x80; } while (busy); if (readcnt > 3) { msg_pinfo("%s called with unsupported readcnt %i.\n", @@ -170,27 +170,27 @@ } switch (writecnt) { case 1: - OUTB(writearr[0], data->it8716f_flashport + 1); + OUTB(writearr[0], data->flashport + 1); writeenc = 0x0; break; case 2: - OUTB(writearr[0], data->it8716f_flashport + 1); - OUTB(writearr[1], data->it8716f_flashport + 7); + OUTB(writearr[0], data->flashport + 1); + OUTB(writearr[1], data->flashport + 7); writeenc = 0x1; break; case 4: - OUTB(writearr[0], data->it8716f_flashport + 1); - OUTB(writearr[1], data->it8716f_flashport + 4); - OUTB(writearr[2], data->it8716f_flashport + 3); - OUTB(writearr[3], data->it8716f_flashport + 2); + OUTB(writearr[0], data->flashport + 1); + OUTB(writearr[1], data->flashport + 4); + OUTB(writearr[2], data->flashport + 3); + OUTB(writearr[3], data->flashport + 2); writeenc = 0x2; break; case 5: - OUTB(writearr[0], data->it8716f_flashport + 1); - OUTB(writearr[1], data->it8716f_flashport + 4); - OUTB(writearr[2], data->it8716f_flashport + 3); - OUTB(writearr[3], data->it8716f_flashport + 2); - OUTB(writearr[4], data->it8716f_flashport + 7); + OUTB(writearr[0], data->flashport + 1); + OUTB(writearr[1], data->flashport + 4); + OUTB(writearr[2], data->flashport + 3); + OUTB(writearr[3], data->flashport + 2); + OUTB(writearr[4], data->flashport + 7); writeenc = 0x3; break; default: @@ -204,17 +204,17 @@ * We can't use writecnt directly, but have to use a strange encoding. */ OUTB(((0x4 + (data->fast_spi ? 1 : 0)) << 4) - | ((readcnt & 0x3) << 2) | (writeenc), data->it8716f_flashport); + | ((readcnt & 0x3) << 2) | (writeenc), data->flashport); if (readcnt > 0) { unsigned int i; do { - busy = INB(data->it8716f_flashport) & 0x80; + busy = INB(data->flashport) & 0x80; } while (busy); for (i = 0; i < readcnt; i++) - readarr[i] = INB(data->it8716f_flashport + 5 + i); + readarr[i] = INB(data->flashport + 5 + i); } return 0; @@ -417,7 +417,7 @@ return SPI_GENERIC_ERROR; } - data->it8716f_flashport = flashport; + data->flashport = flashport; data->fast_spi = 1; spi_master_it87xx.data = data; -- To view, visit https://review.coreboot.org/c/flashrom/+/47663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic1c9647ef640152417a66dbb411554b83e30ad75 Gerrit-Change-Number: 47663 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 3

Change in flashrom[master]: it87spi.c: Move singleton state into spi master state tracker
by Edward O'Callaghan (Code Review) 22 Nov '20

22 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47662 ) Change subject: it87spi.c: Move singleton state into spi master state tracker ...................................................................... it87spi.c: Move singleton state into spi master state tracker Make use of the reneterent framework by moving singleton static state out of the global life-time and into a per-spi_master basis. This allows for the it87spi master to be reneterent and its internal state's life-time to be correctly handled by Flashrom's core dispatch logic. BUG=b:173477683 TEST=builds Change-Id: I6e9c3e6f12e51e456ee237c389cc326c64a71999 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M it87spi.c 1 file changed, 71 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/47662/1 diff --git a/it87spi.c b/it87spi.c index bb6e3fa..78fd19c 100644 --- a/it87spi.c +++ b/it87spi.c @@ -38,9 +38,22 @@ #define CHIP_ID_BYTE2_REG 0x21 #define CHIP_VER_REG 0x22 -static uint16_t it8716f_flashport = 0; -/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ -static int fast_spi = 1; +struct it8716f_spi_data { + uint16_t it8716f_flashport; + /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ + int fast_spi; +}; + +static int get_data_from_context(const struct flashctx *flash, struct it8716f_spi_data **data) +{ + if (!flash || !flash->mst || !flash->mst->spi.data) { + msg_perr("Unable to extract fd from flash context.\n"); + return SPI_GENERIC_ERROR; + } + *data = (struct it8716f_spi_data *)flash->mst->spi.data; + + return 0; +} void enter_conf_mode_ite(uint16_t port) { @@ -105,16 +118,20 @@ unsigned int i; int result; chipaddr bios = flash->virtual_memory; + struct it8716f_spi_data *data; + + if (get_data_from_context(flash, &data) < 0) + return SPI_GENERIC_ERROR; result = spi_write_enable(flash); if (result) return result; /* FIXME: The command below seems to be redundant or wrong. */ - OUTB(0x06, it8716f_flashport + 1); - OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); + OUTB(0x06, data->it8716f_flashport + 1); + OUTB(((2 + (data->fast_spi ? 1 : 0)) << 4), data->it8716f_flashport); for (i = 0; i < flash->chip->page_size; i++) mmio_writeb(buf[i], (void *)(bios + start + i)); - OUTB(0, it8716f_flashport); + OUTB(0, data->it8716f_flashport); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-10 ms, so wait in 1 ms steps. */ @@ -138,9 +155,13 @@ unsigned char *readarr) { uint8_t busy, writeenc; + struct it8716f_spi_data *data; + + if (get_data_from_context(flash, &data) < 0) + return SPI_GENERIC_ERROR; do { - busy = INB(it8716f_flashport) & 0x80; + busy = INB(data->it8716f_flashport) & 0x80; } while (busy); if (readcnt > 3) { msg_pinfo("%s called with unsupported readcnt %i.\n", @@ -149,27 +170,27 @@ } switch (writecnt) { case 1: - OUTB(writearr[0], it8716f_flashport + 1); + OUTB(writearr[0], data->it8716f_flashport + 1); writeenc = 0x0; break; case 2: - OUTB(writearr[0], it8716f_flashport + 1); - OUTB(writearr[1], it8716f_flashport + 7); + OUTB(writearr[0], data->it8716f_flashport + 1); + OUTB(writearr[1], data->it8716f_flashport + 7); writeenc = 0x1; break; case 4: - OUTB(writearr[0], it8716f_flashport + 1); - OUTB(writearr[1], it8716f_flashport + 4); - OUTB(writearr[2], it8716f_flashport + 3); - OUTB(writearr[3], it8716f_flashport + 2); + OUTB(writearr[0], data->it8716f_flashport + 1); + OUTB(writearr[1], data->it8716f_flashport + 4); + OUTB(writearr[2], data->it8716f_flashport + 3); + OUTB(writearr[3], data->it8716f_flashport + 2); writeenc = 0x2; break; case 5: - OUTB(writearr[0], it8716f_flashport + 1); - OUTB(writearr[1], it8716f_flashport + 4); - OUTB(writearr[2], it8716f_flashport + 3); - OUTB(writearr[3], it8716f_flashport + 2); - OUTB(writearr[4], it8716f_flashport + 7); + OUTB(writearr[0], data->it8716f_flashport + 1); + OUTB(writearr[1], data->it8716f_flashport + 4); + OUTB(writearr[2], data->it8716f_flashport + 3); + OUTB(writearr[3], data->it8716f_flashport + 2); + OUTB(writearr[4], data->it8716f_flashport + 7); writeenc = 0x3; break; default: @@ -182,18 +203,18 @@ * Note: * We can't use writecnt directly, but have to use a strange encoding. */ - OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4) - | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport); + OUTB(((0x4 + (data->fast_spi ? 1 : 0)) << 4) + | ((readcnt & 0x3) << 2) | (writeenc), data->it8716f_flashport); if (readcnt > 0) { unsigned int i; do { - busy = INB(it8716f_flashport) & 0x80; + busy = INB(data->it8716f_flashport) & 0x80; } while (busy); for (i = 0; i < readcnt; i++) - readarr[i] = INB(it8716f_flashport + 5 + i); + readarr[i] = INB(data->it8716f_flashport + 5 + i); } return 0; @@ -206,7 +227,12 @@ static int it8716f_spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { - fast_spi = 0; + struct it8716f_spi_data *data; + + if (get_data_from_context(flash, &data) < 0) + return SPI_GENERIC_ERROR; + + data->fast_spi = 0; /* FIXME: Check if someone explicitly requested to use IT87 SPI although * the mainboard does not use IT87 SPI translation. This should be done @@ -264,7 +290,7 @@ return 0; } -static const struct spi_master spi_master_it87xx = { +static struct spi_master spi_master_it87xx = { .max_data_read = 3, .max_data_write = MAX_DATA_UNSPECIFIED, .command = it8716f_spi_send_command, @@ -274,6 +300,13 @@ .write_aai = spi_chip_write_1, }; + +static int it8716f_shutdown(void *data) +{ + free(data); + return 0; +} + static uint16_t it87spi_probe(uint16_t port) { uint8_t tmp = 0; @@ -377,7 +410,19 @@ } free(param); exit_conf_mode_ite(port); - it8716f_flashport = flashport; + + struct it8716f_spi_data *data = calloc(1, sizeof(struct it8716f_spi_data)); + if (!data) { + msg_perr("Unable to allocate space for extra SPI master data.\n"); + return SPI_GENERIC_ERROR; + } + + data->it8716f_flashport = flashport; + data->fast_spi = 1; + spi_master_it87xx.data = data; + + register_shutdown(it8716f_shutdown, data); + if (internal_buses_supported & BUS_SPI) msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); /* FIXME: Add the SPI bus or replace the other buses with it? */ -- To view, visit https://review.coreboot.org/c/flashrom/+/47662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6e9c3e6f12e51e456ee237c389cc326c64a71999 Gerrit-Change-Number: 47662 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 3

Change in flashrom[master]: it87spi.c: Reorder functions with primitives at the top
by Edward O'Callaghan (Code Review) 22 Nov '20

22 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47661 ) Change subject: it87spi.c: Reorder functions with primitives at the top ...................................................................... it87spi.c: Reorder functions with primitives at the top Reshuffle file with no semantic changes, this avoids unnecessary prototypes for static member functions as to pave the way for further cleanups as well as an easier to parse implementation. BUG=b:173477683 TEST=builds Change-Id: I94b169d19cb29336bb9cb4c16d0efee15b1e14c2 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M it87spi.c 1 file changed, 165 insertions(+), 173 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/61/47661/1 diff --git a/it87spi.c b/it87spi.c index 79b4448..bb6e3fa 100644 --- a/it87spi.c +++ b/it87spi.c @@ -33,14 +33,15 @@ #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e -static uint16_t it8716f_flashport = 0; -/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ -static int fast_spi = 1; - /* Helper functions for most recent ITE IT87xx Super I/O chips */ #define CHIP_ID_BYTE1_REG 0x20 #define CHIP_ID_BYTE2_REG 0x21 #define CHIP_VER_REG 0x22 + +static uint16_t it8716f_flashport = 0; +/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ +static int fast_spi = 1; + void enter_conf_mode_ite(uint16_t port) { OUTB(0x87, port); @@ -98,14 +99,170 @@ return; } +/* Page size is usually 256 bytes */ +static int it8716f_spi_page_program(struct flashctx *flash, const uint8_t *buf, unsigned int start) +{ + unsigned int i; + int result; + chipaddr bios = flash->virtual_memory; + + result = spi_write_enable(flash); + if (result) + return result; + /* FIXME: The command below seems to be redundant or wrong. */ + OUTB(0x06, it8716f_flashport + 1); + OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); + for (i = 0; i < flash->chip->page_size; i++) + mmio_writeb(buf[i], (void *)(bios + start + i)); + OUTB(0, it8716f_flashport); + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 1-10 ms, so wait in 1 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(1000); + return 0; +} + +/* + * The IT8716F only supports commands with length 1,2,4,5 bytes including + * command byte and can not read more than 3 bytes from the device. + * + * This function expects writearr[0] to be the first byte sent to the device, + * whereas the IT8716F splits commands internally into address and non-address + * commands with the address in inverse wire order. That's why the register + * ordering in case 4 and 5 may seem strange. + */ static int it8716f_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, - unsigned char *readarr); + unsigned char *readarr) +{ + uint8_t busy, writeenc; + + do { + busy = INB(it8716f_flashport) & 0x80; + } while (busy); + if (readcnt > 3) { + msg_pinfo("%s called with unsupported readcnt %i.\n", + __func__, readcnt); + return SPI_INVALID_LENGTH; + } + switch (writecnt) { + case 1: + OUTB(writearr[0], it8716f_flashport + 1); + writeenc = 0x0; + break; + case 2: + OUTB(writearr[0], it8716f_flashport + 1); + OUTB(writearr[1], it8716f_flashport + 7); + writeenc = 0x1; + break; + case 4: + OUTB(writearr[0], it8716f_flashport + 1); + OUTB(writearr[1], it8716f_flashport + 4); + OUTB(writearr[2], it8716f_flashport + 3); + OUTB(writearr[3], it8716f_flashport + 2); + writeenc = 0x2; + break; + case 5: + OUTB(writearr[0], it8716f_flashport + 1); + OUTB(writearr[1], it8716f_flashport + 4); + OUTB(writearr[2], it8716f_flashport + 3); + OUTB(writearr[3], it8716f_flashport + 2); + OUTB(writearr[4], it8716f_flashport + 7); + writeenc = 0x3; + break; + default: + msg_pinfo("%s called with unsupported writecnt %i.\n", + __func__, writecnt); + return SPI_INVALID_LENGTH; + } + /* + * Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes. + * Note: + * We can't use writecnt directly, but have to use a strange encoding. + */ + OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4) + | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport); + + if (readcnt > 0) { + unsigned int i; + + do { + busy = INB(it8716f_flashport) & 0x80; + } while (busy); + + for (i = 0; i < readcnt; i++) + readarr[i] = INB(it8716f_flashport + 5 + i); + } + + return 0; +} + +/* + * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles + * Need to read this big flash using firmware cycles 3 byte at a time. + */ static int it8716f_spi_chip_read(struct flashctx *flash, uint8_t *buf, - unsigned int start, unsigned int len); + unsigned int start, unsigned int len) +{ + fast_spi = 0; + + /* FIXME: Check if someone explicitly requested to use IT87 SPI although + * the mainboard does not use IT87 SPI translation. This should be done + * via a programmer parameter for the internal programmer. + */ + if ((flash->chip->total_size * 1024 > 512 * 1024)) { + default_spi_read(flash, buf, start, len); + } else { + mmio_readn((void *)(flash->virtual_memory + start), buf, len); + } + + return 0; +} + static int it8716f_spi_chip_write_256(struct flashctx *flash, const uint8_t *buf, - unsigned int start, unsigned int len); + unsigned int start, unsigned int len) +{ + const struct flashchip *chip = flash->chip; + /* + * IT8716F only allows maximum of 512 kb SPI chip size for memory + * mapped access. It also can't write more than 1+3+256 bytes at once, + * so page_size > 256 bytes needs a fallback. + * FIXME: Split too big page writes into chunks IT87* can handle instead + * of degrading to single-byte program. + * FIXME: Check if someone explicitly requested to use IT87 SPI although + * the mainboard does not use IT87 SPI translation. This should be done + * via a programmer parameter for the internal programmer. + */ + if ((chip->total_size * 1024 > 512 * 1024) || (chip->page_size > 256)) { + spi_chip_write_1(flash, buf, start, len); + } else { + unsigned int lenhere; + + if (start % chip->page_size) { + /* start to the end of the page or to start + len, + * whichever is smaller. + */ + lenhere = min(len, chip->page_size - start % chip->page_size); + spi_chip_write_1(flash, buf, start, lenhere); + start += lenhere; + len -= lenhere; + buf += lenhere; + } + + while (len >= chip->page_size) { + it8716f_spi_page_program(flash, buf, start); + start += chip->page_size; + len -= chip->page_size; + buf += chip->page_size; + } + if (len) + spi_chip_write_1(flash, buf, start, len); + } + + return 0; +} static const struct spi_master spi_master_it87xx = { .max_data_read = 3, @@ -267,169 +424,4 @@ return ret; } -/* - * The IT8716F only supports commands with length 1,2,4,5 bytes including - * command byte and can not read more than 3 bytes from the device. - * - * This function expects writearr[0] to be the first byte sent to the device, - * whereas the IT8716F splits commands internally into address and non-address - * commands with the address in inverse wire order. That's why the register - * ordering in case 4 and 5 may seem strange. - */ -static int it8716f_spi_send_command(const struct flashctx *flash, - unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, - unsigned char *readarr) -{ - uint8_t busy, writeenc; - - do { - busy = INB(it8716f_flashport) & 0x80; - } while (busy); - if (readcnt > 3) { - msg_pinfo("%s called with unsupported readcnt %i.\n", - __func__, readcnt); - return SPI_INVALID_LENGTH; - } - switch (writecnt) { - case 1: - OUTB(writearr[0], it8716f_flashport + 1); - writeenc = 0x0; - break; - case 2: - OUTB(writearr[0], it8716f_flashport + 1); - OUTB(writearr[1], it8716f_flashport + 7); - writeenc = 0x1; - break; - case 4: - OUTB(writearr[0], it8716f_flashport + 1); - OUTB(writearr[1], it8716f_flashport + 4); - OUTB(writearr[2], it8716f_flashport + 3); - OUTB(writearr[3], it8716f_flashport + 2); - writeenc = 0x2; - break; - case 5: - OUTB(writearr[0], it8716f_flashport + 1); - OUTB(writearr[1], it8716f_flashport + 4); - OUTB(writearr[2], it8716f_flashport + 3); - OUTB(writearr[3], it8716f_flashport + 2); - OUTB(writearr[4], it8716f_flashport + 7); - writeenc = 0x3; - break; - default: - msg_pinfo("%s called with unsupported writecnt %i.\n", - __func__, writecnt); - return SPI_INVALID_LENGTH; - } - /* - * Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes. - * Note: - * We can't use writecnt directly, but have to use a strange encoding. - */ - OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4) - | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport); - - if (readcnt > 0) { - unsigned int i; - - do { - busy = INB(it8716f_flashport) & 0x80; - } while (busy); - - for (i = 0; i < readcnt; i++) - readarr[i] = INB(it8716f_flashport + 5 + i); - } - - return 0; -} - -/* Page size is usually 256 bytes */ -static int it8716f_spi_page_program(struct flashctx *flash, const uint8_t *buf, unsigned int start) -{ - unsigned int i; - int result; - chipaddr bios = flash->virtual_memory; - - result = spi_write_enable(flash); - if (result) - return result; - /* FIXME: The command below seems to be redundant or wrong. */ - OUTB(0x06, it8716f_flashport + 1); - OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); - for (i = 0; i < flash->chip->page_size; i++) - mmio_writeb(buf[i], (void *)(bios + start + i)); - OUTB(0, it8716f_flashport); - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 1-10 ms, so wait in 1 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1000); - return 0; -} - -/* - * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles - * Need to read this big flash using firmware cycles 3 byte at a time. - */ -static int it8716f_spi_chip_read(struct flashctx *flash, uint8_t *buf, - unsigned int start, unsigned int len) -{ - fast_spi = 0; - - /* FIXME: Check if someone explicitly requested to use IT87 SPI although - * the mainboard does not use IT87 SPI translation. This should be done - * via a programmer parameter for the internal programmer. - */ - if ((flash->chip->total_size * 1024 > 512 * 1024)) { - default_spi_read(flash, buf, start, len); - } else { - mmio_readn((void *)(flash->virtual_memory + start), buf, len); - } - - return 0; -} - -static int it8716f_spi_chip_write_256(struct flashctx *flash, const uint8_t *buf, - unsigned int start, unsigned int len) -{ - const struct flashchip *chip = flash->chip; - /* - * IT8716F only allows maximum of 512 kb SPI chip size for memory - * mapped access. It also can't write more than 1+3+256 bytes at once, - * so page_size > 256 bytes needs a fallback. - * FIXME: Split too big page writes into chunks IT87* can handle instead - * of degrading to single-byte program. - * FIXME: Check if someone explicitly requested to use IT87 SPI although - * the mainboard does not use IT87 SPI translation. This should be done - * via a programmer parameter for the internal programmer. - */ - if ((chip->total_size * 1024 > 512 * 1024) || (chip->page_size > 256)) { - spi_chip_write_1(flash, buf, start, len); - } else { - unsigned int lenhere; - - if (start % chip->page_size) { - /* start to the end of the page or to start + len, - * whichever is smaller. - */ - lenhere = min(len, chip->page_size - start % chip->page_size); - spi_chip_write_1(flash, buf, start, lenhere); - start += lenhere; - len -= lenhere; - buf += lenhere; - } - - while (len >= chip->page_size) { - it8716f_spi_page_program(flash, buf, start); - start += chip->page_size; - len -= chip->page_size; - buf += chip->page_size; - } - if (len) - spi_chip_write_1(flash, buf, start, len); - } - - return 0; -} - -#endif +#endif /* defined(__i386__) || defined(__x86_64__) */ -- To view, visit https://review.coreboot.org/c/flashrom/+/47661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I94b169d19cb29336bb9cb4c16d0efee15b1e14c2 Gerrit-Change-Number: 47661 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

4 7

Change in flashrom[master]: flashrom: Added Support for BoyaMicro BY25Q128AS
by Jack Olsen (Code Review) 20 Nov '20

20 Nov '20

Jack Olsen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44308 ) Change subject: flashrom: Added Support for BoyaMicro BY25Q128AS ...................................................................... flashrom: Added Support for BoyaMicro BY25Q128AS Tested on Buspirate Change-Id: I881ba86cfaa82e43c73360135d47c74d896cc191 --- M flashchips.c M flashchips.h 2 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/44308/1 diff --git a/flashchips.c b/flashchips.c index 09ac9b4..5c60b2c 100644 --- a/flashchips.c +++ b/flashchips.c @@ -3442,6 +3442,44 @@ .voltage = {3000, 3600}, }, + { + .vendor = "Boya", + .name = "BY25Q128AS", + .bustype = BUS_SPI, + .manufacture_id = BOYA_ID, + .model_id = BOYA_BY25Q128AS, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, + .unlock = spi_disable_blockprotect_at25fs040, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + { .vendor = "Bright", .name = "BM29F040", diff --git a/flashchips.h b/flashchips.h index 4ae6c07..9d19ef5 100644 --- a/flashchips.h +++ b/flashchips.h @@ -207,6 +207,10 @@ #define ATMEL_AT49F080 0x23 #define ATMEL_AT49F080T 0x27 +/* Boya Microelectronics Inc.*/ +#define BOYA_ID 0x68 +#define BOYA_BY25Q128AS 0x4018 + /* Bright Microelectronics has the same manufacturer ID as Hyundai... */ #define BRIGHT_ID 0xAD /* Bright Microelectronics */ #define BRIGHT_BM29F040 0x40 -- To view, visit https://review.coreboot.org/c/flashrom/+/44308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I881ba86cfaa82e43c73360135d47c74d896cc191 Gerrit-Change-Number: 44308 Gerrit-PatchSet: 1 Gerrit-Owner: Jack Olsen <omegasec(a)tutanota.com> Gerrit-MessageType: newchange

5 21

Change in flashrom[master]: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call
by Simon Buhrow (Code Review) 20 Nov '20

20 Nov '20

Simon Buhrow has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40477 ) Change subject: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call ...................................................................... Patch Set 21: PS21 is a shortly (and successfully) tested version. Let me know if there is anything bad. -- To view, visit https://review.coreboot.org/c/flashrom/+/40477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie4a07499ec5ef0af23818593f45dc427285a9e8a Gerrit-Change-Number: 40477 Gerrit-PatchSet: 21 Gerrit-Owner: Simon Buhrow Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 20 Nov 2020 10:50:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

2024

2023

2022

2021

2020

2019

2018

2017

flashrom-gerrit November 2020