August 2019 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: libflashrom.h: Add types not included in all projects
by Mario Limonciello (Code Review) 23 Sep '19

23 Sep '19

Mario Limonciello has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/35155 ) Change subject: libflashrom.h: Add types not included in all projects ...................................................................... libflashrom.h: Add types not included in all projects Fixes this in fwupd: ``` cc -Iplugins/flashrom/1ac62b6@@fu_plugin_flashrom@sha -Iplugins/flashrom -I../plugins/flashrom -Iplugins/flashrom/../.. -I../plugins/flashrom/../.. -Iplugins/flashrom/../../src -I../plugins/flashrom/../../src -Iplugins/flashrom/../../libfwupd -I../plugins/flashrom/../../libfwupd -Isubprojects/flashrom -I../subprojects/flashrom -Isrc -I/usr/include/libxmlb-1 -I/usr/include/libmount -I/usr/include/blkid -I/usr/include/uuid -I/usr/include/glib-2.0 -I/usr/lib/x86_64-linux-gnu/glib-2.0/include -I/usr/include/gio-unix-2.0 -I/usr/include/gusb-1 -I/usr/include/libusb-1.0 -I/usr/include/libsoup-2.4 -I/usr/include/libxml2 -I/usr/include/gudev-1.0 -I/usr/include/x86_64-linux-gnu -I/usr/include/libftdi1 -fdiagnostics-color=always -pipe -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Wextra -std=c99 -g -fstack-protector-strong -Waggregate-return -Wunused -Warray-bounds -Wcast-align -Wclobbered -Wdeclaration-after-statement -Wduplicated-branches -Wduplicated-cond -Wempty-body -Wformat=2 -Wformat-nonliteral -Wformat-security -Wformat-signedness -Wignored-qualifiers -Wimplicit-function-declaration -Winit-self -Wlogical-op -Wmissing-declarations -Wmissing-format-attribute -Wmissing-include-dirs -Wmissing-noreturn -Wmissing-parameter-type -Wmissing-prototypes -Wnested-externs -Wno-cast-function-type -Wno-address-of-packed-member -Wno-unknown-pragmas -Wno-deprecated-declarations -Wno-discarded-qualifiers -Wno-missing-field-initializers -Wno-strict-aliasing -Wno-suggest-attribute=format -Wno-unused-parameter -Wnull-dereference -Wold-style-definition -Woverride-init -Wpointer-arith -Wredundant-decls -Wreturn-type -Wshadow -Wsign-compare -Wstrict-aliasing -Wstrict-prototypes -Wswitch-default -Wtype-limits -Wundef -Wuninitialized -Wunused-but-set-variable -Wunused-variable -Wvla -Wwrite-strings -D_DEFAULT_SOURCE -DFWUPD_DISABLE_DEPRECATED -D_BSD_SOURCE -D_XOPEN_SOURCE=700 -fPIC -pthread '-DG_LOG_DOMAIN="FuPluginFlashrom"' '-DLOCALSTATEDIR="/usr/local/var"' -MD -MQ 'plugins/flashrom/1ac62b6@@fu_plugin_flashrom@sha/fu-plugin-flashrom.c.o' -MF 'plugins/flashrom/1ac62b6@@fu_plugin_flashrom@sha/fu-plugin-flashrom.c.o.d' -o 'plugins/flashrom/1ac62b6@@fu_plugin_flashrom@sha/fu-plugin-flashrom.c.o' -c ../plugins/flashrom/fu-plugin-flashrom.c In file included from ../plugins/flashrom/fu-plugin-flashrom.c:27: ../subprojects/flashrom/libflashrom.h:57:72: error: unknown type name ‘bool’ 57 | void flashrom_flag_set(struct flashrom_flashctx *, enum flashrom_flag, bool value); | ^~~~ ../subprojects/flashrom/libflashrom.h:58:1: error: unknown type name ‘bool’ 58 | bool flashrom_flag_get(const struct flashrom_flashctx *, enum flashrom_flag); | ^~~~ ../subprojects/flashrom/libflashrom.h:69:37: error: unknown type name ‘uint8_t’ 69 | struct flashrom_flashctx *, const uint8_t *buf, size_t len); | ^~~~~~~ ``` Signed-off-by: Mario Limonciello <mario.limonciello(a)dell.com> Change-Id: Ib48ddc6412f82677f43e445346dc64ccfadf2423 --- M libflashrom.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/55/35155/1 diff --git a/libflashrom.h b/libflashrom.h index 38c95d2..ed42d6d 100644 --- a/libflashrom.h +++ b/libflashrom.h @@ -20,6 +20,8 @@ #include <sys/types.h> #include <stddef.h> +#include <stdbool.h> +#include <cstdint.h> #include <stdarg.h> int flashrom_init(int perform_selfcheck); -- To view, visit https://review.coreboot.org/c/flashrom/+/35155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib48ddc6412f82677f43e445346dc64ccfadf2423 Gerrit-Change-Number: 35155 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Limonciello <superm1(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips.c: EN29F002(A)(N)B tested +EW
by Alan Green (Code Review) 17 Sep '19

17 Sep '19

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/35092 ) Change subject: flashchips.c: EN29F002(A)(N)B tested +EW ...................................................................... flashchips.c: EN29F002(A)(N)B tested +EW Mark EN29F002(A)(N)B as tested for erase and write. This chip was marked tested in the Chromium (downstream) repo change 98d917cfba55b68516cdf64c754d2f36c8c26722 "Add a bunch of new/tested stuff and various small changes 8" TEST=Build and run flashrom -L Signed-off-by: Alan Green <avg(a)google.com> Change-Id: Idd26187905f389fc858eea5b13915af88e40afe9 --- M flashchips.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/92/35092/1 diff --git a/flashchips.c b/flashchips.c index f84f1cc..3994c93 100644 --- a/flashchips.c +++ b/flashchips.c @@ -5398,7 +5398,7 @@ .total_size = 256, .page_size = 256, .feature_bits = FEATURE_ADDR_AAA | FEATURE_EITHER_RESET, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .block_erasers = -- To view, visit https://review.coreboot.org/c/flashrom/+/35092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idd26187905f389fc858eea5b13915af88e40afe9 Gerrit-Change-Number: 35092 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips.c: Identify MX25L25645G part
by Alan Green (Code Review) 17 Sep '19

17 Sep '19

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/35091 ) Change subject: flashchips.c: Identify MX25L25645G part ...................................................................... flashchips.c: Identify MX25L25645G part Apply downstream patch d978051c2e7da88088ec4ef19827c04873a5479d, "flashrom: Identify MX25L25645G part" from chris_zhou(a)compal.corp-partner.google.com 2019-04-13. Change description was: MX25L25635F and MX25L25645G have the same chips identify. Add MX25L25645G to the name of the part so that it doesn't confused people. Signed-off-by: Alan Green <avg(a)google.com> Change-Id: I317345b4753cfc46fdca8f673a0591e33b62138b --- M flashchips.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/91/35091/1 diff --git a/flashchips.c b/flashchips.c index 1c67887..f84f1cc 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8109,7 +8109,7 @@ { .vendor = "Macronix", - .name = "MX25L25635F", + .name = "MX25L25635F/MX25L25645G", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25L25635F, -- To view, visit https://review.coreboot.org/c/flashrom/+/35091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I317345b4753cfc46fdca8f673a0591e33b62138b Gerrit-Change-Number: 35091 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: Add GD25Q127C name to the GD25Q128C entry
by Alan Green (Code Review) 17 Sep '19

17 Sep '19

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/35089 ) Change subject: flashchips: Add GD25Q127C name to the GD25Q128C entry ...................................................................... flashchips: Add GD25Q127C name to the GD25Q128C entry Renamed GigaDevice GD25Q128 to GD25Q127C/GD25Q128. According to downstream (ChromiumOS) change 4216ba3d0fbd1804a71002b9c17e0b04029a03f1 "flashchips: Add GD25Q127C name to the GD25Q128C entry", the 127C chip is replacement for the 128C chip. I have confirmed that 127C is newer and that 128C does not appear to be documented on Gigadevice's website or available from Digikey. TEST=Ran flashrom -L Signed-off-by: Alan Green <avg(a)google.com> Change-Id: I3366e5904eff2443fda90552f7f5e31a8785d8b3 --- M flashchips.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/89/35089/1 diff --git a/flashchips.c b/flashchips.c index 9b686c1..1c67887 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6158,7 +6158,7 @@ { .vendor = "GigaDevice", - .name = "GD25Q128C", + .name = "GD25Q127C/GD25Q128C", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q128, -- To view, visit https://review.coreboot.org/c/flashrom/+/35089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3366e5904eff2443fda90552f7f5e31a8785d8b3 Gerrit-Change-Number: 35089 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips.c: Put SFDP-capable chip back into position
by Alan Green (Code Review) 17 Sep '19

17 Sep '19

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/35037 ) Change subject: flashchips.c: Put SFDP-capable chip back into position ...................................................................... flashchips.c: Put SFDP-capable chip back into position Put entry for Unknown SFDP-capable chip back into place at end of file. SHA 1f9cc7d89992114c70f7a0545ad9f98701bebe56 reordered many entries in flashchips.c, including this one. However, the entry for Unknown, SFDP-capable chip should not have been moved before any specific chip entries. As reported by Angel Pons <th3fanbus(a)gmail.com> at https://review.coreboot.org/c/flashrom/+/33931: """ Oops, this introduced a bug: the SFDP entry is no longer at the end of flashchips.c, so probing on a SFDP-capable Winbond chip results in added noise (flashrom says things about an unknown chip, and then has two definitions for the same chip). """ Signed-off-by: Alan Green <avg(a)google.com> Change-Id: I5955020456dbcd5e7db280a459b668a743e464dc --- M flashchips.c 1 file changed, 22 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/37/35037/1 diff --git a/flashchips.c b/flashchips.c index c6f9517..9b686c1 100644 --- a/flashchips.c +++ b/flashchips.c @@ -15612,28 +15612,6 @@ }, { - .vendor = "Unknown", - .name = "SFDP-capable chip", - .bustype = BUS_SPI, - .manufacture_id = GENERIC_MANUF_ID, - .model_id = SFDP_DEVICE_ID, - .total_size = 0, /* set by probing function */ - .page_size = 0, /* set by probing function */ - .feature_bits = 0, /* set by probing function */ - /* We present our own "report this" text hence we do not */ - /* want the default "This flash part has status UNTESTED..." */ - /* text to be printed. */ - .tested = TEST_OK_PREW, - .probe = probe_spi_sfdp, - .block_erasers = {}, /* set by probing function */ - .unlock = spi_disable_blockprotect, /* is this safe? */ - .write = NULL, /* set by probing function */ - .read = spi_chip_read, - /* FIXME: some vendor extensions define this */ - .voltage = {0}, - }, - - { .vendor = "Winbond", .name = "W25P16", .bustype = BUS_SPI, @@ -17576,6 +17554,28 @@ }, { + .vendor = "Unknown", + .name = "SFDP-capable chip", + .bustype = BUS_SPI, + .manufacture_id = GENERIC_MANUF_ID, + .model_id = SFDP_DEVICE_ID, + .total_size = 0, /* set by probing function */ + .page_size = 0, /* set by probing function */ + .feature_bits = 0, /* set by probing function */ + /* We present our own "report this" text hence we do not */ + /* want the default "This flash part has status UNTESTED..." */ + /* text to be printed. */ + .tested = TEST_OK_PREW, + .probe = probe_spi_sfdp, + .block_erasers = {}, /* set by probing function */ + .unlock = spi_disable_blockprotect, /* is this safe? */ + .write = NULL, /* set by probing function */ + .read = spi_chip_read, + /* FIXME: some vendor extensions define this */ + .voltage = {0}, + }, + + { .vendor = "Programmer", .name = "Opaque flash chip", .bustype = BUS_PROG, -- To view, visit https://review.coreboot.org/c/flashrom/+/35037 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5955020456dbcd5e7db280a459b668a743e464dc Gerrit-Change-Number: 35037 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: flashchips.c: Sort file by vendor and model
by Alan Green (Code Review) 22 Aug '19

22 Aug '19

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33931 Change subject: flashchips.c: Sort file by vendor and model ...................................................................... flashchips.c: Sort file by vendor and model For self-consistency, and to allow tools to assist with merging the chromium fork of flashrom, sort the entries of flashchips.c. The file is already largely sorted, though deviations have crept in over time. This is a non-clever mostly ASCII-order sorting. It is not intended to be permanent. Post-merge we can explore options such as breaking apart flashchips.c into per-vendor files or directories. Change-Id: I75a99583592526f60ba5264e92391bf8b1213b20 --- M flashchips.c 1 file changed, 5,510 insertions(+), 5,510 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/31/33931/1 -- To view, visit https://review.coreboot.org/c/flashrom/+/33931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I75a99583592526f60ba5264e92391bf8b1213b20 Gerrit-Change-Number: 33931 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: upstream changes to GD25LQ128
by Alan Green (Code Review) 21 Aug '19

21 Aug '19

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34735 ) Change subject: flashchips: upstream changes to GD25LQ128 ...................................................................... flashchips: upstream changes to GD25LQ128 Change name of GD25LQ128 to GD25LQ128CD. This is an upstreaming of the change from the chromium flashrom repo SHA 6c957d745f5d3dcadd1035734a5cf1b804bd0f2f (Also visible at https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/…) The rationale from that change was: The GD25LQ128C part is EOL. It's replacement is GD25LQ128D, but both chips identify in the same manner. Add GD25LQ128D to the name of the part so that it doesn't confused people. Making this name consistent will simplify further merging from the chromium fork. Change-Id: I57804f1a33170668e029a7b08ac050d9a3bd6dbb --- M flashchips.c M flashchips.h 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/35/34735/1 diff --git a/flashchips.c b/flashchips.c index f8d336e..c6f9517 100644 --- a/flashchips.c +++ b/flashchips.c @@ -5886,10 +5886,10 @@ { .vendor = "GigaDevice", - .name = "GD25LQ128", + .name = "GD25LQ128C/GD25LQ128D", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, - .model_id = GIGADEVICE_GD25LQ128, + .model_id = GIGADEVICE_GD25LQ128CD, .total_size = 16384, .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ diff --git a/flashchips.h b/flashchips.h index 006b95e..7b8bf04 100644 --- a/flashchips.h +++ b/flashchips.h @@ -381,7 +381,7 @@ #define GIGADEVICE_GD25LQ16 0x6015 #define GIGADEVICE_GD25LQ32 0x6016 #define GIGADEVICE_GD25LQ64 0x6017 /* Same as GD25LQ64B (which is faster) */ -#define GIGADEVICE_GD25LQ128 0x6018 +#define GIGADEVICE_GD25LQ128CD 0x6018 #define GIGADEVICE_GD29GL064CAB 0x7E0601 #define HYUNDAI_ID 0xAD /* Hyundai */ -- To view, visit https://review.coreboot.org/c/flashrom/+/34735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I57804f1a33170668e029a7b08ac050d9a3bd6dbb Gerrit-Change-Number: 34735 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: chipset_enable: Mark Intel/CM246 as DEP
by Nico Huber (Code Review) 08 Aug '19

08 Aug '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34073 ) Change subject: chipset_enable: Mark Intel/CM246 as DEP ...................................................................... chipset_enable: Mark Intel/CM246 as DEP The usual ME-lock limitations apply, so this is DEP instead of OK. Tested on Siemens/Field PG M6, and also regression tested on Apollo Lake and Skylake. Flashrom works fine, and logs and descriptor dumps look good. Also, register and descriptor output agree on the flash layout and permissions. Change-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/34073/1 diff --git a/chipset_enable.c b/chipset_enable.c index 3773158..f75f94d 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2044,7 +2044,7 @@ {0x8086, 0xa30a, B_S, NT, "Intel", "C242", enable_flash_pch300}, {0x8086, 0xa30c, B_S, NT, "Intel", "QM370", enable_flash_pch300}, {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300}, - {0x8086, 0xa30e, B_S, NT, "Intel", "CM246", enable_flash_pch300}, + {0x8086, 0xa30e, B_S, DEP, "Intel", "CM246", enable_flash_pch300}, #endif {0}, }; -- To view, visit https://review.coreboot.org/c/flashrom/+/34073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61 Gerrit-Change-Number: 34073 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in flashrom[master]: chipset_enable: Add support for Cannon Lake U Premium
by Matt DeVillier (Code Review) 08 Aug '19

08 Aug '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34076 ) Change subject: chipset_enable: Add support for Cannon Lake U Premium ...................................................................... chipset_enable: Add support for Cannon Lake U Premium Add support for Cannon Lake U Premium (CFL-U/WHL-U). Same as discrete 300-series CNP PCH. Tested on out-of-tree WHL-U board. Change-Id: I8a318d63cf408a3b2cec436a3fa6e26cf8552ead Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M chipset_enable.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/76/34076/1 diff --git a/chipset_enable.c b/chipset_enable.c index 3773158..e880e73 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1995,6 +1995,7 @@ {0x8086, 0x9d53, B_S, NT, "Intel", "Kaby Lake U Base", enable_flash_pch100}, {0x8086, 0x9d56, B_S, NT, "Intel", "Kaby Lake Y Premium", enable_flash_pch100}, {0x8086, 0x9d58, B_S, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100}, + {0x8086, 0x9d84, B_S, NT, "Intel", "Cannon Lake U Premium", enable_flash_pch300}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, {0x8086, 0xa143, B_S, NT, "Intel", "H110", enable_flash_pch100}, -- To view, visit https://review.coreboot.org/c/flashrom/+/34076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8a318d63cf408a3b2cec436a3fa6e26cf8552ead Gerrit-Change-Number: 34076 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi: Add support for discrete Cannon Lake PCHs
by Nico Huber (Code Review) 08 Aug '19

08 Aug '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34072 ) Change subject: ichspi: Add support for discrete Cannon Lake PCHs ...................................................................... ichspi: Add support for discrete Cannon Lake PCHs Only minor differences in the Firmware Descriptor, compared to their predecessors. We extend our check on the `ICCRIBA` field in the descriptor to dis- tinguish it from older generation. Alas, the `freq_read` field was repurposed, so we can't use it as sanity check any more. Change-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M ich_descriptors.c M ich_descriptors.h M ichspi.c M util/ich_descriptors_tool/ich_descriptors_tool.c 5 files changed, 87 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/72/34072/1 diff --git a/chipset_enable.c b/chipset_enable.c index 4b0bab5..3773158 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2035,16 +2035,16 @@ {0x8086, 0xa2c9, B_S, NT, "Intel", "Z370", enable_flash_pch100}, {0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100}, {0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, - {0x8086, 0xa303, B_S, BAD, "Intel", "H310", enable_flash_pch300}, - {0x8086, 0xa304, B_S, BAD, "Intel", "H370", enable_flash_pch300}, - {0x8086, 0xa305, B_S, BAD, "Intel", "Z390", enable_flash_pch300}, - {0x8086, 0xa306, B_S, BAD, "Intel", "Q370", enable_flash_pch300}, - {0x8086, 0xa308, B_S, BAD, "Intel", "B360", enable_flash_pch300}, - {0x8086, 0xa309, B_S, BAD, "Intel", "C246", enable_flash_pch300}, - {0x8086, 0xa30a, B_S, BAD, "Intel", "C242", enable_flash_pch300}, - {0x8086, 0xa30c, B_S, BAD, "Intel", "QM370", enable_flash_pch300}, - {0x8086, 0xa30d, B_S, BAD, "Intel", "HM370", enable_flash_pch300}, - {0x8086, 0xa30e, B_S, BAD, "Intel", "CM246", enable_flash_pch300}, + {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300}, + {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300}, + {0x8086, 0xa305, B_S, NT, "Intel", "Z390", enable_flash_pch300}, + {0x8086, 0xa306, B_S, NT, "Intel", "Q370", enable_flash_pch300}, + {0x8086, 0xa308, B_S, NT, "Intel", "B360", enable_flash_pch300}, + {0x8086, 0xa309, B_S, NT, "Intel", "C246", enable_flash_pch300}, + {0x8086, 0xa30a, B_S, NT, "Intel", "C242", enable_flash_pch300}, + {0x8086, 0xa30c, B_S, NT, "Intel", "QM370", enable_flash_pch300}, + {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300}, + {0x8086, 0xa30e, B_S, NT, "Intel", "CM246", enable_flash_pch300}, #endif {0}, }; diff --git a/ich_descriptors.c b/ich_descriptors.c index a757add..9653d60 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -45,6 +45,7 @@ case CHIPSET_APOLLO_LAKE: return 6; case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: return 16; case CHIPSET_100_SERIES_SUNRISE_POINT: return 10; @@ -106,7 +107,7 @@ "5 series Ibex Peak", "6 series Cougar Point", "7 series Panther Point", "8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg", "9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point", - "C620 series Lewisburg", "Apollo Lake", + "C620 series Lewisburg", "300 series Cannon Point", "Apollo Lake", }; if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names)) cs = 0; @@ -198,6 +199,7 @@ case CHIPSET_9_SERIES_WILDCAT_POINT_LP: case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: { uint8_t size_enc; if (idx == 0) { @@ -265,6 +267,7 @@ return freq_str[0][value]; case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: return freq_str[1][value]; case CHIPSET_APOLLO_LAKE: return freq_str[2][value]; @@ -281,6 +284,7 @@ switch (cs) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: has_flill1 = true; break; @@ -398,7 +402,8 @@ msg_pdbg2("\n"); msg_pdbg2("--- Details ---\n"); - if (cs == CHIPSET_100_SERIES_SUNRISE_POINT) { + if (cs == CHIPSET_100_SERIES_SUNRISE_POINT || + cs == CHIPSET_300_SERIES_CANNON_POINT) { const char *const master_names[] = { "BIOS", "ME", "GbE", "unknown", "EC", }; @@ -408,14 +413,26 @@ return; } - msg_pdbg2(" FD BIOS ME GbE Pltf Reg5 Reg6 Reg7 EC Reg9\n"); + size_t num_regions; + msg_pdbg2(" FD BIOS ME GbE Pltf Reg5 Reg6 Reg7 EC Reg9"); + if (cs == CHIPSET_100_SERIES_SUNRISE_POINT) { + num_regions = 10; + msg_pdbg2("\n"); + } else { + num_regions = 16; + msg_pdbg2(" RegA RegB RegC RegD RegE RegF\n"); + } for (i = 0; i < nm; i++) { size_t j; msg_pdbg2("%-4s", master_names[i]); - for (j = 0; j < 10; j++) + for (j = 0; j < min(num_regions, 12); j++) msg_pdbg2(" %c%c ", desc->master.mstr[i].read & (1 << j) ? 'r' : ' ', desc->master.mstr[i].write & (1 << j) ? 'w' : ' '); + for (; j < num_regions; j++) + msg_pdbg2(" %c%c ", + desc->master.mstr[i].ext_read & (1 << (j - 12)) ? 'r' : ' ', + desc->master.mstr[i].ext_write & (1 << (j - 12)) ? 'w' : ' '); msg_pdbg2("\n"); } } else if (cs == CHIPSET_C620_SERIES_LEWISBURG) { @@ -919,10 +936,15 @@ return CHIPSET_8_SERIES_LYNX_POINT; msg_pwarn("Peculiar firmware descriptor, assuming Wildcat Point compatibility.\n"); return CHIPSET_9_SERIES_WILDCAT_POINT; - } else if (content->NM == 6) { - return CHIPSET_C620_SERIES_LEWISBURG; + } else if (content->ICCRIBA < 0x34) { + if (content->NM == 6) + return CHIPSET_C620_SERIES_LEWISBURG; + else + return CHIPSET_100_SERIES_SUNRISE_POINT; } else { - return CHIPSET_100_SERIES_SUNRISE_POINT; + if (content->ICCRIBA > 0x34) + msg_pwarn("Unknown firmware descriptor, assuming 300 series compatibility.\n"); + return CHIPSET_300_SERIES_CANNON_POINT; } } @@ -938,6 +960,9 @@ const enum ich_chipset guess = guess_ich_chipset_from_content(content); switch (guess) { + case CHIPSET_300_SERIES_CANNON_POINT: + /* `freq_read` was repurposed, so can't check on it any more. */ + return guess; case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_APOLLO_LAKE: @@ -1089,6 +1114,7 @@ case CHIPSET_9_SERIES_WILDCAT_POINT_LP: case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; @@ -1123,6 +1149,7 @@ switch (cs) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: mmio_le_writel(control, spibar + PCH100_REG_FDOC); return mmio_le_readl(spibar + PCH100_REG_FDOD); diff --git a/ich_descriptors.h b/ich_descriptors.h index 4225286..c6bf5d8 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -170,8 +170,9 @@ * Chipset/Generation #FLREGs width (bits) * ICH8 .. Panther Point/7 5 13 * Lynx Point/8 .. Wildcat Point/9 7 15 - * Sunrise Point/100 .. 10 15 + * Sunrise Point/100 .. 200 Series 10 15 * Lewisburg/100 .. 16 15 + * Cannon Point/300 .. 16 15 */ union { uint32_t FLREGs[MAX_NUM_FLREGS]; /* Flash Descriptor Regions */ @@ -234,9 +235,10 @@ }; /* From Skylake on */ struct { - uint32_t :8, - read :12, - write :12; + uint32_t ext_read :4, + ext_write :4, + read :12, + write :12; } mstr[MAX_NUM_MASTERS]; }; }; diff --git a/ichspi.c b/ichspi.c index e1ede60..68bd5d7 100644 --- a/ichspi.c +++ b/ichspi.c @@ -395,15 +395,25 @@ pprint_reg(HSFS, FDONE, reg_val, ", "); pprint_reg(HSFS, FCERR, reg_val, ", "); pprint_reg(HSFS, AEL, reg_val, ", "); - if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT && - ich_generation != CHIPSET_C620_SERIES_LEWISBURG) { + switch (ich_generation) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: + break; + default: pprint_reg(HSFS, BERASE, reg_val, ", "); + break; } pprint_reg(HSFS, SCIP, reg_val, ", "); - if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT || - ich_generation == CHIPSET_C620_SERIES_LEWISBURG) { + switch (ich_generation) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", "); pprint_reg(HSFS, WRSDIS, reg_val, ", "); + break; + default: + break; } pprint_reg(HSFS, FDOPSS, reg_val, ", "); pprint_reg(HSFS, FDV, reg_val, ", "); @@ -414,12 +424,16 @@ { msg_pdbg("HSFC: "); pprint_reg(HSFC, FGO, reg_val, ", "); - if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT && - ich_generation != CHIPSET_C620_SERIES_LEWISBURG) { - pprint_reg(HSFC, FCYCLE, reg_val, ", "); - } else { + switch (ich_generation) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", "); pprint_reg(HSFC, WET, reg_val, ", "); + break; + default: + pprint_reg(HSFC, FCYCLE, reg_val, ", "); + break; } pprint_reg(HSFC, FDBC, reg_val, ", "); pprint_reg(HSFC, SME, reg_val, "\n"); @@ -1567,9 +1581,10 @@ static enum ich_access_protection ich9_handle_frap(uint32_t frap, int i) { const int rwperms_unknown = ARRAY_SIZE(access_names); - static const char *const region_names[6] = { + static const char *const region_names[] = { "Flash Descriptor", "BIOS", "Management Engine", "Gigabit Ethernet", "Platform Data", "Device Expansion", + "BIOS2", "unknown", "EC/BMC", }; const char *const region_name = i < ARRAY_SIZE(region_names) ? region_names[i] : "unknown"; @@ -1724,6 +1739,7 @@ switch (ich_generation) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: num_pr = 6; /* Includes GPR0 */ reg_pr0 = PCH100_REG_FPR0; @@ -1754,6 +1770,7 @@ case CHIPSET_C620_SERIES_LEWISBURG: num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */ break; + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: num_freg = 16; break; @@ -1848,6 +1865,7 @@ switch (ich_gen) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: tmp = mmio_readl(ich_spibar + PCH100_REG_DLOCK); msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); @@ -1921,6 +1939,7 @@ case CHIPSET_ICH8: case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_BAYTRAIL: break; @@ -1952,6 +1971,7 @@ case CHIPSET_ICH8: case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: break; default: @@ -1981,8 +2001,10 @@ ich_spi_mode = ich_hwseq; } - if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT) { - msg_pdbg("Enabling hardware sequencing by default for 100 series PCH.\n"); + if (ich_spi_mode == ich_auto && + (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT || + ich_gen == CHIPSET_300_SERIES_CANNON_POINT)) { + msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n"); ich_spi_mode = ich_hwseq; } diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 2c7966d..2db0f62 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -133,6 +133,7 @@ "\t- \"8\" or \"lynx\" for Intel's 8 series chipsets.\n" "\t- \"9\" or \"wildcat\" for Intel's 9 series chipsets.\n" "\t- \"100\" or \"sunrise\" for Intel's 100 series chipsets.\n" +"\t- \"300\" or \"cannon\" for Intel's 300 series chipsets.\n" "If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" "the GbE blob that is required to initialize the GbE are also dumped to files.\n", argv[0], argv[0]); @@ -221,6 +222,9 @@ else if ((strcmp(csn, "100") == 0) || (strcmp(csn, "sunrise") == 0)) cs = CHIPSET_100_SERIES_SUNRISE_POINT; + else if ((strcmp(csn, "300") == 0) || + (strcmp(csn, "cannon") == 0)) + cs = CHIPSET_300_SERIES_CANNON_POINT; else if (strcmp(csn, "apollo") == 0) cs = CHIPSET_APOLLO_LAKE; } -- To view, visit https://review.coreboot.org/c/flashrom/+/34072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02 Gerrit-Change-Number: 34072 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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flashrom-gerrit August 2019