August 2019 - flashrom-gerrit - mail.coreboot.org

Change in ...flashrom[master]: nicintel_eeprom: Reduce usage of is_i210()
by Nico Huber (Code Review) 10 Dec '19

10 Dec '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33637 Change subject: nicintel_eeprom: Reduce usage of is_i210() ...................................................................... nicintel_eeprom: Reduce usage of is_i210() Don't entagle the code paths for the two NIC classes if it's not necessary. Only compile tested. Change-Id: I59164ccf54afbbd64a0598282d13e80ff7fd6fa4 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M nicintel_eeprom.c 1 file changed, 52 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/37/33637/1 diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index 4e01fcb..4d45f79 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -145,14 +145,6 @@ return 1; } -static int nicintel_ee_probe(struct flashctx *flash) -{ - if (is_i210(nicintel_pci->device_id)) - return nicintel_ee_probe_i210(flash); - - return nicintel_ee_probe_82580(flash); -} - #define MAX_ATTEMPTS 10000000 static int nicintel_ee_read_word(unsigned int addr, uint16_t *data) { @@ -281,6 +273,11 @@ return 0; } +static int nicintel_ee_erase_i210(struct flashctx *flash, unsigned int addr, unsigned int len) +{ + return nicintel_ee_write_i210(flash, NULL, addr, len); +} + static int nicintel_ee_bitset(int reg, int bit, bool val) { uint32_t tmp; @@ -392,24 +389,24 @@ nicintel_ee_bitset(EEC, EE_REQ, 0); /* Give up direct access. */ return ret; } -static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) -{ - if (is_i210(nicintel_pci->device_id)) - return nicintel_ee_write_i210(flash, buf, addr, len); - return nicintel_ee_write_82580(flash, buf, addr, len); +static int nicintel_ee_erase_82580(struct flashctx *flash, unsigned int addr, unsigned int len) +{ + return nicintel_ee_write_82580(flash, NULL, addr, len); } -static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, unsigned int len) -{ - return nicintel_ee_write(flash, NULL, addr, len); -} - -static const struct opaque_master opaque_master_nicintel_ee = { - .probe = nicintel_ee_probe, +static const struct opaque_master opaque_master_nicintel_ee_82580 = { + .probe = nicintel_ee_probe_82580, .read = nicintel_ee_read, - .write = nicintel_ee_write, - .erase = nicintel_ee_erase, + .write = nicintel_ee_write_82580, + .erase = nicintel_ee_erase_82580, +}; + +static const struct opaque_master opaque_master_nicintel_ee_i210 = { + .probe = nicintel_ee_probe_i210, + .read = nicintel_ee_read, + .write = nicintel_ee_write_i210, + .erase = nicintel_ee_erase_i210, }; static int nicintel_ee_shutdown_i210(void *arg) @@ -432,7 +429,7 @@ return -1; } -static int nicintel_ee_shutdown(void *eecp) +static int nicintel_ee_shutdown_82580(void *eecp) { uint32_t old_eec = *(uint32_t *)eecp; /* Request bitbanging and unselect the chip first to be safe. */ @@ -463,35 +460,44 @@ if (!io_base_addr) return 1; - nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", - io_base_addr + (is_i210(dev->device_id) ? 0x12000 : 0), MEMMAP_SIZE); - if (!nicintel_eebar) - return 1; - - nicintel_pci = dev; - if ((dev->device_id != UNPROG_DEVICE) && ! is_i210(dev->device_id)) - { - uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); - - /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting the EE_PRES definition), - * and 3.3.1.7 for possible recovery. */ - if (!(eec & BIT(EE_PRES))) { - msg_perr("Controller reports no EEPROM is present.\n"); + if (!is_i210(dev->device_id)) { + nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", io_base_addr, MEMMAP_SIZE); + if (!nicintel_eebar) return 1; + + nicintel_pci = dev; + if ((dev->device_id != UNPROG_DEVICE)) { + uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); + + /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting + the EE_PRES definition), + and 3.3.1.7 for possible recovery. */ + if (!(eec & BIT(EE_PRES))) { + msg_perr("Controller reports no EEPROM is present.\n"); + return 1; + } + + uint32_t *eecp = malloc(sizeof(uint32_t)); + if (eecp == NULL) + return 1; + *eecp = eec; + + if (register_shutdown(nicintel_ee_shutdown_82580, eecp)) + return 1; } - uint32_t *eecp = malloc(sizeof(uint32_t)); - if (eecp == NULL) + return register_opaque_master(&opaque_master_nicintel_ee_82580); + } else { + nicintel_eebar = rphysmap("Intel i210 NIC w/ emulated EEPROM", + io_base_addr + 0x12000, MEMMAP_SIZE); + if (!nicintel_eebar) return 1; - *eecp = eec; - if (register_shutdown(nicintel_ee_shutdown, eecp)) - return 1; - } - - if (is_i210(dev->device_id)) if (register_shutdown(nicintel_ee_shutdown_i210, NULL)) return 1; - return register_opaque_master(&opaque_master_nicintel_ee); + return register_opaque_master(&opaque_master_nicintel_ee_i210); + } + + return 1; } -- To view, visit https://review.coreboot.org/c/flashrom/+/33637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I59164ccf54afbbd64a0598282d13e80ff7fd6fa4 Gerrit-Change-Number: 33637 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 4

Change in ...flashrom[master]: Implement IFWI layout reading
by Nico Huber (Code Review) 02 Dec '19

02 Dec '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/31018 Change subject: Implement IFWI layout reading ...................................................................... Implement IFWI layout reading Alas, yet another conflicting command-line option before we overhaul the internal layout handling. Change-Id: I1f1ef4c5d109b81dec7a11bca04ba89204fa84eb Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Makefile M cli_classic.c A ifwi.c M libflashrom.c M libflashrom.h 5 files changed, 463 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/31018/1 diff --git a/Makefile b/Makefile index 1e7db3e..4a1094d 100644 --- a/Makefile +++ b/Makefile @@ -536,7 +536,7 @@ ############################################################################### # Library code. -LIB_OBJS = libflashrom.o layout.o flashrom.o udelay.o programmer.o helpers.o ich_descriptors.o fmap.o +LIB_OBJS = libflashrom.o layout.o flashrom.o udelay.o programmer.o helpers.o ich_descriptors.o fmap.o ifwi.o ############################################################################### # Frontend related stuff. diff --git a/cli_classic.c b/cli_classic.c index 536ef24..f764a6d 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -57,6 +57,7 @@ " --fmap read ROM layout from fmap embedded in ROM\n" " --fmap-file <fmapfile> read ROM layout from fmap in <fmapfile>\n" " --ifd read layout from an Intel Firmware Descriptor\n" + " --ifwi read layout from an Integrated Firmware Image\n" " -i | --image <name> only flash image <name> from flash layout\n" " -o | --output <logfile> log output to <logfile>\n" " --flash-contents <ref-file> assume flash contents to be <ref-file>\n" @@ -100,7 +101,7 @@ struct flashctx *fill_flash; const char *name; int namelen, opt, i, j; - int startchip = -1, chipcount = 0, option_index = 0, force = 0, ifd = 0, fmap = 0; + int startchip = -1, chipcount = 0, option_index = 0, force = 0, ifd = 0, ifwi = 0, fmap = 0; #if CONFIG_PRINT_WIKI == 1 int list_supported_wiki = 0; #endif @@ -110,6 +111,7 @@ enum programmer prog = PROGRAMMER_INVALID; enum { OPTION_IFD = 0x0100, + OPTION_IFWI, OPTION_FMAP, OPTION_FMAP_FILE, OPTION_FLASH_CONTENTS, @@ -129,6 +131,7 @@ {"force", 0, NULL, 'f'}, {"layout", 1, NULL, 'l'}, {"ifd", 0, NULL, OPTION_IFD}, + {"ifwi", 0, NULL, OPTION_IFWI}, {"fmap", 0, NULL, OPTION_FMAP}, {"fmap-file", 1, NULL, OPTION_FMAP_FILE}, {"image", 1, NULL, 'i'}, @@ -238,6 +241,10 @@ fprintf(stderr, "Error: --layout and --ifd both specified. Aborting.\n"); cli_classic_abort_usage(); } + if (ifwi) { + fprintf(stderr, "Error: --layout and --ifwi both specified. Aborting.\n"); + cli_classic_abort_usage(); + } if (fmap) { fprintf(stderr, "Error: --layout and --fmap-file both specified. Aborting.\n"); cli_classic_abort_usage(); @@ -249,12 +256,31 @@ fprintf(stderr, "Error: --layout and --ifd both specified. Aborting.\n"); cli_classic_abort_usage(); } + if (ifwi) { + fprintf(stderr, "Error: --ifwi and --ifd both specified. Aborting.\n"); + cli_classic_abort_usage(); + } if (fmap) { fprintf(stderr, "Error: --fmap-file and --ifd both specified. Aborting.\n"); cli_classic_abort_usage(); } ifd = 1; break; + case OPTION_IFWI: + if (layoutfile) { + fprintf(stderr, "Error: --layout and --ifwi both specified. Aborting.\n"); + cli_classic_abort_usage(); + } + if (ifd) { + fprintf(stderr, "Error: --ifd and --ifwi both specified. Aborting.\n"); + cli_classic_abort_usage(); + } + if (fmap) { + fprintf(stderr, "Error: --fmap-file and --ifwi both specified. Aborting.\n"); + cli_classic_abort_usage(); + } + ifwi = 1; + break; case OPTION_FMAP_FILE: if (fmap) { fprintf(stderr, "Error: --fmap or --fmap-file specified " @@ -265,6 +291,10 @@ fprintf(stderr, "Error: --fmap-file and --ifd both specified. Aborting.\n"); cli_classic_abort_usage(); } + if (ifwi) { + fprintf(stderr, "Error: --fmap-file and --ifwi both specified. Aborting.\n"); + cli_classic_abort_usage(); + } if (layoutfile) { fprintf(stderr, "Error: --fmap-file and --layout both specified. Aborting.\n"); cli_classic_abort_usage(); @@ -282,6 +312,10 @@ fprintf(stderr, "Error: --fmap and --ifd both specified. Aborting.\n"); cli_classic_abort_usage(); } + if (ifwi) { + fprintf(stderr, "Error: --fmap and --ifwi both specified. Aborting.\n"); + cli_classic_abort_usage(); + } if (layoutfile) { fprintf(stderr, "Error: --layout and --fmap both specified. Aborting.\n"); cli_classic_abort_usage(); @@ -452,7 +486,7 @@ goto out; } - if (!ifd && !fmap && process_include_args(get_global_layout())) { + if (!ifd && !ifwi && !fmap && process_include_args(get_global_layout())) { ret = 1; goto out; } @@ -611,6 +645,10 @@ process_include_args(layout))) { ret = 1; goto out_shutdown; + } else if (ifwi && (flashrom_layout_read_from_ifwi(&layout, fill_flash) || + process_include_args(layout))) { + ret = 1; + goto out_shutdown; } else if (fmap && fmapfile) { struct stat s; if (stat(fmapfile, &s) != 0) { diff --git a/ifwi.c b/ifwi.c new file mode 100644 index 0000000..320335a --- /dev/null +++ b/ifwi.c @@ -0,0 +1,359 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2019 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include <stddef.h> +#include <stdint.h> +#include <inttypes.h> +#include <stdbool.h> +#include <stdlib.h> +#include <string.h> + +#include "hwaccess.h" +#include "layout.h" +#include "flash.h" +#include "ifwi.h" + +static size_t bpdt_size(const struct bpdt *const header) +{ + return BPDT_HEADER_LENGTH + header->desc_count * BPDT_ENTRY_LENGTH; +} + +static int deserialize_bpdt_header(struct bpdt *const header, const uint8_t *const from) +{ + header->signature = read_le32(from + 0); + header->desc_count = read_le16(from + 4); + header->version = read_le16(from + 6); + header->xorsum = read_le32(from + 8); + header->ifwi_version = read_le32(from + 12); + + if (header->signature != BPDT_SIGNATURE) { + msg_gerr("IFWI: BPDT signature mismatch. Found 0x%08"PRIx32", expected 0x%08x.\n", + header->signature, BPDT_SIGNATURE); + return -4; + } + if (header->version != 1) { + msg_gerr("IFWI: Unknown BPDT version: %"PRIu32".\n", header->version); + return -3; + } + return 0; +} + +static int deserialize_bpdt_entries(struct bpdt *const bpdt, const uint8_t *const from, const size_t limit) +{ + unsigned int i; + size_t offset; + + for (i = 0, offset = 0; i < bpdt->desc_count; ++i, offset += BPDT_ENTRY_LENGTH) { + bpdt->entries[i].type = read_le16(from + offset + 0); + bpdt->entries[i].flags = read_le16(from + offset + 2); + bpdt->entries[i].offset = read_le32(from + offset + 4); + bpdt->entries[i].size = read_le32(from + offset + 8); + msg_gdbg("IFWI: BPDT entry #%u (0x%04"PRIx16", 0x%04"PRIx16", 0x%08"PRIx32", 0x%08"PRIx32")\n", + i, bpdt->entries[i].type, bpdt->entries[i].flags, + bpdt->entries[i].offset, bpdt->entries[i].size); + + const uint32_t end = bpdt->entries[i].offset + bpdt->entries[i].size; + if (end < bpdt->entries[i].offset) { + msg_gerr("IFWI: BPDT entry overflows 32-bit space; " + "offset 0x%08"PRIx32" size 0x%08"PRIx32"\n", + bpdt->entries[i].offset, bpdt->entries[i].size); + return -4; + } + if (end > limit) { + msg_gerr("IFWI: BPDT entry points outside of the partition: %08"PRIx32":%08"PRIx32"\n", + bpdt->entries[i].offset, end - 1); + return -4; + } + } + return (int)i; +} + +static int read_bpdt(struct bpdt **bpdt, + const size_t flash_offset, const size_t partition_limit, + int (*const read)(void *args, uint8_t *buf, unsigned int start, unsigned int len), + void *const read_args) +{ + uint8_t *buf; + int ret; + + buf = malloc(BPDT_HEADER_LENGTH); + *bpdt = malloc(sizeof(**bpdt)); + if (!buf || !*bpdt) { + msg_gerr("Out of memory!\n"); + ret = -1; + goto _free_bpdt_ret; + } + + if (read(read_args, buf, flash_offset, BPDT_HEADER_LENGTH)) { + ret = -2; + goto _free_bpdt_ret; + } + ret = deserialize_bpdt_header(*bpdt, buf); + if (ret < 0) + goto _free_bpdt_ret; + + buf = realloc_or_free(buf, bpdt_size(*bpdt)); + *bpdt = realloc_or_free(*bpdt, offsetof(struct bpdt, entries) + + (*bpdt)->desc_count * sizeof((*bpdt)->entries[0])); + if (!buf || !*bpdt) { + ret = -1; + goto _free_bpdt_ret; + } + + if (read(read_args, buf + BPDT_HEADER_LENGTH, + flash_offset + BPDT_HEADER_LENGTH, bpdt_size(*bpdt) - BPDT_HEADER_LENGTH)) { + ret = -2; + goto _free_bpdt_ret; + } + ret = deserialize_bpdt_entries(*bpdt, (uint8_t *)buf + BPDT_HEADER_LENGTH, partition_limit); + if (ret < 0) + goto _free_bpdt_ret; + + ret = 0; + goto _free_buf_ret; + +_free_bpdt_ret: + free(*bpdt); +_free_buf_ret: + free(buf); + return ret; +} + +static size_t spd_size(const struct spd *const header) +{ + return header->header_length + header->num_entries * SPD_ENTRY_LENGTH; +} + +static int deserialize_spd_header(struct spd *const header, const uint8_t *const from) +{ + header->marker = read_le32(from + 0); + header->num_entries = read_le32(from + 4); + header->header_version = read_le8 (from + 8); + header->entry_version = read_le8 (from + 9); + header->header_length = read_le8 (from + 10); + header->checksum = read_le8 (from + 11); + memcpy(header->name, from + 12, sizeof(header->name) - 1); + header->name[sizeof(header->name) - 1] = '\0'; + + if (header->marker != SPD_MARKER) { + msg_gerr("IFWI: SPD marker mismatch. Found 0x%08"PRIx32", expected 0x%08x.\n", + header->marker, SPD_MARKER); + return -4; + } + if (header->header_version != 1) { + msg_gerr("IFWI: Unknown SPD header version: %"PRIu8".\n", header->header_version); + return -3; + } + if (header->entry_version != 1) { + msg_gerr("IFWI: Unknown SPD entry version: %"PRIu8".\n", header->entry_version); + return -3; + } + return 0; +} + +static int deserialize_spd_entries(struct spd *const spd, const uint8_t *const from, const size_t limit) +{ + unsigned int i; + size_t offset; + + for (i = 0, offset = 0; i < spd->num_entries; ++i, offset += SPD_ENTRY_LENGTH) { + memcpy(spd->entries[i].name, from + offset, sizeof(spd->entries[i].name) - 1); + spd->entries[i].name[sizeof(spd->entries[i].name) - 1] = '\0'; + spd->entries[i].offset = read_le32(from + offset + 12); + spd->entries[i].length = read_le32(from + offset + 16); + msg_gdbg("IFWI: SPD entry #%u (%s, 0x%08"PRIx32", 0x%08"PRIx32")\n", + i, spd->entries[i].name, spd->entries[i].offset, spd->entries[i].length); + + const uint32_t end = spd->entries[i].offset + spd->entries[i].length; + if (end < spd->entries[i].offset) { + msg_gerr("IFWI: SPD entry overflows 32-bit space; " + "offset 0x%08"PRIx32" size 0x%08"PRIx32"\n", + spd->entries[i].offset, spd->entries[i].length); + return -4; + } + if (end > limit) { + msg_gerr("IFWI: SPD entry points outside of the partition: %08"PRIx32":%08"PRIx32"\n", + spd->entries[i].offset, end - 1); + return -4; + } + } + return (int)i; +} + +static int read_spd(struct spd **spd, + const size_t flash_offset, const size_t partition_limit, + int (*const read)(void *args, uint8_t *buf, unsigned int start, unsigned int len), + void *const read_args) +{ + uint8_t *buf; + int ret; + + buf = malloc(SPD_MIN_HEADER_LENGTH); + *spd = malloc(sizeof(**spd)); + if (!buf || !*spd) { + msg_gerr("Out of memory!\n"); + ret = -1; + goto _free_spd_ret; + } + + if (read(read_args, buf, flash_offset, SPD_MIN_HEADER_LENGTH)) { + ret = -2; + goto _free_spd_ret; + } + ret = deserialize_spd_header(*spd, (uint8_t *)buf); + if (ret < 0) + goto _free_spd_ret; + + buf = realloc_or_free(buf, spd_size(*spd)); + *spd = realloc_or_free(*spd, offsetof(struct spd, entries) + + (*spd)->num_entries * sizeof((*spd)->entries[0])); + if (!buf || !*spd) { + ret = -1; + goto _free_spd_ret; + } + + if (read(read_args, buf + (*spd)->header_length, + flash_offset + (*spd)->header_length, spd_size(*spd) - (*spd)->header_length)) { + ret = -2; + goto _free_spd_ret; + } + ret = deserialize_spd_entries(*spd, (uint8_t *)buf + (*spd)->header_length, partition_limit); + if (ret < 0) + goto _free_spd_ret; + + ret = 0; + goto _free_buf_ret; + +_free_spd_ret: + free(*spd); +_free_buf_ret: + free(buf); + return ret; +} + +static int layout_from_ifwi(struct flashrom_layout **const layout, + const size_t primary_offset, const size_t secondary_offset, + const size_t partition_limit, + int (*const read)(void *args, uint8_t *buf, unsigned int start, unsigned int len), + void *const read_args) +{ + struct bpdt *bpdt; + struct spd *spd; + size_t bpdt_offset, offset; + unsigned int i, j; + int ret = -1; + + if (!secondary_offset) + bpdt_offset = primary_offset; + else + bpdt_offset = secondary_offset; + + ret = read_bpdt(&bpdt, bpdt_offset, partition_limit - primary_offset, read, read_args); + if (ret < 0) + return ret; + + if (!secondary_offset && !(*layout = new_layout(32))) { + ret = -1; + goto _free_bpdt_ret; + } + + ret = add_layout_entry(layout, secondary_offset ? "S-BPDT" : "BPDT", + bpdt_offset, bpdt_offset + bpdt_size(bpdt) - 1); + if (ret < 0) + goto _free_layout_ret; + + for (i = 0; i < bpdt->desc_count; ++i) { + offset = primary_offset + bpdt->entries[i].offset; + + if (!bpdt->entries[i].offset || !bpdt->entries[i].size) { + msg_gdbg("IFWI: Skipping empty BPDT entry #%u of type %"PRIu16".\n", + i, bpdt->entries[i].type); + continue; + } + + switch (bpdt->entries[i].type) { + case 5: + /* recurse into secondary BPDT */ + ret = layout_from_ifwi(layout, primary_offset, offset, + partition_limit, read, read_args); + if (ret) + goto _free_layout_ret; + continue; + case 0: /* Fall through.*/ + case 1: /* Fall through.*/ + case 2: /* Fall through.*/ + case 3: /* Fall through.*/ + case 4: /* Fall through.*/ + case 6: /* Fall through.*/ + case 7: /* Fall through.*/ + case 8: /* Fall through.*/ + case 9: /* Fall through.*/ + case 14: /* Fall through.*/ + case 15: + break; + default: + continue; + } + + ret = read_spd(&spd, offset, partition_limit - offset, read, read_args); + switch (ret) { + case 0: + break; + case -1: /* Fall through. */ + case -2: + goto _free_layout_ret; + default: + continue; + } + + ret = add_layout_entry(layout, spd->name, offset, offset + bpdt->entries[i].size - 1); + if (ret < 0) { + free(spd); + goto _free_layout_ret; + } + for (j = 0; j < spd->num_entries; ++j) { + offset = primary_offset + bpdt->entries[i].offset + + (spd->entries[j].offset & SPD_ENTRY_OFFSET_MASK); + ret = add_layout_entry( + layout, spd->entries[j].name, + offset, offset + spd->entries[j].length - 1); + if (ret < 0) { + free(spd); + goto _free_layout_ret; + } + } + free(spd); + } + + ret = 0; + goto _free_bpdt_ret; + +_free_layout_ret: + free(*layout); +_free_bpdt_ret: + free(bpdt); + return ret; +} + +int layout_from_ifwi_rom(struct flashrom_layout **const layout, + struct flashrom_flashctx *const flashctx, + const size_t flash_offset) +{ + return layout_from_ifwi(layout, flash_offset, 0, flashctx->chip->total_size * 1024, + (int (*)(void *, uint8_t *, unsigned int, unsigned int))flashctx->chip->read, + flashctx); +} diff --git a/libflashrom.c b/libflashrom.c index f90a22c..96e34cc 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -30,6 +30,7 @@ #include "layout.h" #include "hwaccess.h" #include "ich_descriptors.h" +#include "ifwi.h" #include "libflashrom.h" /** @@ -383,6 +384,67 @@ #endif } +/** + * @brief Read a layout from the Intel IFWI in the flash. + * + * @param[out] layout Points to a struct flashrom_layout pointer that + * gets set if the descriptor is read and parsed + * successfully. + * @param[in] flashctx Flash context to read the descriptor from flash. + * + * @return 0 on success, + * 6 if descriptor parsing isn't implemented for the host, + * 3 if the data on flash couldn't be parsed, + * 2 if the data on flash couldn't be read, + * 1 on any other error. + */ +int flashrom_layout_read_from_ifwi(struct flashrom_layout **const layout, + struct flashrom_flashctx *const flashctx) +{ + struct flashrom_layout *ifd_layout; + unsigned int i; + int ret; + + ret = flashrom_layout_read_from_ifd(&ifd_layout, flashctx, NULL, 0); + if (ret) + return ret; + + for (i = 0; i < ifd_layout->num_entries; ++i) { + if (strcmp(ifd_layout->entries[i].name, "bios") == 0) + break; + } + if (i >= ifd_layout->num_entries) { + msg_gerr("Cannot find BIOS region in Intel Firmware Descriptor (IFD).\n"); + ret = 3; + goto _free_ifd_ret; + } + + msg_cinfo("Reading IFWI layout... "); + ret = layout_from_ifwi_rom(layout, flashctx, ifd_layout->entries[i].start); + switch (ret) { + case -4: /* Fall through. */ + case -3: + ret = 3; + break; + case -2: + ret = 2; + break; + case 0: + break; + default: + ret = 1; + break; + } + if (ret) + msg_cinfo("FAILED.\n"); + else + msg_cinfo("done.\n"); + +_free_ifd_ret: + free(ifd_layout); + return ret; +} + static int flashrom_layout_parse_fmap(struct flashrom_layout **layout, struct flashctx *const flashctx, const struct fmap *const fmap) { diff --git a/libflashrom.h b/libflashrom.h index 38c95d2..9ca7ea0 100644 --- a/libflashrom.h +++ b/libflashrom.h @@ -63,6 +63,7 @@ struct flashrom_layout; int flashrom_layout_read_from_ifd(struct flashrom_layout **, struct flashrom_flashctx *, const void *dump, size_t len); +int flashrom_layout_read_from_ifwi(struct flashrom_layout **, struct flashrom_flashctx *); int flashrom_layout_read_fmap_from_rom(struct flashrom_layout **, struct flashrom_flashctx *, off_t offset, size_t length); int flashrom_layout_read_fmap_from_buffer(struct flashrom_layout **layout, -- To view, visit https://review.coreboot.org/c/flashrom/+/31018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1f1ef4c5d109b81dec7a11bca04ba89204fa84eb Gerrit-Change-Number: 31018 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 6

Change in ...flashrom[master]: ifwi: Add definitions for the Integrated Firmware Image format
by Nico Huber (Code Review) 02 Dec '19

02 Dec '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/31017 Change subject: ifwi: Add definitions for the Integrated Firmware Image format ...................................................................... ifwi: Add definitions for the Integrated Firmware Image format The Integrated Firmware Image (IFWI) is used as a partitioning format on some Intel SoCs (e.g. Apollo Lake). It is not tied to NOR flashes, rather to have a common format between different types of boot media. Change-Id: I4bdf47637bfb68560e6d4269f89710572c1bb82a Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- A ifwi.h 1 file changed, 80 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/17/31017/1 diff --git a/ifwi.h b/ifwi.h new file mode 100644 index 0000000..622fccf --- /dev/null +++ b/ifwi.h @@ -0,0 +1,80 @@ +/* + * This file is part of the flashrom project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * The Integrated Firmware Image (IFWI) is used as a partitioning + * format on some Intel SoCs (e.g. Apollo Lake). It is not tied to + * NOR flashes, rather to have a common format between different + * types of boot media. + */ + +#ifndef __IFWI_H__ +#define __IFWI_H__ 1 + +#include <stdint.h> + +#include "layout.h" + +int layout_from_ifwi_rom(struct flashrom_layout **, struct flashrom_flashctx *, const size_t flash_offset); + +/*********** Boot Partition Descriptor Table (BPDT) ***********/ + +#define BPDT_ENTRY_LENGTH 12 + +struct bpdt_entry { /* points to a Sub-Partition */ + uint16_t type; + uint16_t flags; + uint32_t offset; /* from start of Logical Boot Partition */ + uint32_t size; +}; + +#define BPDT_SIGNATURE 0x000055aa +#define BPDT_HEADER_LENGTH 24 + +struct bpdt { + uint32_t signature; + uint16_t desc_count; + uint16_t version; + uint32_t xorsum; /* covers BPDT to S-BPDT (inclusive), iff there is + a redundant Logical Boot Partition, otherwise 0 */ + uint32_t ifwi_version; /* revision of this IFWI build */ + struct bpdt_entry entries[]; +}; + +/**************** Sub-Partition Directory (SPD) ***************/ + +#define SPD_ENTRY_OFFSET_MASK 0x01ffffff +#define SPD_ENTRY_LENGTH 24 + +struct spd_entry { + char name[12 + 1]; /* serialized as 12 chars w/o terminator */ + uint32_t offset; /* from start of the SPD header */ + uint32_t length; +}; + +#define SPD_MARKER 0x44504324 /* $CPD */ +#define SPD_MIN_HEADER_LENGTH 16 + +struct spd { + uint32_t marker; + uint32_t num_entries; + uint8_t header_version; + uint8_t entry_version; + uint8_t header_length; + uint8_t checksum; /* xor-sum covering header + entries */ + char name[4 + 1]; /* serialized as 4 chars w/o terminator */ + struct spd_entry entries[]; +}; + +#endif /* __IFWI_H__ */ -- To view, visit https://review.coreboot.org/c/flashrom/+/31017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4bdf47637bfb68560e6d4269f89710572c1bb82a Gerrit-Change-Number: 31017 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

5 8

Change in ...flashrom[master]: layout: Add interface to create a dynamically growing layout
by Nico Huber (Code Review) 02 Dec '19

02 Dec '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/31014 Change subject: layout: Add interface to create a dynamically growing layout ...................................................................... layout: Add interface to create a dynamically growing layout Another interim solution until we have a better internal layout structure (i.e. linked lists). Change-Id: I0093de58bc7eadc5cd52355937df23c4a6e934ed Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M layout.c M layout.h 2 files changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/14/31014/1 diff --git a/layout.c b/layout.c index c589d17..420a3d9 100644 --- a/layout.c +++ b/layout.c @@ -243,3 +243,54 @@ l->entries[i].start, l->entries[i].end, l->entries[i].name); } } + +static size_t dynlayout_size(unsigned int num_entries) +{ + return sizeof(struct dynamic_layout) + num_entries * sizeof(struct romentry); +} + +struct flashrom_layout *new_layout(unsigned int num_entries) +{ + struct dynamic_layout *const dyn = malloc(dynlayout_size(num_entries)); + if (!dyn) { + msg_gerr("Out of memory!\n"); + return NULL; + } + + memset(dyn, 0x00, sizeof(*dyn)); + dyn->base.entries = (void *)((uint8_t *)dyn + sizeof(*dyn)); + dyn->allocated = num_entries; + + return &dyn->base; +} + +int add_layout_entry(struct flashrom_layout **const l, const char *const name, + const size_t start, const size_t end) +{ + struct dynamic_layout *dyn; + + if (!*l) + *l = new_layout(8); + if (!*l) + return -1; + + dyn = (void *)*l; + + if (dyn->base.num_entries >= dyn->allocated) { + const unsigned int allocate = (dyn->allocated ? : 1) * 2; + dyn = realloc(dyn, dynlayout_size(allocate)); + if (!dyn) + return -1; + dyn->base.entries = (void *)((uint8_t *)dyn + sizeof(*dyn)); + dyn->allocated = allocate; + *l = (void *)dyn; + } + + const unsigned int i = dyn->base.num_entries++; + memset(&dyn->base.entries[i], 0x00, sizeof(dyn->base.entries[i])); + dyn->base.entries[i].start = start; + dyn->base.entries[i].end = end; + snprintf(dyn->base.entries[i].name, sizeof(dyn->base.entries[i].name), "%s", name); + + return 0; +} diff --git a/layout.h b/layout.h index a10cbb4..4227e92 100644 --- a/layout.h +++ b/layout.h @@ -54,6 +54,12 @@ struct romentry entry; }; +struct dynamic_layout { + struct flashrom_layout base; + /* number of (pre)allocated entries */ + unsigned int allocated; +}; + struct flashrom_layout *get_global_layout(void); struct flashrom_flashctx; const struct flashrom_layout *get_layout(const struct flashrom_flashctx *const flashctx); @@ -62,4 +68,7 @@ void report_layout(const struct flashrom_layout *); +struct flashrom_layout *new_layout(unsigned int num_entries); +int add_layout_entry(struct flashrom_layout **, const char *name, size_t start, size_t end); + #endif /* !__LAYOUT_H__ */ -- To view, visit https://review.coreboot.org/c/flashrom/+/31014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0093de58bc7eadc5cd52355937df23c4a6e934ed Gerrit-Change-Number: 31014 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

2 3

Change in flashrom[master]: dediprog.c: Add id parameter to dediprog programmer
by Ryan O'Leary (Code Review) 15 Nov '19

15 Nov '19

Ryan O'Leary has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34160 ) Change subject: dediprog.c: Add id parameter to dediprog programmer ...................................................................... dediprog.c: Add id parameter to dediprog programmer When multiple dediprog programmers are connected, the 'id' parameter allows you to specify which one to use. The id is a string like SF012345 or DP012345. The value is printed on a sticker on the back of the dediprog. This is an improvement over the 'device' parameter which is based on enumeration order and changes when you plug/unplug devices or reboot the machine. To find the id without the sticker, run flashrom with the -V option. This prints the ids as they are enumerated. Alternatively, with dpcmd, you can use the --list-device-id and --fix-device commands to list and write device ids respectively. Note this only supports SF100 at the moment, but SF600 support is possible with more work. Change-Id: I4281213ab02131feb5d47bf66118a001cec0d219 Signed-off-by: Ryan O'Leary <ryanoleary(a)google.com> --- M dediprog.c 1 file changed, 133 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/60/34160/1 diff --git a/dediprog.c b/dediprog.c index 8029b64..1d10b24 100644 --- a/dediprog.c +++ b/dediprog.c @@ -823,6 +823,46 @@ return 0; } +/* Read the id from the dediprog. This should return the numeric part of the + * serial number found on a sticker on the back of the dediprog. Note this + * number is stored in writable eeprom, so it could get out of sync. Also note, + * this function only supports SF100 at this time, but SF600 support is not too + * much different. + * @return the id on success, -1 on failure + */ +static int dediprog_read_id(void) +{ + int ret; + uint8_t buf[3]; + + ret = libusb_control_transfer(dediprog_handle, REQTYPE_OTHER_IN, + 0x7, /* request */ + 0, /* value */ + 0xEF00, /* index */ + buf, sizeof(buf), + DEFAULT_TIMEOUT); + if (ret != sizeof(buf)) { + msg_perr("Failed to read dediprog id, error %d!\n", ret); + return -1; + } + + return buf[0] << 16 | buf[1] << 8 | buf[2]; +} + +/* Return the prefix to display in front of the id. These two characters also + * appear on the sticker even though they can be derived from the numerical + * part. + * @id a dediprog's id + * @return either "DP" or "SF" + */ +static const char* dediprog_id_prefix(int id) { + /* This is so the id matches dpcmd. */ + if (id < 600000) { + return "DP"; + } + return "SF"; +} + /* * This command presumably sets the voltage for the SF100 itself (not the * SPI flash). Only use this command with firmware older than V6.0.0. Newer @@ -997,9 +1037,11 @@ int dediprog_init(void) { - char *voltage, *device, *spispeed, *target_str; + char *voltage, *id_str, *device, *spispeed, *target_str; int spispeed_idx = 1; int millivolt = 3500; + int id = -1; /* -1 defaults to enumeration order */ + int found_id; long usedevice = 0; long target = FLASH_TYPE_APPLICATION_FLASH_1; int i, ret; @@ -1029,9 +1071,37 @@ msg_pinfo("Setting voltage to %i mV\n", millivolt); } + id_str = extract_programmer_param("id"); + if (id_str) { + char prefix0, prefix1; + const char *prefix; + if (sscanf(id_str, "%c%c%d", &prefix0, &prefix1, &id) != 3) { + msg_perr("Error: Could not parse dediprog 'id'.\n"); + msg_perr("Expected a string like SF012345 or DP012345.\n"); + free(id_str); + return 1; + } + if (id < 0 || id >= 0x1000000) { + msg_perr("Error: id %s is out of range!\n", id_str); + free(id_str); + return 1; + } + prefix = dediprog_id_prefix(id); + if (strlen(prefix) != 2 || prefix[0] != prefix0 || prefix[1] != prefix1) { + msg_perr("Error: %s is an invalid id!\n", id_str); + free(id_str); + return 1; + } + msg_pinfo("Will search for dediprog id %s%06d.\n", dediprog_id_prefix(id), id); + } + free(id_str); + device = extract_programmer_param("device"); if (device) { char *dev_suffix; + if (id != -1) { + msg_perr("Error: Cannot use 'id' and 'device'.\n"); + } errno = 0; usedevice = strtol(device, &dev_suffix, 10); if (errno != 0 || device == dev_suffix) { @@ -1097,25 +1167,69 @@ const uint16_t vid = devs_dediprog[0].vendor_id; const uint16_t pid = devs_dediprog[0].device_id; - dediprog_handle = usb_dev_get_by_vid_pid_number(usb_ctx, vid, pid, (unsigned int) usedevice); - if (!dediprog_handle) { - msg_perr("Could not find a Dediprog programmer on USB.\n"); - libusb_exit(usb_ctx); - return 1; + for (;;) { + /* Notice we can only call dediprog_read_id() after + * libusb_set_configuration() and libusb_claim_interface(). When + * searching by id and either configuration or claim fails + * (usually the device is in use by another instance of + * flashrom), the device is skipped and the next device is + * tried. + */ + dediprog_handle = usb_dev_get_by_vid_pid_number(usb_ctx, vid, pid, (unsigned int) usedevice); + if (!dediprog_handle) { + msg_perr("Could not find a Dediprog programmer on USB.\n"); + libusb_exit(usb_ctx); + return 1; + } + ret = libusb_set_configuration(dediprog_handle, 1); + if (ret != 0) { + msg_perr("Could not set USB device configuration: %i %s\n", + ret, libusb_error_name(ret)); + libusb_close(dediprog_handle); + if (id != -1) { + usedevice++; + continue; + } + libusb_exit(usb_ctx); + return 1; + } + ret = libusb_claim_interface(dediprog_handle, 0); + if (ret < 0) { + msg_perr("Could not claim USB device interface %i: %i %s\n", + 0, ret, libusb_error_name(ret)); + libusb_close(dediprog_handle); + if (id != -1) { + usedevice++; + continue; + } + libusb_exit(usb_ctx); + return 1; + } + + /* Read the dediprog's id. The value is only used (besides + * logging) when searching by id. + */ + found_id = dediprog_read_id(); + if (id != -1) { + if (found_id < 0) { + msg_perr("Could not read id.\n"); + libusb_release_interface(dediprog_handle, 0); + libusb_close(dediprog_handle); + usedevice++; + continue; + } + msg_pinfo("Found dediprog id %s%06d.\n", dediprog_id_prefix(found_id), found_id); + if (found_id != id) { + libusb_release_interface(dediprog_handle, 0); + libusb_close(dediprog_handle); + usedevice++; + continue; + } + } + break; } - ret = libusb_set_configuration(dediprog_handle, 1); - if (ret != 0) { - msg_perr("Could not set USB device configuration: %i %s\n", ret, libusb_error_name(ret)); - libusb_close(dediprog_handle); - libusb_exit(usb_ctx); - return 1; - } - ret = libusb_claim_interface(dediprog_handle, 0); - if (ret < 0) { - msg_perr("Could not claim USB device interface %i: %i %s\n", 0, ret, libusb_error_name(ret)); - libusb_close(dediprog_handle); - libusb_exit(usb_ctx); - return 1; + if (found_id >= 0) { + msg_pinfo("Using dediprog id %s%06d.\n", dediprog_id_prefix(found_id), found_id); } if (register_shutdown(dediprog_shutdown, NULL)) -- To view, visit https://review.coreboot.org/c/flashrom/+/34160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4281213ab02131feb5d47bf66118a001cec0d219 Gerrit-Change-Number: 34160 Gerrit-PatchSet: 1 Gerrit-Owner: Ryan O'Leary Gerrit-MessageType: newchange

2 11

Change in flashrom[master]: flashchips: Add missing N25Q/MT25Q 1.8v variants
by Jacob Creedon (Code Review) 11 Nov '19

11 Nov '19

Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34491 ) Change subject: flashchips: Add missing N25Q/MT25Q 1.8v variants ...................................................................... flashchips: Add missing N25Q/MT25Q 1.8v variants This adds missing 1.8v variants for the 256Mb and 512Mb capacities for N25Q and MT25Q devices. Only the MT25QU512 has been tested in hardware, all other variants added are marked as untested. Signed-off-by: Jacob Creedon <jcreedon(a)google.com> Change-Id: I85630e4f6c0aa3b261f9871b7d363dad278b997e --- M flashchips.c 1 file changed, 178 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/91/34491/1 diff --git a/flashchips.c b/flashchips.c index d25f7a2..5424a04 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10545,6 +10545,46 @@ { .vendor = "Micron/Numonyx/ST", + .name = "N25Q256..1E", /* ..1E = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q256__1E, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32768 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron/Numonyx/ST", .name = "N25Q256..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -10585,6 +10625,46 @@ { .vendor = "Micron/Numonyx/ST", + .name = "N25Q512..1E", /* ..1E = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q512__1E, + .total_size = 65536, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {65536 * 1024, 1} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron/Numonyx/ST", .name = "N25Q512..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -10674,6 +10754,55 @@ { .vendor = "Micron", + .name = "MT25QU256", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q256__1E, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32768 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, { + .eraseblocks = { {32768 * 1024, 1} }, + .block_erase = spi_block_erase_60, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron", .name = "MT25QL512", /* L = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, @@ -10722,6 +10851,55 @@ }, { + .vendor = "Micron", + .name = "MT25QU512", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q512__1E, + .total_size = 65536, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 16384} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 2048} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 2048} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 1024} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {65536 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, { + .eraseblocks = { {65536 * 1024, 1} }, + .block_erase = spi_block_erase_60, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { .vendor = "MoselVitelic", .name = "V29C51000B", .bustype = BUS_PARALLEL, -- To view, visit https://review.coreboot.org/c/flashrom/+/34491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I85630e4f6c0aa3b261f9871b7d363dad278b997e Gerrit-Change-Number: 34491 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com> Gerrit-MessageType: newchange

4 13

Change in flashrom[master]: flashchips: Add N25Q00A devices
by Jacob Creedon (Code Review) 14 Oct '19

14 Oct '19

Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34521 ) Change subject: flashchips: Add N25Q00A devices ...................................................................... flashchips: Add N25Q00A devices This adds the 1Gb N25Q00A device in both the 1.8v and 3v variants. This is implemented from the datasheet and is marked as untested. Signed-off-by: Jacob Creedon <jcreedon(a)google.com> Change-Id: If36880f37746c95a97c8122a8f2fd0aecede5e8e --- M flashchips.c 1 file changed, 80 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/34521/1 diff --git a/flashchips.c b/flashchips.c index 021ae6c..5d292f1 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10304,6 +10304,86 @@ { .vendor = "Micron/Numonyx/ST", + .name = "N25Q00A..1G", /* ..1G = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q00A__1G, + .total_size = 131072, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32768 * 1024, 4} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron/Numonyx/ST", + .name = "N25Q00A..3G", /* ..3G = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q00A__3G, + .total_size = 131072, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32768 * 1024, 4} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron/Numonyx/ST", .name = "N25Q016", .bustype = BUS_SPI, .manufacture_id = ST_ID, -- To view, visit https://review.coreboot.org/c/flashrom/+/34521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If36880f37746c95a97c8122a8f2fd0aecede5e8e Gerrit-Change-Number: 34521 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com> Gerrit-MessageType: newchange

2 2

Change in flashrom[master]: flashchips: Fix part names for N25Q512 and N25Q00A
by Jacob Creedon (Code Review) 14 Oct '19

14 Oct '19

Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34520 ) Change subject: flashchips: Fix part names for N25Q512 and N25Q00A ...................................................................... flashchips: Fix part names for N25Q512 and N25Q00A For the N25Q512 and N25Q00A, the 1G and 3G are used instead of 1E and 3E to represent 1.8v and 3v respectively. Signed-off-by: Jacob Creedon <jcreedon(a)google.com> Change-Id: I289c33f7293f47b9449907350654cd6183c778d4 --- M flashchips.c M flashchips.h 2 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/20/34520/1 diff --git a/flashchips.c b/flashchips.c index 3a0da8d..021ae6c 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10625,10 +10625,10 @@ { .vendor = "Micron/Numonyx/ST", - .name = "N25Q512..1E", /* ..1E = 1.8V, uniform 64KB/4KB blocks/sectors */ + .name = "N25Q512..1G", /* ..1G = 1.8V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q512__1E, + .model_id = ST_N25Q512__1G, .total_size = 65536, .page_size = 256, /* supports SFDP */ @@ -10665,10 +10665,10 @@ { .vendor = "Micron/Numonyx/ST", - .name = "N25Q512..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ + .name = "N25Q512..3G", /* ..3G = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q512__3E, + .model_id = ST_N25Q512__3G, .total_size = 65536, .page_size = 256, /* supports SFDP */ @@ -10708,7 +10708,7 @@ .name = "MT25QL01G", /* L = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q00A__3E, + .model_id = ST_N25Q00A__3G, .total_size = 131072, .page_size = 256, /* supports SFDP */ @@ -10754,7 +10754,7 @@ .name = "MT25QU01G", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q00A__1E, + .model_id = ST_N25Q00A__1G, .total_size = 131072, .page_size = 256, /* supports SFDP */ @@ -11070,7 +11070,7 @@ .name = "MT25QL512", /* L = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q512__3E, + .model_id = ST_N25Q512__3G, .total_size = 65536, .page_size = 256, /* supports SFDP */ @@ -11119,7 +11119,7 @@ .name = "MT25QU512", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q512__1E, + .model_id = ST_N25Q512__1G, .total_size = 65536, .page_size = 256, /* supports SFDP */ diff --git a/flashchips.h b/flashchips.h index e53e0df..0dcf735 100644 --- a/flashchips.h +++ b/flashchips.h @@ -866,10 +866,10 @@ #define ST_N25Q128__1E 0xBB18 /* N25Q128/MT25QU128, 1.8V, (uniform sectors expected) */ #define ST_N25Q256__3E 0xBA19 /* N25Q256/MT25QL256, 3.0V, (uniform sectors expected) */ #define ST_N25Q256__1E 0xBB19 /* N25Q256/MT25QU256, 1.8V, (uniform sectors expected) */ -#define ST_N25Q512__3E 0xBA20 /* N25Q512/MT25QL512, 3.0V, (uniform sectors expected) */ -#define ST_N25Q512__1E 0xBB20 /* N25Q512/MT25QU512, 1.8V, (uniform sectors expected) */ -#define ST_N25Q00A__3E 0xBA21 /* N25Q00A/MT25QL01G, 3.0V, (uniform sectors expected) */ -#define ST_N25Q00A__1E 0xBB21 /* N25Q00A/MT25QU01G, 1.8V, (uniform sectors expected) */ +#define ST_N25Q512__3G 0xBA20 /* N25Q512/MT25QL512, 3.0V, (uniform sectors expected) */ +#define ST_N25Q512__1G 0xBB20 /* N25Q512/MT25QU512, 1.8V, (uniform sectors expected) */ +#define ST_N25Q00A__3G 0xBA21 /* N25Q00A/MT25QL01G, 3.0V, (uniform sectors expected) */ +#define ST_N25Q00A__1G 0xBB21 /* N25Q00A/MT25QU01G, 1.8V, (uniform sectors expected) */ #define ST_MT25QL02G 0xBA22 /* MT25QL02G, 3.0V, (uniform sectors expected) */ #define ST_MT25QU02G 0xBB22 /* MT25QU02G, 1.8V, (uniform sectors expected) */ #define ST_NP5Q032 0xDA16 /* Phase-change memory (PCM), 3V */ -- To view, visit https://review.coreboot.org/c/flashrom/+/34520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I289c33f7293f47b9449907350654cd6183c778d4 Gerrit-Change-Number: 34520 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com> Gerrit-MessageType: newchange

3 5

Change in flashrom[master]: flashchips: Add missing MT25Q capacities
by Jacob Creedon (Code Review) 14 Oct '19

14 Oct '19

Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34492 ) Change subject: flashchips: Add missing MT25Q capacities ...................................................................... flashchips: Add missing MT25Q capacities This adds the 128Mb, 1Gb, and 2Gb capacities of the MT25Q devices. All of these are implemented via the datasheet and should work but are untested in hardware. Signed-off-by: Jacob Creedon <jcreedon(a)google.com> Change-Id: Ice6ea9426361afc25d4b731e2e3079edf234fdda --- M flashchips.c M flashchips.h 2 files changed, 274 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/92/34492/1 diff --git a/flashchips.c b/flashchips.c index 5424a04..6b553fb 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10705,6 +10705,270 @@ { .vendor = "Micron", + .name = "MT25QL01G", /* L = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q00A__3E, + .total_size = 131072, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {131072 * 1024, 1} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron", + .name = "MT25QU01G", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q00A__1E, + .total_size = 131072, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {131072 * 1024, 1} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron", + .name = "MT25QL02G", /* L = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_MT25QL02G, + .total_size = 262144, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 65536} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 65536} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 8192} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 8192} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 4096} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 4096} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {262144 * 1024, 1} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron", + .name = "ST_MT25QU02G", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q00A__1E, + .total_size = 262144, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 65536} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 65536} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 8192} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 8192} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 4096} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 4096} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {262144 * 1024, 1} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron", + .name = "MT25QU128", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q128__1E, + .total_size = 16384, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16384 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, { + .eraseblocks = { {16384 * 1024, 1} }, + .block_erase = spi_block_erase_60, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron", + .name = "MT25QL128", /* L = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q128__3E, + .total_size = 16384, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16384 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, { + .eraseblocks = { {16384 * 1024, 1} }, + .block_erase = spi_block_erase_60, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron", .name = "MT25QL256", /* L = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, diff --git a/flashchips.h b/flashchips.h index 006b95e..e53e0df 100644 --- a/flashchips.h +++ b/flashchips.h @@ -862,13 +862,16 @@ #define ST_N25Q032__1E 0xBB16 /* N25Q032, 1.8V, (uniform sectors expected) */ #define ST_N25Q064__3E 0xBA17 /* N25Q064, 3.0V, (uniform sectors expected) */ #define ST_N25Q064__1E 0xBB17 /* N25Q064, 1.8V, (uniform sectors expected) */ -#define ST_N25Q128__3E 0xBA18 /* N25Q128, 3.0V, (uniform sectors expected) */ -#define ST_N25Q128__1E 0xBB18 /* N25Q128, 1.8V, (uniform sectors expected) */ -#define ST_N25Q256__3E 0xBA19 /* N25Q256, 3.0V, (uniform sectors expected) */ -#define ST_N25Q256__1E 0xBB19 /* N25Q256, 1.8V, (uniform sectors expected) */ -#define ST_N25Q512__3E 0xBA20 /* N25Q512, 3.0V, (uniform sectors expected) */ -#define ST_N25Q512__1E 0xBB20 /* N25Q512, 1.8V, (uniform sectors expected) */ -#define ST_N25Q00A__3E 0xBA21 /* N25Q00A, 3.0V, (uniform sectors expected) */ +#define ST_N25Q128__3E 0xBA18 /* N25Q128/MT25QL128, 3.0V, (uniform sectors expected) */ +#define ST_N25Q128__1E 0xBB18 /* N25Q128/MT25QU128, 1.8V, (uniform sectors expected) */ +#define ST_N25Q256__3E 0xBA19 /* N25Q256/MT25QL256, 3.0V, (uniform sectors expected) */ +#define ST_N25Q256__1E 0xBB19 /* N25Q256/MT25QU256, 1.8V, (uniform sectors expected) */ +#define ST_N25Q512__3E 0xBA20 /* N25Q512/MT25QL512, 3.0V, (uniform sectors expected) */ +#define ST_N25Q512__1E 0xBB20 /* N25Q512/MT25QU512, 1.8V, (uniform sectors expected) */ +#define ST_N25Q00A__3E 0xBA21 /* N25Q00A/MT25QL01G, 3.0V, (uniform sectors expected) */ +#define ST_N25Q00A__1E 0xBB21 /* N25Q00A/MT25QU01G, 1.8V, (uniform sectors expected) */ +#define ST_MT25QL02G 0xBA22 /* MT25QL02G, 3.0V, (uniform sectors expected) */ +#define ST_MT25QU02G 0xBB22 /* MT25QU02G, 1.8V, (uniform sectors expected) */ #define ST_NP5Q032 0xDA16 /* Phase-change memory (PCM), 3V */ #define ST_NP5Q064 0xDA17 /* Phase-change memory (PCM), 3V */ #define ST_NP5Q128 0xDA18 /* Phase-change memory (PCM), 3V */ -- To view, visit https://review.coreboot.org/c/flashrom/+/34492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ice6ea9426361afc25d4b731e2e3079edf234fdda Gerrit-Change-Number: 34492 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: Add support for M95M02-A125
by Konstantin Grudnev (Code Review) 04 Oct '19

04 Oct '19

Konstantin Grudnev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34496 ) Change subject: Add support for M95M02-A125 ...................................................................... Add support for M95M02-A125 Automotive 2 Mbit (256KiB) serial SPI bus EEPROM PREW tested successfully with use of ch341a programmer on Linux host 5.2.0-1-MANJARO x86_64 Signed-off-by: Konstantin Grudnev <grudnevkv(a)gmail.com> Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b --- M chipdrivers.h M flashchips.c M flashchips.h M spi.h M spi25.c 5 files changed, 102 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/34496/1 diff --git a/chipdrivers.h b/chipdrivers.h index e380878..0b4435c 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -34,6 +34,7 @@ int probe_spi_res1(struct flashctx *flash); int probe_spi_res2(struct flashctx *flash); int probe_spi_res3(struct flashctx *flash); +int probe_spi_st95(struct flashctx *flash); int probe_spi_at25f(struct flashctx *flash); int spi_write_enable(struct flashctx *flash); int spi_write_disable(struct flashctx *flash); @@ -51,6 +52,7 @@ int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_dc(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigned int blocklen); erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode); int spi_chip_write_1(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int spi_nbyte_read(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); diff --git a/flashchips.c b/flashchips.c index 166af6a..44875c6 100644 --- a/flashchips.c +++ b/flashchips.c @@ -14104,6 +14104,33 @@ }, { + .vendor = "ST", + .name = "M95M02", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M95M02, + .total_size = 256, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_st95, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 256 * 1024, 1 } }, + .block_erase = spi_block_erase_emulation, + } + }, + + .printlock = spi_prettyprint_status_register_bp1_srwd, + .unlock = spi_disable_blockprotect_bp1_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2500, 5500}, + }, + + { .vendor = "Sanyo", .name = "LE25FU106B", .bustype = BUS_SPI, diff --git a/flashchips.h b/flashchips.h index 006b95e..d1eed91 100644 --- a/flashchips.h +++ b/flashchips.h @@ -851,6 +851,12 @@ #define ST_M58WR032KT 0x8814 #define ST_M58WR064KB 0x8811 #define ST_M58WR064KT 0x8810 + +/* 00h ST Manufacturer code ST_ID*/ +/* 01h SPI Family code 0x00*/ +/* 02h Memory Density code ST_M95XXX */ +#define ST_M95M02 0x0012 /* ST M95XXX 2Mbit (256KiB) */ + #define ST_MT28GU01G___1 0x88B0 #define ST_MT28GU01G___2 0x88B1 #define ST_MT28GU256___1 0x8901 diff --git a/spi.h b/spi.h index 0073c71..9f199f3 100644 --- a/spi.h +++ b/spi.h @@ -28,6 +28,12 @@ /* INSIZE may be 0x04 for some chips*/ #define JEDEC_RDID_INSIZE 0x03 +/* Some ST M95X model */ +#define ST_M95_RDID 0x83 +#define ST_M95_RDID_OUTSIZE 0x04 /* 8b op, 24bit addr where size >64KiB */ +#define ST_M95_RDID_INSIZE 0x03 + + /* Some Atmel AT25F* models have bit 3 as don't care bit in commands */ #define AT25F_RDID 0x15 /* 0x15 or 0x1d */ #define AT25F_RDID_OUTSIZE 0x01 diff --git a/spi25.c b/spi25.c index 2a1d492..ec35585 100644 --- a/spi25.c +++ b/spi25.c @@ -21,6 +21,7 @@ #include <stddef.h> #include <string.h> #include <stdbool.h> +#include <stdlib.h> #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" @@ -262,6 +263,32 @@ return 1; } +/* Only used for some stm95080 and higher chip. */ +int probe_spi_st95(struct flashctx *flash) +{ + /* ST_M95_RDID_OUTSIZE depends on size of the flash and + * not all ST_M95XXX have RDID + */ + static const unsigned char cmd[ST_M95_RDID_OUTSIZE] = {ST_M95_RDID}; + unsigned char readarr[ST_M95_RDID_INSIZE]; + uint32_t id1, id2; + + spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); + + id1 = readarr[0]; // manufacture id + id2 = readarr[2]; // model id + + msg_ginfo("RDID[%s: id1 0x%02x, id2 0x%02x, " + "L 0x%02x, M 0x%02x, H 0x%02x]\n", + __func__, flash->chip->manufacture_id, flash->chip->model_id, + readarr[0], readarr[1], readarr[2]); + + if (id1 == flash->chip->manufacture_id && id2 == flash->chip->model_id) + return 1; + + return 0; +} + /* Only used for some Atmel chips. */ int probe_spi_at25f(struct flashctx *flash) { @@ -440,6 +467,13 @@ return result ? result : status; } +static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) +{ + const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_WRITE && spi_master_4ba(flash); + const uint8_t op = native_4ba ? JEDEC_BYTE_PROGRAM_4BA : JEDEC_BYTE_PROGRAM; + return spi_write_cmd(flash, op, native_4ba, addr, bytes, len, 10); +} + static int spi_chip_erase_60(struct flashctx *flash) { /* This usually takes 1-85s, so wait in 1s steps. */ @@ -577,6 +611,33 @@ return spi_write_cmd(flash, 0xdc, true, addr, NULL, 0, 100 * 1000); } +/* some chips don't have erase function */ +int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigned int blocklen) +{ + unsigned int i; + const unsigned int erase_len = flash->chip->page_size; + uint8_t *erased_contents = NULL; + int result = 0; + + erased_contents = (uint8_t*) malloc(erase_len * sizeof(uint8_t)); + if (!erased_contents) { + msg_cerr("Out of memory!\n"); + return 1; + } + + memset(erased_contents, ERASED_VALUE(flash), erase_len * sizeof(uint8_t)); + msg_cinfo("\n"); + for (i = addr; i < blocklen; i+=erase_len) { + if (spi_nbyte_program(flash, i, erased_contents, erase_len)) { + result = 1; + break; + } + } + + free(erased_contents); + return result; +} + erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode) { switch(opcode){ @@ -619,13 +680,6 @@ } } -static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) -{ - const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_WRITE && spi_master_4ba(flash); - const uint8_t op = native_4ba ? JEDEC_BYTE_PROGRAM_4BA : JEDEC_BYTE_PROGRAM; - return spi_write_cmd(flash, op, native_4ba, addr, bytes, len, 10); -} - int spi_nbyte_read(struct flashctx *flash, unsigned int address, uint8_t *bytes, unsigned int len) { -- To view, visit https://review.coreboot.org/c/flashrom/+/34496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b Gerrit-Change-Number: 34496 Gerrit-PatchSet: 1 Gerrit-Owner: Konstantin Grudnev <grudnevkv(a)gmail.com> Gerrit-MessageType: newchange

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