December 2019 - flashrom-gerrit

Change in flashrom[master]: Match -c parameter against patterns in chip names

by Ryan O'Leary (Code Review)

Ryan O'Leary has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/37723 ) Change subject: Match -c parameter against patterns in chip names ...................................................................... Match -c parameter against patterns in chip names This includes patterns such as "EN29GL064H/L", "Am29F002(N)BB" and "A25LQ032/A25LQ32A". This was inspired by a breakage in one of my scripts. The script hard-coded "-c CHIPX". When upstream changed the chip name to "CHIPX/CHIPY", my script broke. By recognizing this pattern, the -c parameter is more resilient to these types of changes. Since an exact match on the whole name takes priority (the current behavior), this should not break anyone's workflow. Change-Id: Iae00bb1108f2d5a0c10977cff63f9348b9fc017f Signed-off-by: Ryan O'Leary <ryanoleary(a)google.com> --- M cli_classic.c 1 file changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/23/37723/1 diff --git a/cli_classic.c b/cli_classic.c index 73cc417..43aac0b 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -103,6 +103,68 @@ return 0; } +/* + * Return 1 if the chip name matches the pattern, otherwise 0. + * + * The pattern may be: + * 1. A single slash followed by a single character. + * Ex: "EN29GL064H/L" matches "EN29GL064H" and "EN29GL064L". + * 2. One character in parens. + * Ex: "Am29F002(N)BB" matches "Am29F002BB" and "Am29F002NBB". + * Ex: "EN29F002(A)(N)B" matches four different chip names. + * 3. A slash-separated list. + * Ex: "A25LQ032/A25LQ32A" matches "A25LQ032" and "A25LQ32A". + * Ex: "MX25L12835F/MX25L12845E/MX25L12865E" matches "MX25L12835F", "MX25L12845E" and "MX25L12865E". + * + * #2 may be nested in #3, for example "W29C010(M)/W29C011A/W29EE011/W29EE012". + */ +static int chip_name_match_pattern(const char *pattern, const char *chip) { + int plen = strlen(pattern); + int clen = strlen(chip); + + if (plen < 3 || clen < 3) { + return 0; + } + + /* Single slash followed by single character. */ + if (pattern[plen-2] == '/') { + for (int pidx = 0; pidx < plen - 2; pidx++) + if (pattern[pidx] == '/') + return 0; + return plen - 2 == clen && + strncmp(pattern, chip, plen - 3) == 0 && + (pattern[plen-1] == chip[clen-1] || + pattern[plen-3] == chip[clen-1]); + } + + int cidx = 0; + for (int pidx = 0; pidx < plen; pidx++) { + if (pattern[pidx] == '/') { + /* Check for termination. */ + if (cidx == clen) + break; + cidx = 0; /* Reset. */ + } else if (pattern[pidx] == '(') { + if (pidx + 2 >= plen || + pattern[pidx+1] == ')' || + pattern[pidx+1] == '(' || + pattern[pidx+2] != ')') + return 0; /* Invalid pattern. */ + if (pattern[pidx+1] == chip[cidx]) + cidx++; + pidx += 2; + } else if (pattern[pidx] == chip[cidx]) { + cidx++; + } else { + /* Reset to next slash. */ + while (pidx < plen && pattern[pidx] != '/') + pidx++; + cidx = 0; + } + } + return cidx == clen; +} + int main(int argc, char *argv[]) { const struct flashchip *chip = NULL; @@ -421,15 +483,22 @@ } /* Does a chip with the requested name exist in the flashchips array? */ if (chip_to_probe) { + /* First check for exact match. */ for (chip = flashchips; chip && chip->name; chip++) if (!strcmp(chip->name, chip_to_probe)) break; + /* Failing that, perform a pattern match. */ + if (!chip || !chip->name) + for (chip = flashchips; chip && chip->name; chip++) + if (chip_name_match_pattern(chip->name, chip_to_probe)) + break; if (!chip || !chip->name) { msg_cerr("Error: Unknown chip '%s' specified.\n", chip_to_probe); msg_gerr("Run flashrom -L to view the hardware supported in this flashrom version.\n"); ret = 1; goto out; } + msg_gdbg("Using chip \"%s\".\n", chip->name); /* Keep chip around for later usage in case a forced read is requested. */ } -- To view, visit https://review.coreboot.org/c/flashrom/+/37723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iae00bb1108f2d5a0c10977cff63f9348b9fc017f Gerrit-Change-Number: 37723 Gerrit-PatchSet: 1 Gerrit-Owner: Ryan O'Leary <ryanoleary(a)google.com> Gerrit-MessageType: newchange

1 year, 10 months

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Change in flashrom[master]: pcidev.c: Factor out pcidev_validate() into pure fn

by Edward O'Callaghan (Code Review)

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/37264 ) Change subject: pcidev.c: Factor out pcidev_validate() into pure fn ...................................................................... pcidev.c: Factor out pcidev_validate() into pure fn This makes writing unit-tests easier. Change-Id: Ia2718f1f40851d3122741cd0e50b0c2b647b727a Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M pcidev.c 1 file changed, 29 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/37264/1 diff --git a/pcidev.c b/pcidev.c index 54c1fd3..4012840 100644 --- a/pcidev.c +++ b/pcidev.c @@ -148,6 +148,33 @@ return (uintptr_t)addr; } +static uintptr_t pcidev_validate(struct pci_dev *dev, int bar, const struct dev_entry *devs) +{ + unsigned i; + + /* Check against list of supported devices. */ + for (i = 0; devs[i].device_name != NULL; i++) { + if (dev->device_id != devs[i].device_id) + continue; + + msg_pinfo("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", + devs[i].vendor_name, devs[i].device_name, + dev->vendor_id, dev->device_id, dev->bus, dev->dev, + dev->func); + + if (devs[i].status == NT) + msg_pinfo("===\nThis PCI device is UNTESTED. Please report the 'flashrom -p " + "xxxx' output\n" + "to flashrom(a)flashrom.org if it works for you. Please add the name " + "of your\n" + "PCI device to the subject. Thank you for your help!\n===\n"); + + + return pcidev_readbar(dev, bar); + } + return 0; +} + static int pcidev_shutdown(void *data) { if (pacc == NULL) { @@ -183,12 +210,10 @@ struct pci_dev *pcidev_init(const struct dev_entry *devs, int bar) { struct pci_dev *dev; - struct pci_dev *found_dev = NULL; struct pci_filter filter; char *pcidev_bdf; char *msg = NULL; int found = 0; - int i; uintptr_t addr = 0; if (pci_init_common() != 0) @@ -207,30 +232,10 @@ for (dev = pacc->devices; dev; dev = dev->next) { if (pci_filter_match(&filter, dev)) { - /* Check against list of supported devices. */ - for (i = 0; devs[i].device_name != NULL; i++) - if ((dev->vendor_id == devs[i].vendor_id) && - (dev->device_id == devs[i].device_id)) - break; - /* Not supported, try the next one. */ - if (devs[i].device_name == NULL) - continue; - - msg_pdbg("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", devs[i].vendor_name, - devs[i].device_name, dev->vendor_id, dev->device_id, dev->bus, dev->dev, - dev->func); - if (devs[i].status == NT) - msg_pinfo("===\nThis PCI device is UNTESTED. Please report the 'flashrom -p " - "xxxx' output\n" - "to flashrom(a)flashrom.org if it works for you. Please add the name " - "of your\n" - "PCI device to the subject. Thank you for your help!\n===\n"); - /* FIXME: We should count all matching devices, not * just those with a valid BAR. */ - if ((addr = pcidev_readbar(dev, bar)) != 0) { - found_dev = dev; + if ((addr = pcidev_validate(dev, bar, devs)) != 0) { found++; } } @@ -246,7 +251,7 @@ return NULL; } - return found_dev; + return dev; } enum pci_write_type { -- To view, visit https://review.coreboot.org/c/flashrom/+/37264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia2718f1f40851d3122741cd0e50b0c2b647b727a Gerrit-Change-Number: 37264 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

1 year, 10 months

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Change in flashrom[master]: chipset_enable.c: Enable Tiger Lake U support

by Edward O'Callaghan (Code Review)

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/37777 ) Change subject: chipset_enable.c: Enable Tiger Lake U support ...................................................................... chipset_enable.c: Enable Tiger Lake U support Did a basic local test with --flash-name and -r bios and ran strings to see if the bios contained reasonable data. BUG=b:146089922 Change-Id: I2c13e0173c9b5e17d2ae197f4a4ab9aa2825c1b3 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M chipset_enable.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/37777/1 diff --git a/chipset_enable.c b/chipset_enable.c index b55852c..d5a2f03 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1996,6 +1996,7 @@ {0x8086, 0x9d56, B_S, NT, "Intel", "Kaby Lake Y Premium", enable_flash_pch100}, {0x8086, 0x9d58, B_S, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100}, {0x8086, 0x9d84, B_S, DEP, "Intel", "Cannon Lake U Premium", enable_flash_pch300}, + {0x8086, 0xa082, B_FS, NT, "Intel", "Tiger Lake U", enable_flash_pch300}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, {0x8086, 0xa143, B_S, NT, "Intel", "H110", enable_flash_pch100}, -- To view, visit https://review.coreboot.org/c/flashrom/+/37777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2c13e0173c9b5e17d2ae197f4a4ab9aa2825c1b3 Gerrit-Change-Number: 37777 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

1 year, 10 months

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Change in flashrom[master]: stlinkv3_spi: Move a declaration out of for-loop head

by Nico Huber (Code Review)

Hello Angel Pons, Miklós Márton, David Hendricks, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/38034 to review the following change. Change subject: stlinkv3_spi: Move a declaration out of for-loop head ...................................................................... stlinkv3_spi: Move a declaration out of for-loop head GCC 4.8 wants an explicit `-std=c99` or something for this to work. It seems easier to keep the common declaration style. Change-Id: Ic0819f82169df4d66cc949494229b0749c06e8f6 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M stlinkv3_spi.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/38034/1 diff --git a/stlinkv3_spi.c b/stlinkv3_spi.c index 02e87bc..7338911 100644 --- a/stlinkv3_spi.c +++ b/stlinkv3_spi.c @@ -333,6 +333,7 @@ int rc = 0; int actual_length = 0; uint32_t rw_status = 0; + unsigned int i; if (stlinkv3_spi_set_SPI_NSS(SPI_NSS_LOW)) { msg_perr("Failed to set the NSS pin to low\n"); @@ -346,7 +347,7 @@ command[2] = (uint8_t)write_cnt; command[3] = (uint8_t)(write_cnt >> 8); - for (unsigned int i = 0; (i < 8) && (i < write_cnt); i++) + for (i = 0; (i < 8) && (i < write_cnt); i++) command[4+i] = write_arr[i]; rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_OUT, -- To view, visit https://review.coreboot.org/c/flashrom/+/38034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic0819f82169df4d66cc949494229b0749c06e8f6 Gerrit-Change-Number: 38034 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Miklós Márton <martonmiklosqdev(a)gmail.com> Gerrit-MessageType: newchange

1 year, 11 months

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Change in flashrom[master]: Add -- to make clean

by Ryan O'Leary (Code Review)

Ryan O'Leary has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/37776 ) Change subject: Add -- to make clean ...................................................................... Add -- to make clean Somehow, I ended up with a file name "-c.d". I probably made it by mistake. This change lets "make clean" be a bit more resilient to files such as these. Change-Id: I2517ffac975f3df75f706350a07f189a98a11b7c Signed-off-by: Ryan O'Leary <ryanoleary(a)google.com> --- M Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/76/37776/1 diff --git a/Makefile b/Makefile index 518d41b..fa66910 100644 --- a/Makefile +++ b/Makefile @@ -1129,7 +1129,7 @@ # This includes all frontends and libflashrom. # We don't use EXEC_SUFFIX here because we want to clean everything. clean: - rm -f $(PROGRAM) $(PROGRAM).exe libflashrom.a *.o *.d $(PROGRAM).8 $(PROGRAM).8.html $(BUILD_DETAILS_FILE) + rm -f -- $(PROGRAM) $(PROGRAM).exe libflashrom.a *.o *.d $(PROGRAM).8 $(PROGRAM).8.html $(BUILD_DETAILS_FILE) @+$(MAKE) -C util/ich_descriptors_tool/ clean distclean: clean -- To view, visit https://review.coreboot.org/c/flashrom/+/37776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2517ffac975f3df75f706350a07f189a98a11b7c Gerrit-Change-Number: 37776 Gerrit-PatchSet: 1 Gerrit-Owner: Ryan O'Leary <ryanoleary(a)google.com> Gerrit-MessageType: newchange

1 year, 11 months

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Change in flashrom[master]: Add support for STLINK V3 debugger/programmer via it's SPI bridge

by Miklós Márton (Code Review)

Miklós Márton has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34661 ) Change subject: Add support for STLINK V3 debugger/programmer via it's SPI bridge ...................................................................... Add support for STLINK V3 debugger/programmer via it's SPI bridge Change-Id: Icffab87ac8f2c570187ed753ec70f054541873a4 Signed-off-by: Miklós Márton <martonmiklosqdev(a)gmail.com> --- M Makefile M flashrom.8.tmpl M flashrom.c M meson.build M programmer.h A stlinkv3_spi.c 6 files changed, 670 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/61/34661/1 diff --git a/Makefile b/Makefile index 545e84a..58dc86a 100644 --- a/Makefile +++ b/Makefile @@ -190,6 +190,11 @@ else override CONFIG_CH341A_SPI = no endif +ifeq ($(CONFIG_STLINKV3_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_STLINKV3_SPI=yes +else +override CONFIG_STLINKV3_SPI = no +endif # libjaylink is also not available for DOS ifeq ($(CONFIG_JLINK_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_JLINK_SPI=yes @@ -353,6 +358,11 @@ else override CONFIG_PICKIT2_SPI = no endif +ifeq ($(CONFIG_STLINKV3_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_STLINKV3_SPI=yes +else +override CONFIG_STLINKV3_SPI = no +endif ifeq ($(CONFIG_CH341A_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_CH341A_SPI=yes else @@ -618,6 +628,9 @@ # Always enable PICkit2 SPI dongles for now. CONFIG_PICKIT2_SPI ?= yes +# Always enable STLink V3 +CONFIG_STLINKV3_SPI ?= yes + # Always enable dummy tracing for now. CONFIG_DUMMY ?= yes @@ -696,6 +709,7 @@ override CONFIG_DIGILENT_SPI = no override CONFIG_DEVELOPERBOX_SPI = no override CONFIG_PICKIT2_SPI = no +override CONFIG_STLINKV3_SPI = no endif ifeq ($(CONFIG_ENABLE_LIBPCI_PROGRAMMERS), no) override CONFIG_INTERNAL = no @@ -863,6 +877,12 @@ NEED_LIBUSB1 += CONFIG_PICKIT2_SPI endif +ifeq ($(CONFIG_STLINKV3_SPI), yes) +FEATURE_CFLAGS += -D'CONFIG_STLINKV3_SPI=1' +PROGRAMMER_OBJS += stlinkv3_spi.o +NEED_LIBUSB1 += CONFIG_STLINKV3_SPI +endif + ifneq ($(NEED_LIBFTDI), ) FTDILIBS := $(call debug_shell,[ -n "$(PKG_CONFIG_LIBDIR)" ] && export PKG_CONFIG_LIBDIR="$(PKG_CONFIG_LIBDIR)" ; $(PKG_CONFIG) --libs libftdi1 || $(PKG_CONFIG) --libs libftdi || printf "%s" "-lftdi -lusb") FEATURE_CFLAGS += $(call debug_shell,grep -q "FT232H := yes" .features && printf "%s" "-D'HAVE_FT232H=1'") diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 30dc97d..5f518a4 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -333,6 +333,8 @@ .sp .BR "* jlink_spi" " (for SPI flash ROMs attached to SEGGER J-Link and compatible devices)" .sp +.BR "* stlinkv3_spi" " (for SPI flash ROMs attached to STMicroelectronics STLINK V3 devices)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER-SPECIFIC INFORMATION @@ -1186,6 +1188,31 @@ .sp syntax where \fBfrequency\fP is the SPI clock frequency in kHz. The maximum speed depends on the device in use. +SS +.BR "stlinkv3_spi " programmer +.IP +This module supports SPI flash programming through the STMicroelectronics +STLINK V3 programmer/debugger's SPI bridge interface +.sp +.B " flashrom \-p stlinkv3_spi" +.sp +If there is more than one compatible device connected, you can select which one +should be used by specifying its serial number with the +.sp +.B " flashrom \-p stlinkv3_spi:serial=number" +.sp +syntax where +.B number +is the serial number of the device (which can be found for example in the +output of lsusb -v). +.sp +The SPI speed can be selected by using the +.sp +.B " flashrom \-p stlinkv3_spi:spispeed=frequency" +.sp +syntax where \fBfrequency\fP is the SPI clock frequency in kHz. +If the passed frequency is not supported by the adapter the nearest lower +supported frequency will be used. .SS .SH EXAMPLES diff --git a/flashrom.c b/flashrom.c index cb1dca6..fdb77b6 100644 --- a/flashrom.c +++ b/flashrom.c @@ -449,6 +449,18 @@ }, #endif +#if CONFIG_STLINKV3_SPI == 1 + { + .name = "stlinkv3_spi", + .type = USB, + .devs.dev = devs_stlinkv3_spi, + .init = stlinkv3_spi_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + {0}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; diff --git a/meson.build b/meson.build index e1b6c16..2b5ef2e 100644 --- a/meson.build +++ b/meson.build @@ -62,6 +62,7 @@ config_satasii = get_option('config_satasii') config_serprog = get_option('config_serprog') config_usbblaster_spi = get_option('config_usbblaster_spi') +config_stlinkv3_spi = get_option('config_stlinkv3_spi') cargs = [] deps = [] @@ -272,6 +273,10 @@ srcs += 'usbblaster_spi.c' cargs += '-DCONFIG_USBBLASTER_SPI=1' endif +if config_stlinkv3_spi + srcs += 'stlinkv3_spi.c' + cargs += '-DCONFIG_STLINKV3_SPI=1' +endif # bitbanging SPI infrastructure if config_bitbang_spi diff --git a/programmer.h b/programmer.h index f4e8b46..1843426 100644 --- a/programmer.h +++ b/programmer.h @@ -121,6 +121,9 @@ #if CONFIG_JLINK_SPI == 1 PROGRAMMER_JLINK_SPI, #endif +#if CONFIG_STLINKV3_SPI == 1 + PROGRAMMER_STLINKV3_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -498,6 +501,12 @@ extern const struct dev_entry devs_pickit2_spi[]; #endif +/* stlinkv3_spi.c */ +#if CONFIG_STLINKV3_SPI == 1 +int stlinkv3_spi_init(void); +extern const struct dev_entry devs_stlinkv3_spi[]; +#endif + /* rayer_spi.c */ #if CONFIG_RAYER_SPI == 1 int rayer_spi_init(void); diff --git a/stlinkv3_spi.c b/stlinkv3_spi.c new file mode 100644 index 0000000..817d28f --- /dev/null +++ b/stlinkv3_spi.c @@ -0,0 +1,597 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2019 Miklós Márton martonmiklosqdev(a)gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/* + * Driver for programming SPI flash chips using the SPI port + * of the STMicroelectronics's STLINK-V3 programmer/debugger. + * + * The implementation is inspired by the ST's STLINK-V3-BRIDGE C++ API: + * https://www.st.com/en/development-tools/stlink-v3-bridge.html + */ + +#include "flash.h" +#include "programmer.h" +#include "spi.h" + +#include <libusb.h> +#include <limits.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> + +typedef enum { + FW_VERSION_OK, + FW_VERSION_OLD, +} fw_version_check_result_t; + +typedef enum { + SPI_BAUDRATEPRESCALER_2 = 0, + SPI_BAUDRATEPRESCALER_4 = 1, + SPI_BAUDRATEPRESCALER_8 = 2, + SPI_BAUDRATEPRESCALER_16 = 3, + SPI_BAUDRATEPRESCALER_32 = 4, + SPI_BAUDRATEPRESCALER_64 = 5, + SPI_BAUDRATEPRESCALER_128 = 6, + SPI_BAUDRATEPRESCALER_256 = 7 +} SPI_prescaler_t; + +typedef enum { + SPI_DIRECTION_2LINES_FULLDUPLEX = 0, + SPI_DIRECTION_2LINES_RXONLY = 1, + SPI_DIRECTION_1LINE_RX = 2, + SPI_DIRECTION_1LINE_TX = 3 +} SPI_dir_t; + +typedef enum { + SPI_MODE_SLAVE = 0, + SPI_MODE_MASTER = 1 +} SPI_mode_t; + +typedef enum { + SPI_DATASIZE_16B = 0, + SPI_DATASIZE_8B = 1 +} SPI_datasize_t; + +typedef enum { + SPI_CPOL_LOW = 0, + SPI_CPOL_HIGH = 1 +} SPI_CPOL_t; + +typedef enum { + SPI_CPHA_1EDGE = 0, + SPI_CPHA_2EDGE = 1 +} SPI_CPHA_t; + +typedef enum { + SPI_FIRSTBIT_LSB = 0, + SPI_FIRSTBIT_MSB = 1 +} SPI_firstbit_t; + +typedef enum { + SPI_NSS_SOFT = 0, + SPI_NSS_HARD = 1 +} SPI_NSS_t; + +typedef enum { + SPI_NSS_LOW = 0, + SPI_NSS_HIGH = 1 +} SPI_NSS_Level_t; + +#define ST_GETVERSION_EXT 0xFB + +#define STLINK_BRIDGE_COMMAND 0xFC +#define STLINK_BRIDGE_CLOSE 0x01 +#define STLINK_BRIDGE_GET_RWCMD_STATUS 0x02 +#define STLINK_BRIDGE_GET_CLOCK 0x03 +#define STLINK_BRIDGE_INIT_SPI 0x20 +#define STLINK_BRIDGE_WRITE_SPI 0x21 +#define STLINK_BRIDGE_READ_SPI 0x22 +#define STLINK_BRIDGE_CS_SPI 0x23 + +#define STLINK_BRIDGE_SPI_ERROR 0x02 + +#define STLINK_SPI_COM 0x02 + +#define STLINK_EP_OUT 0x06 +#define STLINK_EP_IN 0x86 + +#define FIRMWARE_BRIDGE_STLINK_V3_LAST_VERSION 3 + +#define USB_TIMEOUT 5000 + +const struct dev_entry devs_stlinkv3_spi[] = { + {0x0483, 0x374F, OK, "STMicroelectronics", "STLINK-V3"}, + {0} +}; + +static struct libusb_context *usb_ctx; +static libusb_device_handle *stlinkv3_handle; + +/** + * @param[out] bridge_input_clk Current input frequency in kHz of the given com. + */ +static int stlinkv3_get_clk(uint32_t *bridge_input_clk) +{ + uint8_t command[16]; + uint8_t answer[12]; + int actualLength = 0; + int rc = 0; + + if (bridge_input_clk == NULL) + return -1; + + memset(command, 0, sizeof(command)); + memset(answer, 0, sizeof(answer)); + + command[0] = STLINK_BRIDGE_COMMAND; + command[1] = STLINK_BRIDGE_GET_CLOCK; + command[2] = STLINK_SPI_COM; + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_OUT, + command, sizeof(command), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(command)) { + msg_perr("Failed to issue the STLINK_BRIDGE_GET_CLOCK command: '%s'\n", + libusb_error_name(rc)); + return -1; + } + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_IN, + answer, sizeof(answer), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(answer)) { + msg_perr("Failed to get STLINK_BRIDGE_GET_CLOCK answer: '%s'\n", + libusb_error_name(rc)); + return -1; + } + + *bridge_input_clk = (uint32_t)answer[4] + | (uint32_t)answer[5]<<8 + | (uint32_t)answer[6]<<16 + | (uint32_t)answer[7]<<24; + return 0; + +} + +static int stlinkv3_spi_calc_prescaler(uint16_t reqd_freq_in_kHz, + SPI_prescaler_t *prescaler, + uint16_t *calculated_freq_in_kHz) +{ + uint32_t bridge_clk_in_kHz; + uint32_t calculated_prescaler = 1; + uint16_t prescaler_value; + + if (stlinkv3_get_clk(&bridge_clk_in_kHz)) + return -1; + + calculated_prescaler = bridge_clk_in_kHz/reqd_freq_in_kHz; + // Apply a smaller frequency if not exact + if (calculated_prescaler <= 2) { + *prescaler = SPI_BAUDRATEPRESCALER_2; + prescaler_value = 2; + } else if (calculated_prescaler <= 4) { + *prescaler = SPI_BAUDRATEPRESCALER_4; + prescaler_value = 4; + } else if (calculated_prescaler <= 8) { + *prescaler = SPI_BAUDRATEPRESCALER_8; + prescaler_value = 8; + } else if (calculated_prescaler <= 16) { + *prescaler = SPI_BAUDRATEPRESCALER_16; + prescaler_value = 16; + } else if (calculated_prescaler <= 32) { + *prescaler = SPI_BAUDRATEPRESCALER_32; + prescaler_value = 32; + } else if (calculated_prescaler <= 64) { + *prescaler = SPI_BAUDRATEPRESCALER_64; + prescaler_value = 64; + } else if (calculated_prescaler <= 128) { + *prescaler = SPI_BAUDRATEPRESCALER_128; + prescaler_value = 128; + } else if (calculated_prescaler <= 256) { + *prescaler = SPI_BAUDRATEPRESCALER_256; + prescaler_value = 256; + } else { + // smaller frequency not possible + *prescaler = SPI_BAUDRATEPRESCALER_256; + prescaler_value = 256; + } + + *calculated_freq_in_kHz = bridge_clk_in_kHz / prescaler_value; + + return 0; +} + +static int stlinkv3_check_version(fw_version_check_result_t *result) +{ + uint8_t answer[12]; + uint8_t command[16]; + int actualLength = 0; + int rc = 0; + + memset(command, 0, sizeof(command)); + + command[0] = ST_GETVERSION_EXT; + command[1] = 0x80; + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_OUT, + command, sizeof(command), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(command)) { + msg_perr("Failed to issue the ST_GETVERSION_EXT command: '%s'\n", + libusb_error_name(rc)); + return -1; + } + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_IN, + answer, sizeof(answer), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(answer)) { + msg_perr("Failed to retrive the ST_GETVERSION_EXT answer: '%s'\n", + libusb_error_name(rc)); + return -1; + } + + msg_pinfo("Connected to STLink V3 with bridge FW version: %d\n", answer[4]); + *result = answer[4] >= FIRMWARE_BRIDGE_STLINK_V3_LAST_VERSION + ? FW_VERSION_OK + : FW_VERSION_OLD; + return 0; +} + +static int stlinkv3_spi_open(uint16_t reqested_freq_in_kHz) +{ + uint8_t command[16]; + uint8_t answer[2]; + uint16_t SCK_freq_in_kHz; + int actualLength = 0; + int rc = 0; + SPI_prescaler_t prescaler; + fw_version_check_result_t fw_check_result; + + if (stlinkv3_check_version(&fw_check_result)) { + msg_perr("Failed to query FW version"); + return -1; + } + + if (fw_check_result != FW_VERSION_OK) { + msg_pinfo("Your STLink V3 has too old version of the bridge interface\n" + "Please update the firmware with the " + "STSW-LINK007 which can be downloaded from here:\n" + "https://www.st.com/en/development-tools/stsw-link007.html"); + return -1; + } + + if (stlinkv3_spi_calc_prescaler(reqested_freq_in_kHz, + &prescaler, + &SCK_freq_in_kHz)) { + msg_perr("Failed to calculate SPI clock prescaler"); + return -1; + } + msg_pinfo("SCK frequency set to %d kHz\n", SCK_freq_in_kHz); + + memset(command, 0, sizeof(command)); + memset(answer, 0, sizeof(answer)); + + command[0] = STLINK_BRIDGE_COMMAND; + command[1] = STLINK_BRIDGE_INIT_SPI; + command[2] = SPI_DIRECTION_2LINES_FULLDUPLEX; + command[3] = (SPI_MODE_MASTER + | (SPI_CPHA_1EDGE << 1) + | (SPI_CPOL_LOW << 2) + | (SPI_FIRSTBIT_MSB << 3)); + command[4] = SPI_DATASIZE_8B; + command[5] = SPI_NSS_SOFT; + command[6] = (uint8_t)prescaler; + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_OUT, + command, sizeof(command), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED && actualLength != sizeof(command)) { + msg_perr("Failed to issue the STLINK_BRIDGE_INIT_SPI command: '%s'\n", + libusb_error_name(rc)); + return -1; + } + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_IN, + answer, sizeof(answer), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(answer)) { + msg_perr("Failed to retrive the STLINK_BRIDGE_INIT_SPI answer: '%s'\n", + libusb_error_name(rc)); + return -1; + } + return 0; +} + +static int stlinkv3_get_last_readwrite_status(uint32_t *status) +{ + uint8_t command[16]; + uint16_t answer[4]; + int rc = 0; + int actualLength = 0; + + memset(command, 0, sizeof(command)); + memset(answer, 0, sizeof(answer)); + + command[0] = STLINK_BRIDGE_COMMAND; + command[1] = STLINK_BRIDGE_GET_RWCMD_STATUS; + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_OUT, + command, sizeof(command), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(command)) { + msg_perr("Failed to issue the STLINK_BRIDGE_GET_RWCMD_STATUS command: '%s'\n", + libusb_error_name(rc)); + return -1; + } + + rc = libusb_bulk_transfer(stlinkv3_handle, + STLINK_EP_IN, + (uint8_t *)answer, + sizeof(answer), + &actualLength, + USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(answer)) { + msg_perr("Failed to retrive the STLINK_BRIDGE_GET_RWCMD_STATUS answer: '%s'\n", + libusb_error_name(rc)); + return -1; + } + + *status = (uint32_t)answer[2] | (uint32_t)answer[3]<<16; + return 0; +} + +static int stlinkv3_spi_set_SPI_NSS(SPI_NSS_Level_t NSS_level) +{ + uint8_t command[16]; + uint8_t answer[2]; + int rc = 0; + int actualLength = 0; + + memset(command, 0, sizeof(command)); + memset(answer, 0, sizeof(answer)); + + command[0] = STLINK_BRIDGE_COMMAND; + command[1] = STLINK_BRIDGE_CS_SPI; + command[2] = (uint8_t) (NSS_level); + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_OUT, + command, sizeof(command), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(command)) { + msg_perr("Failed to issue the STLINK_BRIDGE_CS_SPI command: '%s'\n", + libusb_error_name(rc)); + return -1; + } + + rc = libusb_bulk_transfer(stlinkv3_handle, + STLINK_EP_IN, + (uint8_t *)answer, + sizeof(answer), + &actualLength, + USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(answer)) { + msg_perr("Failed to retrive the STLINK_BRIDGE_CS_SPI answer: '%s'\n", + libusb_error_name(rc)); + return -1; + } + return 0; +} + +static int stlinkv3_spi_transmit(struct flashctx *flash, + unsigned int write_cnt, + unsigned int read_cnt, + const unsigned char *write_arr, + unsigned char *read_arr) +{ + uint8_t command[16]; + int rc = 0 ; + int actualLength = 0; + uint32_t rw_status = 0; + + if (stlinkv3_spi_set_SPI_NSS(SPI_NSS_LOW)) { + msg_perr("Failed to set the NSS pin to low\n"); + return -1; + } + + memset(command, 0, sizeof(command)); + + command[0] = STLINK_BRIDGE_COMMAND; + command[1] = STLINK_BRIDGE_WRITE_SPI; + command[2] = (uint8_t)write_cnt; + command[3] = (uint8_t)(write_cnt >> 8); + + for (unsigned int i = 0; (i < 8) && (i < write_cnt); i++) + command[4+i] = write_arr[i]; + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_OUT, + command, sizeof(command), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(command)) { + msg_perr("Failed to issue the STLINK_BRIDGE_WRITE_SPI command: '%s'\n", + libusb_error_name(rc)); + goto transmit_err; + } + + if (write_cnt > 8) { + rc = libusb_bulk_transfer(stlinkv3_handle, + STLINK_EP_OUT, + (unsigned char *)&write_arr[8], + (unsigned int)(write_cnt - 8), + &actualLength, + USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != (write_cnt - 8)) { + msg_perr("Failed to send the data after the " + "STLINK_BRIDGE_WRITE_SPI command: '%s'\n", + libusb_error_name(rc)); + goto transmit_err; + } + } + + if (stlinkv3_get_last_readwrite_status(&rw_status)) + return -1; + + if (rw_status != 0) { + msg_perr("SPI read/write failure: %d\n", rw_status); + goto transmit_err; + } + + if (read_cnt) { + command[1] = STLINK_BRIDGE_READ_SPI; + command[2] = (uint8_t)read_cnt; + command[3] = (uint8_t)(read_cnt >> 8); + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_OUT, + command, sizeof(command), + &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(command)) { + msg_perr("Failed to issue the STLINK_BRIDGE_READ_SPI command: '%s'\n", + libusb_error_name(rc)); + goto transmit_err; + } + + rc = libusb_bulk_transfer(stlinkv3_handle, + STLINK_EP_IN, + (unsigned char *)read_arr, + (int)read_cnt, + &actualLength, + USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != read_cnt) { + msg_perr("Failed to retrive the STLINK_BRIDGE_READ_SPI answer: '%s'\n", + libusb_error_name(rc)); + goto transmit_err; + } + } + + if (stlinkv3_get_last_readwrite_status(&rw_status)) + goto transmit_err; + + if (rw_status != 0) { + msg_perr("SPI read/write failure: %d\n", rw_status); + goto transmit_err; + } + + if (stlinkv3_spi_set_SPI_NSS(SPI_NSS_HIGH)) { + msg_perr("Failed to set the NSS pin to high\n"); + return -1; + } + return 0; + +transmit_err: + if (stlinkv3_spi_set_SPI_NSS(SPI_NSS_HIGH)) + msg_perr("Failed to set the NSS pin to high\n"); + return -1; +} + +static int stlinkv3_spi_shutdown(void *data) +{ + uint8_t command[16]; + uint8_t answer[2]; + int actualLength = 0; + int rc = 0; + + memset(command, 0, sizeof(command)); + memset(answer, 0, sizeof(answer)); + + command[0] = STLINK_BRIDGE_COMMAND; + command[1] = STLINK_BRIDGE_CLOSE; + command[2] = STLINK_SPI_COM; + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_OUT, + command, sizeof(command), &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(command)) + msg_perr("Failed to issue the STLINK_BRIDGE_CLOSE command: '%s'\n", + libusb_error_name(rc)); + + rc = libusb_bulk_transfer(stlinkv3_handle, STLINK_EP_IN, + answer, sizeof(answer), &actualLength, USB_TIMEOUT); + if (rc != LIBUSB_TRANSFER_COMPLETED || actualLength != sizeof(answer)) + msg_perr("Failed to retrive the STLINK_BRIDGE_CLOSE answer: '%s'\n", + libusb_error_name(rc)); + + libusb_close(stlinkv3_handle); + libusb_exit(usb_ctx); + + return 0; +} + +static const struct spi_master spi_programmer_stlinkv3 = { + .max_data_read = UINT16_MAX, + .max_data_write = UINT16_MAX, + .command = stlinkv3_spi_transmit, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, +}; + +int stlinkv3_spi_init(void) +{ + uint16_t sck_freq_kHz = 1000; // selecting 1 MHz SCK is a good bet + char *speed_str = NULL; + char *serialno = NULL; + char *endptr = NULL; + + libusb_init(&usb_ctx); + if (!usb_ctx) { + msg_perr("Could not initialize libusb!\n"); + return 1; + } + + serialno = extract_programmer_param("serial"); + if (serialno) + msg_pdbg("Opening STLINK-V3 with serial: %s\n", serialno); + stlinkv3_handle = usb_dev_get_by_vid_pid_serial(usb_ctx, + devs_stlinkv3_spi[0].vendor_id, devs_stlinkv3_spi[0].device_id, serialno); + + if (!stlinkv3_handle) { + if (serialno) + msg_perr("No STLINK-V3 seems to be connected with serial %s\n", serialno); + else + msg_perr("Could not find any connected STLINK-V3\n"); + free(serialno); + goto err_exit; + } + free(serialno); + + speed_str = extract_programmer_param("spispeed"); + if (speed_str) { + sck_freq_kHz = strtoul(speed_str, &endptr, 0); + if (*endptr) { + msg_perr("The spispeed parameter passed with invalid format: %s\n", + speed_str); + msg_perr("Please pass the parameter with a simple number in kHz\n"); + return -1; + } + free(speed_str); + } + + if (stlinkv3_spi_open(sck_freq_kHz)) + goto err_exit; + + if (register_shutdown(stlinkv3_spi_shutdown, NULL)) + goto err_exit; + + if (register_spi_master(&spi_programmer_stlinkv3)) + goto err_exit; + + return 0; + +err_exit: + libusb_exit(usb_ctx); + return 1; +} -- To view, visit https://review.coreboot.org/c/flashrom/+/34661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Icffab87ac8f2c570187ed753ec70f054541873a4 Gerrit-Change-Number: 34661 Gerrit-PatchSet: 1 Gerrit-Owner: Miklós Márton <martonmiklosqdev(a)gmail.com> Gerrit-MessageType: newchange

1 year, 11 months

4
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Change in flashrom[master]: It's added support for ST95XXX chips . The following chipsets have be...

by David Hendricks (Code Review)

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/37893 ) Change subject: It's added support for ST95XXX chips . The following chipsets have been tested for read, erase and write operations: [ STM95080 STM95160 STM95320 STM95640 STM95128 STM95256 STM95512 STM95M01 STM95M02 ] ...................................................................... It's added support for ST95XXX chips . The following chipsets have been tested for read, erase and write operations: [ STM95080 STM95160 STM95320 STM95640 STM95128 STM95256 STM95512 STM95M01 STM95M02 ] The chipsets(except st95xxx with literal D) can't respond with RDID instruction and for this reason was added FEATURE_IDENTITY_MISSING feature. The feature works with "force" option and disable rdid checking during read operation. Also It's emulates erase operation for chipsets which don't support it. Known issue: It doesn't support chipset STM95040 because memory size lower then 1K and the chipset has special instruction set for read operation. Change-Id: I4a983a2f375c7023d28b9e762d24b44566e59612 Signed-off-by: Nikolay Nikolaev <evrinoma(a)gmail.com> --- M Makefile M chipdrivers.h M cli_classic.c M flash.h M flashchips.c M flashchips.h M flashrom.c M spi.h M spi25.c D spi95.c 10 files changed, 371 insertions(+), 96 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/37893/1 diff --git a/Makefile b/Makefile index 518d41b..d345d23 100644 --- a/Makefile +++ b/Makefile @@ -555,7 +555,7 @@ CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \ sst28sf040.o 82802ab.o \ sst49lfxxxc.o sst_fwhub.o edi.o flashchips.o spi.o spi25.o spi25_statusreg.o \ - spi95.o opaque.o sfdp.o en29lv640b.o at45db.o + opaque.o sfdp.o en29lv640b.o at45db.o ############################################################################### # Library code. diff --git a/chipdrivers.h b/chipdrivers.h index cb1e877..2afa191 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -34,6 +34,7 @@ int probe_spi_res1(struct flashctx *flash); int probe_spi_res2(struct flashctx *flash); int probe_spi_res3(struct flashctx *flash); +int probe_spi_st95(struct flashctx *flash); int probe_spi_at25f(struct flashctx *flash); int spi_write_enable(struct flashctx *flash); int spi_write_disable(struct flashctx *flash); @@ -51,6 +52,7 @@ int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_dc(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigned int blocklen); erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode); int spi_chip_write_1(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int spi_nbyte_read(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); @@ -202,8 +204,5 @@ int edi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int edi_probe_kb9012(struct flashctx *flash); -/* spi95.c */ -int probe_spi_st95(struct flashctx *flash); -int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigned int blocklen); #endif /* !__CHIPDRIVERS_H__ */ diff --git a/cli_classic.c b/cli_classic.c index 73cc417..08c9316 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -468,7 +468,8 @@ for (j = 0; j < registered_master_count; j++) { startchip = 0; while (chipcount < (int)ARRAY_SIZE(flashes)) { - startchip = probe_flash(&registered_masters[j], startchip, &flashes[chipcount], 0); + startchip = probe_flash(&registered_masters[j], startchip, &flashes[chipcount], (chip_to_probe) && force ); + if (startchip == -1) break; chipcount++; @@ -511,7 +512,7 @@ "chip, using the first one.\n"); for (j = 0; j < registered_master_count; j++) { mst = &registered_masters[j]; - startchip = probe_flash(mst, 0, &flashes[0], 1); + startchip = probe_flash(mst, 0, &flashes[0], 2); if (startchip != -1) break; } diff --git a/flash.h b/flash.h index 1a9bd9f..94a2548 100644 --- a/flash.h +++ b/flash.h @@ -140,6 +140,8 @@ */ #define FEATURE_ERASED_ZERO (1 << 17) #define FEATURE_NO_ERASE (1 << 18) +#define FEATURE_3_BYTE_ADDR_LEN (1 << 19) +#define FEATURE_IDENTITY_MISSING (1 << 20) #define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff) diff --git a/flashchips.c b/flashchips.c index 65dda0e..09f1809 100644 --- a/flashchips.c +++ b/flashchips.c @@ -14808,6 +14808,33 @@ .voltage = {3000, 3600}, /* Also has 12V fast program & erase */ }, + { + .vendor = "ST", + .name = "M95M01", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M95M01, + .total_size = 128, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_IDENTITY_MISSING, + .tested = TEST_OK_PREW, + .probe = probe_spi_st95, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_emulation, + } + }, + + .printlock = spi_prettyprint_status_register_bp1_srwd, + .unlock = spi_disable_blockprotect_bp1_srwd, + .write = spi_chip_write_1, + .read = spi_chip_read, + .voltage = {1800, 5500}, + }, + { .vendor = "ST", .name = "M95M02", @@ -14816,7 +14843,7 @@ .model_id = ST_M95M02, .total_size = 256, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN | FEATURE_NO_ERASE | FEATURE_ERASED_ZERO, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_NO_ERASE | FEATURE_ERASED_ZERO | FEATURE_IDENTITY_MISSING, .tested = TEST_OK_PREW, .probe = probe_spi_st95, .probe_timing = TIMING_ZERO, @@ -15967,6 +15994,214 @@ .wrea_override = 0x17, }, +// { +// .vendor = "ST", +// .name = "M95040", +// .bustype = BUS_SPI, +// .manufacture_id = ST_ID, +// .model_id = ST_M95040, +// .total_size = 512, +// .page_size = 16, +// .feature_bits = FEATURE_WRSR_WREN | FEATURE_3_BYTE_ADDR_LEN| FEATURE_CAPACITY_IN_BYTE | FEATURE_IDENTITY_MISSING, +// .tested = TEST_UNTESTED, +// .probe = probe_spi_st95, +// .probe_timing = TIMING_ZERO, +// .block_erasers = +// { +// { +// .eraseblocks = { { 512 * 1, 1 } }, +// .block_erase = spi_block_erase_emulation, +// } +// }, +// .printlock = spi_prettyprint_status_register_bp1_srwd, +// .unlock = spi_disable_blockprotect_bp1_srwd, +// .write = spi_chip_write_1, +// .read = spi_chip_read, +// .voltage = {2500, 5500}, +// }, + + { + .vendor = "ST", + .name = "M95080", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M95080, + .total_size = 1, + .page_size = 32, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_3_BYTE_ADDR_LEN | FEATURE_IDENTITY_MISSING, + .tested = TEST_OK_PREW, + .probe = probe_spi_st95, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 1 * 1024, 1 } }, + .block_erase = spi_block_erase_emulation, + } + }, + .printlock = spi_prettyprint_status_register_bp1_srwd, + .unlock = spi_disable_blockprotect_bp1_srwd, + .write = spi_chip_write_1, + .read = spi_chip_read, + .voltage = {2500, 5500}, + }, + + { + .vendor = "ST", + .name = "M95160", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M95160, + .total_size = 2, + .page_size = 32, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_3_BYTE_ADDR_LEN | FEATURE_IDENTITY_MISSING, + .tested = TEST_OK_PREW, + .probe = probe_spi_st95, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 2 * 1024, 1 } }, + .block_erase = spi_block_erase_emulation, + } + }, + .printlock = spi_prettyprint_status_register_bp1_srwd, + .unlock = spi_disable_blockprotect_bp1_srwd, + .write = spi_chip_write_1, + .read = spi_chip_read, + .voltage = {2500, 5500}, + }, + + { + .vendor = "ST", + .name = "M95320", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M95320, + .total_size = 4, + .page_size = 32, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_3_BYTE_ADDR_LEN | FEATURE_IDENTITY_MISSING, + .tested = TEST_OK_PREW, + .probe = probe_spi_st95, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 4 * 1024, 1 } }, + .block_erase = spi_block_erase_emulation, + } + }, + .printlock = spi_prettyprint_status_register_bp1_srwd, + .unlock = spi_disable_blockprotect_bp1_srwd, + .write = spi_chip_write_1, + .read = spi_chip_read, + .voltage = {2500, 5500}, + }, + + { + .vendor = "ST", + .name = "M95640", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M95640, + .total_size = 8, + .page_size = 32, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_3_BYTE_ADDR_LEN | FEATURE_IDENTITY_MISSING, + .tested = TEST_OK_PREW, + .probe = probe_spi_st95, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 8 * 1024, 1 } }, + .block_erase = spi_block_erase_emulation, + } + }, + .printlock = spi_prettyprint_status_register_bp1_srwd, + .unlock = spi_disable_blockprotect_bp1_srwd, + .write = spi_chip_write_1, + .read = spi_chip_read, + .voltage = {2500, 5500}, + }, + + { + .vendor = "ST", + .name = "M95128", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M95128, + .total_size = 16, + .page_size = 64, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_3_BYTE_ADDR_LEN | FEATURE_IDENTITY_MISSING, + .tested = TEST_OK_PREW, + .probe = probe_spi_st95, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 16 * 1024, 1 } }, + .block_erase = spi_block_erase_emulation, + } + }, + .printlock = spi_prettyprint_status_register_bp1_srwd, + .unlock = spi_disable_blockprotect_bp1_srwd, + .write = spi_chip_write_1, + .read = spi_chip_read, + .voltage = {2500, 5500}, + }, + + { + .vendor = "ST", + .name = "M95256", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M95256, + .total_size = 32, + .page_size = 64, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_3_BYTE_ADDR_LEN | FEATURE_IDENTITY_MISSING, + .tested = TEST_OK_PREW, + .probe = probe_spi_st95, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 32 * 1024, 1 } }, + .block_erase = spi_block_erase_emulation, + } + }, + .printlock = spi_prettyprint_status_register_bp1_srwd, + .unlock = spi_disable_blockprotect_bp1_srwd, + .write = spi_chip_write_1, + .read = spi_chip_read, + .voltage = {2500, 5500}, + }, + + { + .vendor = "ST", + .name = "M95512", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M95512, + .total_size = 64, + .page_size = 128, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_3_BYTE_ADDR_LEN | FEATURE_IDENTITY_MISSING, + .tested = TEST_OK_PREW, + .probe = probe_spi_st95, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 64 * 1024, 1 } }, + .block_erase = spi_block_erase_emulation, + } + }, + .printlock = spi_prettyprint_status_register_bp1_srwd, + .unlock = spi_disable_blockprotect_bp1_srwd, + .write = spi_chip_write_1, + .read = spi_chip_read, + .voltage = {2500, 5500}, + }, + { .vendor = "SyncMOS/MoselVitelic", .name = "{F,S,V}29C51001B", diff --git a/flashchips.h b/flashchips.h index f02958c..755c3a5 100644 --- a/flashchips.h +++ b/flashchips.h @@ -853,9 +853,19 @@ #define ST_M58WR032KT 0x8814 #define ST_M58WR064KB 0x8811 #define ST_M58WR064KT 0x8810 - -#define ST_M95M02 0x0012 /* ST M95XXX 2Mbit (256KiB) */ - +/* 00h Memory Density code ST_ID*/ +/* 01h SPI Family code 0x00*/ +/* 02h Memory Density code ST_M95XXX */ +#define ST_M95040 0x0009 +#define ST_M95080 0x000A +#define ST_M95160 0x000B +#define ST_M95320 0x000C +#define ST_M95640 0x000D +#define ST_M95128 0x000E +#define ST_M95256 0x000F +#define ST_M95512 0x0010 /* FIXME: 0x0010 it's dummy cause don't mentioned in documentation. The device is delivered with the memory array and Identification Page bits set to all 1s (each byte = FFh).*/ +#define ST_M95M01 0x0011 /* FIXME: 0x0011 it's dummy cause don't mentioned in documentation. The device is delivered with the memory array and Identification Page bits set to all 1s (each byte = FFh).*/ +#define ST_M95M02 0x0012 /* ST M95XXX 2Mbit (256KiB) FIXME: 0x0012 Is this correct value? The device is delivered with the memory array and Identification Page bits set to all 1s (each byte = FFh). */ #define ST_MT28GU01G___1 0x88B0 #define ST_MT28GU01G___2 0x88B1 #define ST_MT28GU256___1 0x8901 diff --git a/flashrom.c b/flashrom.c index 2534e4a..8f5cd85 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1153,9 +1153,13 @@ /* We handle a forced match like a real match, we just avoid probing. Note that probe_flash() * is only called with force=1 after normal probing failed. */ - if (force) + if (force == 2) break; + if (force == 1 && chip->feature_bits & FEATURE_IDENTITY_MISSING) { + flash->flags.force = force; + } + if (flash->chip->probe(flash) != 1) goto notfound; @@ -1219,7 +1223,7 @@ } tmp = flashbuses_to_text(flash->chip->bustype); - msg_cinfo("%s %s flash chip \"%s\" (%d kB, %s) ", force ? "Assuming" : "Found", + msg_cinfo("%s %s flash chip \"%s\" (%d kB, %s) ", force == 2 ? "Assuming" : "Found", flash->chip->vendor, flash->chip->name, flash->chip->total_size, tmp); free(tmp); #if CONFIG_INTERNAL == 1 @@ -1555,7 +1559,7 @@ const struct romentry *entry = NULL; all_skipped = true; - msg_cinfo("Erasing and writing flash chip... "); + msg_cinfo("Erasing and writing flash chip...\n"); while ((entry = layout_next_included(layout, entry))) { info->region_start = entry->start; diff --git a/spi.h b/spi.h index 3f45038..64a07e6 100644 --- a/spi.h +++ b/spi.h @@ -21,6 +21,7 @@ */ #define JEDEC_MAX_ADDR_LEN 0x04 +#define JEDEC_3_BYTE_ADDR_LEN 0x03 /* Read Electronic ID */ #define JEDEC_RDID 0x9f @@ -28,12 +29,28 @@ /* INSIZE may be 0x04 for some chips*/ #define JEDEC_RDID_INSIZE 0x03 -/* Some ST M95X model */ -#define ST_M95_RDID 0x83 -#define ST_M95_RDID_3BA_OUTSIZE 0x04 /* 8b op, 24bit addr where size >64KiB */ -#define ST_M95_RDID_2BA_OUTSIZE 0x03 /* 8b op, 16bit addr where size <=64KiB */ -#define ST_M95_RDID_OUTSIZE_MAX 0x04 /* ST_M95_RDID_3BA_OUTSIZE */ -#define ST_M95_RDID_INSIZE 0x03 +/* Some ST M95X model */ +#define ST_M95_RDID 0x83 +#define ST_M95_RDID_OUTSIZE 0x03 +#define ST_M95_RDID_INSIZE 0x03 +#define ST_M95_RDLS 0x83 +#define ST_M95_RDLS_OUTSIZE 0x03 +#define ST_M95_RDLS_INSIZE 0x01 +#define ST_M95_RDSR 0x05 +#define ST_M95_RDSR_OUTSIZE 0x01 +#define ST_M95_RDSR_INSIZE 0x01 +#define ST_M95_READ 0x03 +#define ST_M95_READ_OUTSIZE 0x03 +#define ST_M95_READ_INSIZE 0x03 +#define ST_M95_WREN 0x06 +#define ST_M95_WREN_OUTSIZE 0x01 +#define ST_M95_WREN_INSIZE 0x00 +#define ST_M95_WRITE 0x02 +#define ST_M95_WRITE_OUTSIZE 0x06 +#define ST_M95_WRITE_INSIZE 0x03 +#define ST_M95_WRID 0x82 +#define ST_M95_WRID_OUTSIZE 0x06 +#define ST_M95_WRID_INSIZE 0x00 /* Some Atmel AT25F* models have bit 3 as don't care bit in commands */ #define AT25F_RDID 0x15 /* 0x15 or 0x1d */ diff --git a/spi25.c b/spi25.c index 2a1d492..3c0579a 100644 --- a/spi25.c +++ b/spi25.c @@ -21,6 +21,7 @@ #include <stddef.h> #include <string.h> #include <stdbool.h> +#include <stdlib.h> #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" @@ -262,6 +263,31 @@ return 1; } +/* Only used for some stm95 and higher chip. */ +int probe_spi_st95(struct flashctx *flash) +{ +// + static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; + unsigned char readarr[JEDEC_RDID_INSIZE]; + uint32_t manufacture_id; + uint32_t model_id; + + spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); + + manufacture_id = readarr[0]; + model_id = readarr[2]; + + msg_ginfo("RDID[%s: manID 0x%02x, modID 0x%02x, L 0x%02x, M 0x%02x, H 0x%02x]\n", __func__, flash->chip->manufacture_id, flash->chip->model_id, readarr[0], readarr[1], readarr[2]); + + if (manufacture_id == flash->chip->manufacture_id && model_id == flash->chip->model_id) + return 1; + + if (flash->flags.force) + return 1; + + return 0; +} + /* Only used for some Atmel chips. */ int probe_spi_at25f(struct flashctx *flash) { @@ -379,10 +405,16 @@ "with this chip/programmer combination.\n", cmd_buf[0]); return -1; } - cmd_buf[1] = (addr >> 16) & 0xff; - cmd_buf[2] = (addr >> 8) & 0xff; - cmd_buf[3] = (addr >> 0) & 0xff; - return 3; + if (flash->chip->feature_bits & FEATURE_3_BYTE_ADDR_LEN) { + cmd_buf[1] = (addr >> 8) & 0xff; + cmd_buf[2] = (addr >> 0) & 0xff; + return 2; + } else { + cmd_buf[1] = (addr >> 16) & 0xff; + cmd_buf[2] = (addr >> 8) & 0xff; + cmd_buf[3] = (addr >> 0) & 0xff; + return 3; + } } } @@ -405,7 +437,16 @@ const uint8_t *const out_bytes, const size_t out_len, const unsigned int poll_delay) { - uint8_t cmd[1 + JEDEC_MAX_ADDR_LEN + 256]; + const unsigned int cmd_len = 1 + (flash->chip->feature_bits & FEATURE_3_BYTE_ADDR_LEN ? JEDEC_3_BYTE_ADDR_LEN : JEDEC_MAX_ADDR_LEN) + 256; + uint8_t *cmd = NULL; + + cmd = (uint8_t*) malloc(cmd_len * sizeof(uint8_t)); + if (!cmd) { + msg_cerr("Out of memory!\n"); + return 1; + } + memset(cmd,0x00, cmd_len * sizeof(uint8_t)); + struct spi_command cmds[] = { { .readarr = 0, @@ -423,7 +464,7 @@ if (addr_len < 0) return 1; - if (1 + addr_len + out_len > sizeof(cmd)) { + if (1 + addr_len + out_len > cmd_len) { msg_cerr("%s called for too long a write\n", __func__); return 1; } @@ -436,6 +477,7 @@ msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); const int status = spi_poll_wip(flash, poll_delay); + free(cmd); return result ? result : status; } @@ -577,6 +619,26 @@ return spi_write_cmd(flash, 0xdc, true, addr, NULL, 0, 100 * 1000); } +/* ST95XXX chips don't have an erase operation and erase is made as part of write command */ +int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigned int blocklen) +{ + uint8_t *erased_contents = NULL; + int result = 0; + + erased_contents = (uint8_t *)malloc(blocklen * sizeof(uint8_t)); + if (!erased_contents) { + msg_cerr("Out of memory!\n"); + return 1; + } + memset(erased_contents, ERASED_VALUE(flash), blocklen * sizeof(uint8_t)); + msg_cinfo("\nIt takes too long!\n"); + + result = spi_write_chunked(flash, erased_contents, 0, blocklen, flash->chip->page_size); + free(erased_contents); + + return result; +} + erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode) { switch(opcode){ @@ -630,14 +692,28 @@ unsigned int len) { const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_READ && spi_master_4ba(flash); - uint8_t cmd[1 + JEDEC_MAX_ADDR_LEN] = { native_4ba ? JEDEC_READ_4BA : JEDEC_READ, }; + const unsigned int cmd_len = 1 + (flash->chip->feature_bits & FEATURE_3_BYTE_ADDR_LEN ? JEDEC_3_BYTE_ADDR_LEN : JEDEC_MAX_ADDR_LEN); + int result; + uint8_t *cmd = NULL; + + cmd = (uint8_t*) malloc(cmd_len * sizeof(uint8_t)); + if (!cmd) { + msg_cerr("Out of memory!\n"); + return 1; + } + memset(cmd, 0x00, cmd_len * sizeof(uint8_t)); + + cmd[0] = native_4ba ? JEDEC_READ_4BA : JEDEC_READ; const int addr_len = spi_prepare_address(flash, cmd, native_4ba, address); if (addr_len < 0) return 1; /* Send Read */ - return spi_send_command(flash, 1 + addr_len, len, cmd, bytes); + result = spi_send_command(flash, 1 + addr_len, len, cmd, bytes); + free(cmd); + + return result; } /* diff --git a/spi95.c b/spi95.c deleted file mode 100644 index ecb2c1d..0000000 --- a/spi95.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the flashrom project. - * - * Copyright (C) 2019 Konstantin Grudnev - * Copyright (C) 2019 Nikolay Nikolaev - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, - * or any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Contains SPI chip driver functions related to ST95XXX series (SPI EEPROM) - */ -#include <string.h> -#include <stdlib.h> -#include "flashchips.h" -#include "chipdrivers.h" -#include "spi.h" - -/* For ST95XXX chips which have RDID */ -int probe_spi_st95(struct flashctx *flash) -{ - /* - * ST_M95_RDID_OUTSIZE depends on size of the flash and - * not all ST_M95XXX have RDID. - */ - static const unsigned char cmd[ST_M95_RDID_OUTSIZE_MAX] = { ST_M95_RDID }; - unsigned char readarr[ST_M95_RDID_INSIZE]; - uint32_t id1, id2; - - uint32_t rdid_outsize = ST_M95_RDID_2BA_OUTSIZE; // 16 bit address - if (flash->chip->total_size * KiB > 64 * KiB) - rdid_outsize = ST_M95_RDID_3BA_OUTSIZE; // 24 bit address - - spi_send_command(flash, rdid_outsize, sizeof(readarr), cmd, readarr); - - id1 = readarr[0]; // manufacture id - id2 = (readarr[1] << 8) | readarr[2]; // SPI family code + model id - - msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); - - if (id1 == flash->chip->manufacture_id && id2 == flash->chip->model_id) - return 1; - - return 0; -} - -/* ST95XXX chips don't have erase operation and erase is made as part of write command */ -int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigned int blocklen) -{ - uint8_t *erased_contents = NULL; - int result = 0; - - erased_contents = (uint8_t *)malloc(blocklen * sizeof(uint8_t)); - if (!erased_contents) { - msg_cerr("Out of memory!\n"); - return 1; - } - memset(erased_contents, ERASED_VALUE(flash), blocklen * sizeof(uint8_t)); - result = spi_write_chunked(flash, erased_contents, 0, blocklen, flash->chip->page_size); - free(erased_contents); - return result; -} -- To view, visit https://review.coreboot.org/c/flashrom/+/37893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4a983a2f375c7023d28b9e762d24b44566e59612 Gerrit-Change-Number: 37893 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

1 year, 11 months

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Change in ...flashrom[master]: Add "--dangerous-bruteforce" mode for the unreliable ISP environments

by mikeb mikeb (Code Review)

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/31830 to review the following change. Change subject: Add "--dangerous-bruteforce" mode for the unreliable ISP environments ...................................................................... Add "--dangerous-bruteforce" mode for the unreliable ISP environments Some in-system-programming environments are very unreliable, e.g. when you connect a SOIC8 test clip to the flash chip of WR841ND v9 wireless router: because the low power SOC of this router becomes powered and is constantly trying to boot, the router's flash chip is correctly detected only 30% of times, and when it is detected just 30% of the read operations are successful - the rest result in zeroes or garbage data being read from a flash chip. While in this new "--dangerous-bruteforce" mode, flashrom will be constantly probing for a flash chip until it is correctly detected - and then, depending on the operation selected by a user, at the moments of chip availability it will be reading or writing by the small chunks of 256 bytes maximum size, verifying each small chunk and retrying the operation until the success or timeout (~ 60 sec). Constant probing between the small chunk operations is also being done - to avoid a possible situation where we have got two identical blocks of zeroes while reading a chunk and erroneously accepted it. Currently this mode is active only for those SPI25 chips which are ".write = spi_chip_write_256" and ".read = spi_chip_read", but later could be expanded to more functions to become useful for more chips. NOTE: this mode is experimental! Also, some targets like WR841ND v9 could block the ISP chip access completely if there is no bootable firmware inside (e.g. after you've tried to erase the chip contents). In such a situation it could be hard to recover the firmware without desoldering a flash chip and flashing it separately. Please do not erase or write to a flash chip using this mode if you are not sure. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: If47476793721a0061fd65bc6d1f98d48b03dc6c1 --- M cli_classic.c M flash.h M flashrom.c M libflashrom.c M libflashrom.h M spi25.c 6 files changed, 148 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/30/31830/1 diff --git a/cli_classic.c b/cli_classic.c index ced08c6..454df2b 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -51,6 +51,7 @@ " -V | --verbose more verbose output\n" " -c | --chip <chipname> probe only for specified flash chip\n" " -f | --force force specific operations (see man page)\n" + " --dangerous-bruteforce verify each small chunk and probe constantly\n" " -n | --noverify don't auto-verify\n" " -N | --noverify-all verify included regions only (cf. -i)\n" " -l | --layout <layoutfile> read ROM layout from <layoutfile>\n" @@ -104,7 +105,7 @@ #if CONFIG_PRINT_WIKI == 1 int list_supported_wiki = 0; #endif - int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; + int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0, bruteforce = 0, timeout = 30000; int dont_verify_it = 0, dont_verify_all = 0, list_supported = 0, operation_specified = 0; struct flashrom_layout *layout = NULL; enum programmer prog = PROGRAMMER_INVALID; @@ -113,6 +114,7 @@ OPTION_FMAP, OPTION_FMAP_FILE, OPTION_FLASH_CONTENTS, + OPTION_BRUTEFORCE, }; int ret = 0; @@ -127,6 +129,7 @@ {"chip", 1, NULL, 'c'}, {"verbose", 0, NULL, 'V'}, {"force", 0, NULL, 'f'}, + {"dangerous-bruteforce", 0, NULL, OPTION_BRUTEFORCE}, {"layout", 1, NULL, 'l'}, {"ifd", 0, NULL, OPTION_IFD}, {"fmap", 0, NULL, OPTION_FMAP}, @@ -228,6 +231,9 @@ case 'f': force = 1; break; + case OPTION_BRUTEFORCE: + bruteforce = 1; + break; case 'l': if (layoutfile) { fprintf(stderr, "Error: --layout specified " @@ -503,16 +509,27 @@ msg_pdbg("The following protocols are supported: %s.\n", tempstr); free(tempstr); - for (j = 0; j < registered_master_count; j++) { - startchip = 0; - while (chipcount < ARRAY_SIZE(flashes)) { - startchip = probe_flash(&registered_masters[j], startchip, &flashes[chipcount], 0); - if (startchip == -1) - break; - chipcount++; - startchip++; + do { + chipcount = 0; + for (j = 0; j < registered_master_count; j++) { + startchip = 0; + while (chipcount < ARRAY_SIZE(flashes)) { + startchip = probe_flash(&registered_masters[j], startchip, &flashes[chipcount], 0); + if (startchip == -1) + break; + chipcount++; + startchip++; + } } - } + timeout--; + if (!timeout) { + msg_cerr("Error: Timed out trying to detect a chip.\n"); + ret = 1; + goto out_shutdown; + } + } while (bruteforce && ( !chipcount || // wait for the correct chip detection + ((flashes[0].chip->manufacture_id == GENERIC_MANUF_ID) || + (flashes[0].chip->model_id == GENERIC_DEVICE_ID)) ) ); if (chipcount > 1) { msg_cinfo("Multiple flash chip definitions match the detected chip(s): \"%s\"", @@ -650,6 +667,7 @@ #if CONFIG_INTERNAL == 1 flashrom_flag_set(fill_flash, FLASHROM_FLAG_FORCE_BOARDMISMATCH, !!force_boardmismatch); #endif + flashrom_flag_set(fill_flash, FLASHROM_FLAG_BRUTEFORCE, !!bruteforce); flashrom_flag_set(fill_flash, FLASHROM_FLAG_VERIFY_AFTER_WRITE, !dont_verify_it); flashrom_flag_set(fill_flash, FLASHROM_FLAG_VERIFY_WHOLE_CHIP, !dont_verify_all); diff --git a/flash.h b/flash.h index 911214c..6ba116e 100644 --- a/flash.h +++ b/flash.h @@ -256,6 +256,7 @@ struct { bool force; bool force_boardmismatch; + bool bruteforce; bool verify_after_write; bool verify_whole_chip; } flags; diff --git a/flashrom.c b/flashrom.c index e82c32e..8f2c859 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1641,6 +1641,8 @@ size_t i, j; bool first = true; struct block_eraser *const eraser = &flashctx->chip->block_erasers[erasefunction]; + unsigned int bruteforce = flashrom_flag_get(flashctx, FLASHROM_FLAG_BRUTEFORCE); + int timeout; info->erase_start = 0; for (i = 0; i < NUM_ERASEREGIONS; ++i) { @@ -1662,9 +1664,34 @@ msg_cdbg(", "); msg_cdbg("0x%06x-0x%06x:", info->erase_start, info->erase_end); - ret = per_blockfn(flashctx, info, eraser->block_erase); - if (ret) - return ret; + if (!bruteforce) { + ret = per_blockfn(flashctx, info, eraser->block_erase); + if (ret) + return ret; + } else { + timeout = 30000; + while(1) { + timeout--; + if (!timeout) { + msg_cerr("%s timeout during command execution\n", __func__); + return 2; + } + + /* First probe. */ + if (flashctx->chip->probe(flashctx) != 1) + continue; + + ret = per_blockfn(flashctx, info, eraser->block_erase); + if (ret) + continue; + + /* Second probe. */ + if (flashctx->chip->probe(flashctx) != 1) + continue; + + break; + } + } } if (info->region_end < info->erase_start) break; diff --git a/libflashrom.c b/libflashrom.c index f90a22c..6dd0167 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -250,6 +250,7 @@ switch (flag) { case FLASHROM_FLAG_FORCE: flashctx->flags.force = value; break; case FLASHROM_FLAG_FORCE_BOARDMISMATCH: flashctx->flags.force_boardmismatch = value; break; + case FLASHROM_FLAG_BRUTEFORCE: flashctx->flags.bruteforce = value; break; case FLASHROM_FLAG_VERIFY_AFTER_WRITE: flashctx->flags.verify_after_write = value; break; case FLASHROM_FLAG_VERIFY_WHOLE_CHIP: flashctx->flags.verify_whole_chip = value; break; } @@ -267,6 +268,7 @@ switch (flag) { case FLASHROM_FLAG_FORCE: return flashctx->flags.force; case FLASHROM_FLAG_FORCE_BOARDMISMATCH: return flashctx->flags.force_boardmismatch; + case FLASHROM_FLAG_BRUTEFORCE: return flashctx->flags.bruteforce; case FLASHROM_FLAG_VERIFY_AFTER_WRITE: return flashctx->flags.verify_after_write; case FLASHROM_FLAG_VERIFY_WHOLE_CHIP: return flashctx->flags.verify_whole_chip; default: return false; diff --git a/libflashrom.h b/libflashrom.h index 38c95d2..0f2ead8 100644 --- a/libflashrom.h +++ b/libflashrom.h @@ -51,6 +51,7 @@ enum flashrom_flag { FLASHROM_FLAG_FORCE, FLASHROM_FLAG_FORCE_BOARDMISMATCH, + FLASHROM_FLAG_BRUTEFORCE, FLASHROM_FLAG_VERIFY_AFTER_WRITE, FLASHROM_FLAG_VERIFY_WHOLE_CHIP, }; diff --git a/spi25.c b/spi25.c index 8b6c462..832c836 100644 --- a/spi25.c +++ b/spi25.c @@ -21,6 +21,7 @@ #include <stddef.h> #include <string.h> #include <stdbool.h> +#include <stdlib.h> #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" @@ -655,6 +656,48 @@ return spi_send_command(flash, 1 + addr_len, len, cmd, bytes); } +static int spi_rw_bruteforce(struct flashctx *flash, uint8_t *buf1, uint8_t *buf2, + unsigned int startrw_here, unsigned int torw_len, bool rw_flag) { + int rc = 0; + int timeout = 30000; + while (1) { + timeout--; + if (!timeout) { + msg_cerr("%s timeout during command execution\n", __func__); + return -1; + } + + /* First probe. */ + if (flash->chip->probe(flash) != 1) + continue; + + /* First operation. */ + if (rw_flag == 0) + rc = spi_nbyte_read(flash, startrw_here, buf1, torw_len); + else + rc = spi_nbyte_program(flash, startrw_here, buf1, torw_len); + + if (rc != 0) + break; + + /* Second probe. */ + if (flash->chip->probe(flash) != 1) + continue; + + /* Second operation. */ + rc = spi_nbyte_read(flash, startrw_here, buf2, torw_len); + if (rc != 0) + break; + + /* Compare two buffers. */ + if (memcmp(buf1, buf2, torw_len)) + continue; + + break; + } + return rc; +} + /* * Read a part of the flash chip. * FIXME: Use the chunk code from Michael Karcher instead. @@ -668,6 +711,19 @@ /* Limit for multi-die 4-byte-addressing chips. */ unsigned int area_size = min(flash->chip->total_size * 1024, 16 * 1024 * 1024); + unsigned int bruteforce = flashrom_flag_get(flash, FLASHROM_FLAG_BRUTEFORCE); + uint8_t *const buf1 = bruteforce ? malloc(chunksize) : NULL; + uint8_t *const buf2 = bruteforce ? malloc(chunksize) : NULL; + + if (bruteforce) { + if (!buf1 || !buf2) { + msg_gerr("Out of memory!\n"); + goto _free_ret; + } + msg_cdbg("spi_read_chunked: chunksize %i ---> %i\n", chunksize, min(chunksize, 256)); + chunksize = min(chunksize, 256); + } + /* Warning: This loop has a very unusual condition and body. * The loop needs to go through each area with at least one affected * byte. The lowest area number is (start / area_size) since that @@ -685,7 +741,11 @@ lenhere = min(start + len, (i + 1) * area_size) - starthere; for (j = 0; j < lenhere; j += chunksize) { toread = min(chunksize, lenhere - j); - rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread); + if (bruteforce) { + rc = spi_rw_bruteforce(flash, buf1, buf2, starthere + j, toread, 0 /* read */); + memcpy(buf + starthere - start + j, buf1, toread); + } else + rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread); if (rc) break; } @@ -693,6 +753,9 @@ break; } +_free_ret: + free(buf1); + free(buf2); return rc; } @@ -712,6 +775,19 @@ */ unsigned int page_size = flash->chip->page_size; + unsigned int bruteforce = flashrom_flag_get(flash, FLASHROM_FLAG_BRUTEFORCE); + uint8_t *const buf1 = bruteforce ? malloc(chunksize) : NULL; + uint8_t *const buf2 = bruteforce ? malloc(chunksize) : NULL; + + if (bruteforce) { + if (!buf1 || !buf2) { + msg_gerr("Out of memory!\n"); + goto _free_ret; + } + msg_cdbg("spi_write_chunked: chunksize %i ---> %i\n", chunksize, min(chunksize, 256)); + chunksize = min(chunksize, 256); + } + /* Warning: This loop has a very unusual condition and body. * The loop needs to go through each page with at least one affected * byte. The lowest page number is (start / page_size) since that @@ -731,12 +807,20 @@ int rc; towrite = min(chunksize, lenhere - j); - rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite); + if (bruteforce) { + memcpy(buf1, buf + starthere - start + j, towrite); + rc = spi_rw_bruteforce(flash, buf1, buf2, starthere + j, towrite, 1 /* write */); + } else + rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite); + if (rc) return rc; } } +_free_ret: + free(buf1); + free(buf2); return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/31830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If47476793721a0061fd65bc6d1f98d48b03dc6c1 Gerrit-Change-Number: 31830 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: chipset_enable.c: Mark Intel HM76 as DEP

by Angel Pons (Code Review)

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/37803 ) Change subject: chipset_enable.c: Mark Intel HM76 as DEP ...................................................................... chipset_enable.c: Mark Intel HM76 as DEP Tested reading, writing and erasing the internal flash chip using a Samsung NP530U3C laptop with an Intel HM76 PCH. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well. Change-Id: I1097c5fcf782e7ecf52f05c571ad188456307d00 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/03/37803/1 diff --git a/chipset_enable.c b/chipset_enable.c index b55852c..e826d90 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1831,7 +1831,7 @@ {0x8086, 0x1e56, B_FS, DEP, "Intel", "QS77", enable_flash_pch7}, {0x8086, 0x1e57, B_FS, DEP, "Intel", "HM77", enable_flash_pch7}, {0x8086, 0x1e58, B_FS, NT, "Intel", "UM77", enable_flash_pch7}, - {0x8086, 0x1e59, B_FS, NT, "Intel", "HM76", enable_flash_pch7}, + {0x8086, 0x1e59, B_FS, DEP, "Intel", "HM76", enable_flash_pch7}, {0x8086, 0x1e5d, B_FS, NT, "Intel", "HM75", enable_flash_pch7}, {0x8086, 0x1e5e, B_FS, NT, "Intel", "HM70", enable_flash_pch7}, {0x8086, 0x1e5f, B_FS, DEP, "Intel", "NM70", enable_flash_pch7}, -- To view, visit https://review.coreboot.org/c/flashrom/+/37803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1097c5fcf782e7ecf52f05c571ad188456307d00 Gerrit-Change-Number: 37803 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: mysteries_intel: Add a section about SMM_BWP

by David Hendricks (Code Review)

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36986 ) Change subject: mysteries_intel: Add a section about SMM_BWP ...................................................................... mysteries_intel: Add a section about SMM_BWP Something to point users to when SMM_BWP might be causing problems. Change-Id: I394c033e8d4ff96433162f86aefb428d8acf6349 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M Documentation/mysteries_intel.txt 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/86/36986/1 diff --git a/Documentation/mysteries_intel.txt b/Documentation/mysteries_intel.txt index 10cb37d..d6ceb6a 100644 --- a/Documentation/mysteries_intel.txt +++ b/Documentation/mysteries_intel.txt @@ -5,6 +5,25 @@ A0h), so we have no clue if or where it is on ICH8. Out current policy is to not touch it at all and assume/hope it is 0. += SMM BIOS write protection = +Sometimes a hardware vendor will enable "SMM BIOS Write Protect" (SMM_BWP). +The bits that control this are in the BIOS_CNTL register in the LPC interface. + +When enabled, the SPI flash can only be written when the system is operating in +in System Management Mode (SMM). In other words, only code that was installed by +the BIOS can write to the flash chip. Reads are still possible with code that +runs outside of SMM, such as flashrom. + +Flashrom will attempt to detect this and print a message such as the following: +"Warning: BIOS region SMM protection is enabled!" + +Many vendor-supplied firmware update utilities do not actually write to the ROM; +instead they transfer data to/from memory which is read/written by a routine +running in SMM and is responsible for writing to the firmware ROM. This causes +severe system performance degradataion since all processors must be in SMM +context (ring -2) instead of OS context (ring 0) while the firmware ROM is being +written. + = Accesses beyond region bounds in descriptor mode = Intel's flash image tool will always expand the last region so that it covers the whole flash chip, but some boards ship with a different configuration. -- To view, visit https://review.coreboot.org/c/flashrom/+/36986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I394c033e8d4ff96433162f86aefb428d8acf6349 Gerrit-Change-Number: 36986 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

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flashrom-gerrit December 2019